ELF/AArch64: Fix R_AARCH64_LDST16_ABS_LO12_NC mask

[zatrazz]

Summary

The relocation R_AARCH64_LDST16_ABS_LO12_NC should set a ld/st
immediate value to bits [11:1] not [11:2]. This patches fixes it
and adds a testcase for regression.

With this fix all the faulty tests on test-suite (clavm, lencod,
and trimaran) pass.

[meadori]

LGTM. It is constant with my understanding of: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056b/IHI0056B_aaelf64.pdf

In looking at the surrounding similar relocations, shouldn't R_AARCH64_LDST128_ABS_LO12_NC be 0xFF0?

[ruiu]

LGTM

[zatrazz]

In D27308#612006, @meadori wrote:

LGTM. It is constant with my understanding of: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0056b/IHI0056B_aaelf64.pdf

In looking at the surrounding similar relocations, shouldn't R_AARCH64_LDST128_ABS_LO12_NC be 0xFF0?

Yes, this is on my list. I am struggling to create a testcase that triggers an issue with correct invalid mask.

ELF/Target.cpp

void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
   case R_AARCH64_TLSDESC_LD64_LO12_NC:
     checkAlignment<8>(Loc, Val, Type);
     or32le(Loc, (Val & 0xFF8) << 7);
     break;
   case R_AARCH64_LDST128_ABS_LO12_NC:
     or32le(Loc, (Val & 0x0FF8) << 6);
     break;
   case R_AARCH64_LDST16_ABS_LO12_NC:
-    or32le(Loc, (Val & 0x0FFC) << 9);
+    or32le(Loc, (Val & 0x0FFE) << 9);
     break;
   case R_AARCH64_LDST8_ABS_LO12_NC:
     or32le(Loc, (Val & 0xFFF) << 10);
     break;
   case R_AARCH64_LDST32_ABS_LO12_NC:
     or32le(Loc, (Val & 0xFFC) << 8);
     break;
   case R_AARCH64_LDST64_ABS_LO12_NC:

test/ELF/aarch64-relocs.s

 # CHECK: ldst128:
 # CHECK:   2004c:       74 16 c0 3d     ldr     q20, [x19, #80]
 #foo128:
 #   20050:       66 6f 6f 00     .word
 
 .section .R_AARCH64_LDST16_ABS_LO12_NC,"ax",@progbits
 ldst16:
   ldr h17, [x19, :lo12:foo16]
+  ldrh w1, [x19, :lo12:foo16]
+  ldrh w2, [x19, :lo12:foo16 + 2]
 foo16:
   .asciz "foo"
-  .size mystr, 3
+  .size mystr, 4
 
 # S = 0x20054, A = 0x4
 # R = ((S + A) & 0x0FFC) << 9 = 0xb000
 # 0xb000 | 0x7d400271 = 0x7d40b271
 # CHECK: Disassembly of section .R_AARCH64_LDST16_ABS_LO12_NC:
 # CHECK-NEXT: ldst16:
-# CHECK-NEXT:   20054:       71 b2 40 7d     ldr     h17, [x19, #88]
+# CHECK-NEXT:   20054:       71 c2 40 7d     ldr     h17, [x19, #96]
+# CHECK-NEXT:   20058:       61 c2 40 79     ldrh    w1, [x19, #96]
+# CHECK-NEXT:   2005c:       62 c6 40 79     ldrh    w2, [x19, #98]
 
 .section .R_AARCH64_MOVW_UABS,"ax",@progbits
 movz1:
    movk x12, #:abs_g0_nc:uabs_label
    movk x13, #:abs_g1_nc:uabs_label
    movk x14, #:abs_g2_nc:uabs_label
    movz x15, #:abs_g3:uabs_label
    movk x16, #:abs_g3:uabs_label