[AArch64] allow and-not-compare transform to form 'bics'

[spatel]

Summary

This target hook was added with D19087, and I expected AArch64 to enable it. But nobody has gotten to it yet, and this is blocking another and-not transform that I'd like to add.

lib/Target/AArch64/AArch64ISelLowering.h

public:
   bool isCheapToSpeculateCttz() const override {
     return true;
   }
 
   bool isCheapToSpeculateCtlz() const override {
     return true;
   }
 
+  bool hasAndNotCompare(SDValue) const override {
+    // 'bics'
+    return true;
+  }
+
   bool hasBitPreservingFPLogic(EVT VT) const override {
     // FIXME: Is this always true? It should be true for vectors at least.
     return VT == MVT::f32 || VT == MVT::f64;
   }
 
   bool supportSplitCSR(MachineFunction *MF) const override {
     return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
            MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);

test/CodeGen/AArch64/bics.ll

 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
 
 define i1 @andn_cmp(i32 %x, i32 %y) {
 ; CHECK-LABEL: andn_cmp:
 ; CHECK:       // BB#0:
 ; CHECK-NEXT:    bics wzr, w1, w0
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 ;
   %notx = xor i32 %x, -1
   %and = and i32 %notx, %y
   %cmp = icmp eq i32 %and, 0
   ret i1 %cmp
 }
 
-; FIXME: Recognize a disguised bics.
-
 define i1 @and_cmp(i32 %x, i32 %y) {
 ; CHECK-LABEL: and_cmp:
 ; CHECK:       // BB#0:
-; CHECK-NEXT:    and w8, w0, w1
-; CHECK-NEXT:    cmp w8, w1
+; CHECK-NEXT:    bics wzr, w1, w0
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 ;
   %and = and i32 %x, %y
   %cmp = icmp eq i32 %and, %y
   ret i1 %cmp
 }
 
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
 ; CHECK:       // BB#0:
 ; CHECK-NEXT:    mov w8, #43
-; CHECK-NEXT:    and w8, w0, w8
-; CHECK-NEXT:    cmp w8, #43
+; CHECK-NEXT:    bics wzr, w8, w0
 ; CHECK-NEXT:    cset w0, eq
 ; CHECK-NEXT:    ret
 ;
   %and = and i32 %x, 43
   %cmp = icmp eq i32 %and, 43
   ret i1 %cmp
 }