TII: add hook getInstrOperandImmValue.

[SjoerdMeijer]

Summary

TII: add hook getInstrOperandImmValue. This is refactored from the Hexagon backend, which has been changed accordingly; this is change is intended to be NFC. This target hook is some more groundwork for recognising loop induction statement and trip counts for MachineLoops.

[qcolombet]

include/llvm/Target/TargetInstrInfo.h

1144

MI is probably useless given it is accessible through MO.getParent(), unless it represents something else and in that case it must be documented.

1144

Val should probably be an APInt.

1144

If this is a compile time known constant, why this is not directly MO_Immediate?
What am I saying is in which cases do we need that API?

[kparzysz]

include/llvm/Target/TargetInstrInfo.h

1144

The intent was to evaluate the value of the operand at compile-time: for immediate operands that is trivial, for registers the function would look up their definitions, etc.

[qcolombet]

include/llvm/Target/TargetInstrInfo.h

1144

I see.
One thing that you didn't address is why does the API have both MI and MO?

[arsenm]

include/llvm/Target/TargetInstrInfo.h

1144

I thought there was a vague desire to remove the parent from MachineOperands someday to save memory

[SjoerdMeijer]

include/llvm/Target/TargetInstrInfo.h

1144

I think I added the MI here (so that the API has both the MI and MO). But for no real good reason, other than perhaps consistency that most TII functions take a MI. Will remove it from since MO->getParent() will also give access to it.

[SjoerdMeijer]

Abandoning as the approach is not generic enough, see also https://reviews.llvm.org/D27193

include/llvm/Target/TargetInstrInfo.h

public:
   /// Returns true if the first specified predicate
   /// subsumes the second, e.g. GE subsumes GT.
   virtual
   bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
                          ArrayRef<MachineOperand> Pred2) const {
     return false;
   }
 
+  /// Check if the given operand has a compile-time known constant
+  /// value. Return true if yes, and false otherwise. When returning true, set
+  /// Val to the corresponding constant value.
+  virtual bool getInstrOperandImmValue(const MachineInstr &MI,
+                                       const MachineOperand &MO,
+                                       int64_t &Val) const {
+    return false;
+  }
+
   /// If the specified instruction defines any predicate
   /// or condition code register(s) used for predication, returns true as well
   /// as the definition predicate(s) by reference.
   virtual bool DefinesPredicate(MachineInstr &MI,
                                 std::vector<MachineOperand> &Pred) const {
     return false;
   }
 

lib/Target/Hexagon/HexagonHardwareLoops.cpp

private:
 
     /// \brief Return true if the induction variable may underflow an unsigned
     /// value in the first iteration.
     bool loopCountMayWrapOrUnderFlow(const MachineOperand *InitVal,
                                      const MachineOperand *EndVal,
                                      MachineBasicBlock *MBB, MachineLoop *L,
                                      LoopFeederMap &LoopFeederPhi) const;
 
-    /// \brief Check if the given operand has a compile-time known constant
-    /// value. Return true if yes, and false otherwise. When returning true, set
-    /// Val to the corresponding constant value.
-    bool checkForImmediate(const MachineOperand &MO, int64_t &Val) const;
-
     /// \brief Check if the operand has a compile-time known constant value.
-    bool isImmediate(const MachineOperand &MO) const {
+    bool isImmediate(const HexagonInstrInfo *TII,
+                     const MachineOperand &MO) const {
       int64_t V;
-      return checkForImmediate(MO, V);
+      return TII->getInstrOperandImmValue(*MO.getParent(), MO, V);
     }
 
     /// \brief Return the immediate for the specified operand.
-    int64_t getImmediate(const MachineOperand &MO) const {
+    int64_t getImmediate(const HexagonInstrInfo *TII,
+                         const MachineOperand &MO) const {
       int64_t V;
-      if (!checkForImmediate(MO, V))
+      if (!TII->getInstrOperandImmValue(*MO.getParent(), MO, V))
         llvm_unreachable("Invalid operand");
       return V;
     }
 
     /// \brief Reset the given machine operand to now refer to a new immediate
     /// value.  Assumes that the operand was already referencing an immediate
     /// value, either directly, or via a register.
     void setImmediate(MachineOperand &MO, int64_t Val);
for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
       MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
 
       if (DI->getDesc().isAdd()) {
         // If the register operand to the add is the PHI we're looking at, this
         // meets the induction pattern.
         unsigned IndReg = DI->getOperand(1).getReg();
         MachineOperand &Opnd2 = DI->getOperand(2);
         int64_t V;
-        if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
+        if (MRI->getVRegDef(IndReg) == Phi &&
+            TII->getInstrOperandImmValue(*DI, Opnd2, V)) {
           unsigned UpdReg = DI->getOperand(0).getReg();
           IndMap.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
         }
       }
     }  // for (i)
   }  // for (instr)
 
   SmallVector<MachineOperand,2> Cond;
if (!InitVal->isReg())
     return false;
 
   if (!EndVal->isImm())
     return false;
 
   // A register value that is assigned an immediate is a known value, and it
   // won't underflow in the first iteration.
   int64_t Imm;
-  if (checkForImmediate(*InitVal, Imm))
+  if (TII->getInstrOperandImmValue(*InitVal->getParent(), *InitVal, Imm))
     return (EndVal->getImm() == Imm);
 
   unsigned Reg = InitVal->getReg();
 
   // We don't know the value of a physical register.
   if (!TargetRegisterInfo::isVirtualRegister(Reg))
     return true;
 
bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
   // the instructions performed on the initial value. This works on the simplest
   // cases only.
   if (!Def->isCopy() && !Def->isPHI())
     return false;
 
   return true;
 }
 
-bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
-                                             int64_t &Val) const {
-  if (MO.isImm()) {
-    Val = MO.getImm();
-    return true;
-  }
-  if (!MO.isReg())
-    return false;
-
-  // MO is a register. Check whether it is defined as an immediate value,
-  // and if so, get the value of it in TV. That value will then need to be
-  // processed to handle potential subregisters in MO.
-  int64_t TV;
-
-  unsigned R = MO.getReg();
-  if (!TargetRegisterInfo::isVirtualRegister(R))
-    return false;
-  MachineInstr *DI = MRI->getVRegDef(R);
-  unsigned DOpc = DI->getOpcode();
-  switch (DOpc) {
-    case TargetOpcode::COPY:
-    case Hexagon::A2_tfrsi:
-    case Hexagon::A2_tfrpi:
-    case Hexagon::CONST32:
-    case Hexagon::CONST64: {
-      // Call recursively to avoid an extra check whether operand(1) is
-      // indeed an immediate (it could be a global address, for example),
-      // plus we can handle COPY at the same time.
-      if (!checkForImmediate(DI->getOperand(1), TV))
-        return false;
-      break;
-    }
-    case Hexagon::A2_combineii:
-    case Hexagon::A4_combineir:
-    case Hexagon::A4_combineii:
-    case Hexagon::A4_combineri:
-    case Hexagon::A2_combinew: {
-      const MachineOperand &S1 = DI->getOperand(1);
-      const MachineOperand &S2 = DI->getOperand(2);
-      int64_t V1, V2;
-      if (!checkForImmediate(S1, V1) || !checkForImmediate(S2, V2))
-        return false;
-      TV = V2 | (V1 << 32);
-      break;
-    }
-    case TargetOpcode::REG_SEQUENCE: {
-      const MachineOperand &S1 = DI->getOperand(1);
-      const MachineOperand &S3 = DI->getOperand(3);
-      int64_t V1, V3;
-      if (!checkForImmediate(S1, V1) || !checkForImmediate(S3, V3))
-        return false;
-      unsigned Sub2 = DI->getOperand(2).getImm();
-      unsigned Sub4 = DI->getOperand(4).getImm();
-      if (Sub2 == Hexagon::isub_lo && Sub4 == Hexagon::isub_hi)
-        TV = V1 | (V3 << 32);
-      else if (Sub2 == Hexagon::isub_hi && Sub4 == Hexagon::isub_lo)
-        TV = V3 | (V1 << 32);
-      else
-        llvm_unreachable("Unexpected form of REG_SEQUENCE");
-      break;
-    }
-
-    default:
-      return false;
-  }
-
-  // By now, we should have successfully obtained the immediate value defining
-  // the register referenced in MO. Handle a potential use of a subregister.
-  switch (MO.getSubReg()) {
-    case Hexagon::isub_lo:
-      Val = TV & 0xFFFFFFFFULL;
-      break;
-    case Hexagon::isub_hi:
-      Val = (TV >> 32) & 0xFFFFFFFFULL;
-      break;
-    default:
-      Val = TV;
-      break;
-  }
-  return true;
-}
-
 void HexagonHardwareLoops::setImmediate(MachineOperand &MO, int64_t Val) {
   if (MO.isImm()) {
     MO.setImm(Val);
     return;
   }
 
   assert(MO.isReg());
   unsigned R = MO.getReg();
for (unsigned i = 1, n = Phi->getNumOperands(); i < n; i += 2) {
       MachineInstr *DI = MRI->getVRegDef(PhiReg);
 
       if (DI->getDesc().isAdd()) {
         // If the register operand to the add/sub is the PHI we are looking
         // at, this meets the induction pattern.
         unsigned IndReg = DI->getOperand(1).getReg();
         MachineOperand &Opnd2 = DI->getOperand(2);
         int64_t V;
-        if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
+        if (MRI->getVRegDef(IndReg) == Phi &&
+            TII->getInstrOperandImmValue(*DI, Opnd2, V)) {
           unsigned UpdReg = DI->getOperand(0).getReg();
           IndRegs.insert(std::make_pair(UpdReg, std::make_pair(IndReg, V)));
         }
       }
     }  // for (i)
   }  // for (instr)
 
   if (IndRegs.empty())
bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
   for (unsigned i = 0, n = PredDef->getNumOperands(); i < n; ++i) {
     MachineOperand &MO = PredDef->getOperand(i);
     if (MO.isReg()) {
       // Skip all implicit references.  In one case there was:
       //   %vreg140<def> = FCMPUGT32_rr %vreg138, %vreg139, %USR<imp-use>
       if (MO.isImplicit())
         continue;
       if (MO.isUse()) {
-        if (!isImmediate(MO)) {
+        if (!isImmediate(TII, MO)) {
           CmpRegs.insert(MO.getReg());
           continue;
         }
         // Consider the register to be the "immediate" operand.
         if (CmpImmOp)
           return false;
         CmpImmOp = &MO;
       }
if (CmpRegs.count(RB.first)) {
       // because it may underflow.
       Comparison::Kind Cmp = getComparisonKind(PredDef->getOpcode(), 0, 0, 0);
       if (!Cmp || Comparison::isUnsigned(Cmp))
         return false;
 
       // If the register is being compared against an immediate, try changing
       // the compare instruction to use induction register and adjust the
       // immediate operand.
-      int64_t CmpImm = getImmediate(*CmpImmOp);
+      int64_t CmpImm = getImmediate(TII, *CmpImmOp);
       int64_t V = RB.second;
       // Handle Overflow (64-bit).
       if (((V > 0) && (CmpImm > INT64_MAX - V)) ||
           ((V < 0) && (CmpImm < INT64_MIN - V)))
         return false;
       CmpImm += V;
       // Most comparisons of register against an immediate value allow
       // the immediate to be constant-extended. There are some exceptions

lib/Target/Hexagon/HexagonInstrInfo.h

public:
   bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
                                 unsigned &OffsetPos) const override;
 
   /// If the instruction is an increment of a constant value, return the amount.
   bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
 
   bool isTailCall(const MachineInstr &MI) const override;
 
+  /// Check if the given operand has a compile-time known constant
+  /// value. Return true if yes, and false otherwise. When returning true, set
+  /// Val to the corresponding constant value.
+  bool getInstrOperandImmValue(const MachineInstr &MI, const MachineOperand &MO,
+                               int64_t &Val) const override;
+
   /// HexagonInstrInfo specifics.
   ///
 
   const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
 
   unsigned createVR(MachineFunction* MF, MVT VT) const;
 
   bool isAbsoluteSet(const MachineInstr &MI) const;

lib/Target/Hexagon/HexagonInstrInfo.cpp

bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
 
   for (auto &Op : MI.operands())
     if (Op.isGlobal() || Op.isSymbol())
       return true;
   return false;
 }
 
 
+bool
+HexagonInstrInfo::getInstrOperandImmValue(const MachineInstr &MI,
+                                          const MachineOperand &MO,
+                                          int64_t &Val) const {
+  const MachineFunction *MF = MI.getParent()->getParent();
+  const MachineRegisterInfo *MRI =  &MF->getRegInfo();
+
+  if (MO.isImm()) {
+    Val = MO.getImm();
+    return true;
+  }
+
+  if (!MO.isReg())
+    return false;
+
+  // MO is a register. Check whether it is defined as an immediate value,
+  // and if so, get the value of it in TV. That value will then need to be
+  // processed to handle potential subregisters in MO.
+  int64_t TV;
+
+  unsigned R = MO.getReg();
+  if (!TargetRegisterInfo::isVirtualRegister(R))
+    return false;
+
+  MachineInstr *DI = MRI->getVRegDef(R);
+  unsigned DOpc = DI->getOpcode();
+
+  switch (DOpc) {
+    case TargetOpcode::COPY:
+    case Hexagon::A2_tfrsi:
+    case Hexagon::A2_tfrpi:
+    case Hexagon::CONST32:
+    case Hexagon::CONST64: {
+      // Call recursively to avoid an extra check whether operand(1) is
+      // indeed an immediate (it could be a global address, for example),
+      // plus we can handle COPY at the same time.
+      if (!getInstrOperandImmValue(MI, DI->getOperand(1), TV))
+        return false;
+      break;
+    }
+    case Hexagon::A2_combineii:
+    case Hexagon::A4_combineir:
+    case Hexagon::A4_combineii:
+    case Hexagon::A4_combineri:
+    case Hexagon::A2_combinew: {
+      const MachineOperand &S1 = DI->getOperand(1);
+      const MachineOperand &S2 = DI->getOperand(2);
+      int64_t V1, V2;
+      if (!getInstrOperandImmValue(MI, S1, V1) || !getInstrOperandImmValue(MI, S2, V2))
+        return false;
+      TV = V2 | (V1 << 32);
+      break;
+    }
+    case TargetOpcode::REG_SEQUENCE: {
+      const MachineOperand &S1 = DI->getOperand(1);
+      const MachineOperand &S3 = DI->getOperand(3);
+      int64_t V1, V3;
+      if (!getInstrOperandImmValue(MI, S1, V1) || !getInstrOperandImmValue(MI, S3, V3))
+        return false;
+      int64_t Sub2 = DI->getOperand(2).getImm();
+      int64_t Sub4 = DI->getOperand(4).getImm();
+      if (Sub2 == Hexagon::subreg_loreg && Sub4 == Hexagon::subreg_hireg)
+        TV = V1 | (V3 << 32);
+      else if (Sub2 == Hexagon::subreg_hireg && Sub4 == Hexagon::subreg_loreg)
+        TV = V3 | (V1 << 32);
+      else
+        llvm_unreachable("Unexpected form of REG_SEQUENCE");
+      break;
+    }
+
+    default:
+      return false;
+  }
+
+  // By now, we should have successfuly obtained the immediate value defining
+  // the register referenced in MO. Handle a potential use of a subregister.
+  switch (MO.getSubReg()) {
+    case Hexagon::subreg_loreg:
+      Val = TV & 0xFFFFFFFFULL;
+      break;
+    case Hexagon::subreg_hireg:
+      Val = (TV >> 32) & 0xFFFFFFFFULL;
+      break;
+    default:
+      Val = TV;
+      break;
+  }
+
+  return true;
+}
+
+
 // Returns true when SU has a timing class TC1.
 bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
   unsigned SchedClass = MI.getDesc().getSchedClass();
   switch (SchedClass) {
   case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
   case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
   case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
   case Hexagon::Sched::ALU64_tc_1_SLOT23: