TII: add hook analyzeLoopTestBlock

[SjoerdMeijer]

Summary

TII: add hook analyzeLoopTestBlock. This is refactored from the Hexagon backend and is intended to be NFC. This is some more groundwork to recognise loop induction variables and trip counts for MachineLoops, and is related to D27191.

[SjoerdMeijer]

Abandoning as the approach is not generic enough, see https://reviews.llvm.org/D27193

include/llvm/Target/TargetInstrInfo.h

public:
   unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
                                      MachineBasicBlock *DestBB,
                                      const DebugLoc &DL,
                                      int *BytesAdded = nullptr) const {
     return insertBranch(MBB, DestBB, nullptr,
                         ArrayRef<MachineOperand>(), DL, BytesAdded);
   }
 
+  /// For a machine block that contains the loop thest, return the source
+  /// registers of the loop test in SrcReg and SrcReg2 if having two register
+  /// operands, and the value it compares against in CmpValue. Return true if
+  /// the comparison instruction can be analyzed.
+  virtual bool analyzeLoopTestBlock(MachineBasicBlock &MB, unsigned &CmpReg1,
+                                    unsigned &CmpReg2, int &CmpMask,
+                                    int &CmpImm) const {
+    return false;
+  }
+
   /// Analyze the loop code, return true if it cannot be understoo. Upon
   /// success, this function returns false and returns information about the
   /// induction variable and compare instruction used at the end.
   virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
                            MachineInstr *&CmpInst) const {
     return true;
   }
 

lib/Target/Hexagon/HexagonInstrInfo.h

unsigned getInlineAsmLength(const char *Str,
                               const MCAsmInfo &MAI) const override;
 
   /// Allocate and return a hazard recognizer to use for this target when
   /// scheduling the machine instructions after register allocation.
   ScheduleHazardRecognizer*
   CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
                                      const ScheduleDAG *DAG) const override;
 
+  /// Returns true when MB contains a compare with an immediate value
+  bool analyzeLoopTestBlock(MachineBasicBlock &MB, unsigned &CmpReg1,
+                            unsigned &CmpReg2, int &CmpMask,
+                            int &CmpImm) const override;
+
   /// For a comparison instruction, return the source registers
   /// in SrcReg and SrcReg2 if having two register operands, and the value it
   /// compares against in CmpValue. Return true if the comparison instruction
   /// can be analyzed.
   bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                       unsigned &SrcReg2, int &Mask, int &Value) const override;
 
   /// Compute the instruction latency of a given instruction.

lib/Target/Hexagon/HexagonInstrInfo.cpp

HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
       const InstrItineraryData *II, const ScheduleDAG *DAG) const {
   if (UseDFAHazardRec) {
     auto &HST = DAG->MF.getSubtarget<HexagonSubtarget>();
     return new HexagonHazardRecognizer(II, this, HST);
   }
   return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
 }
 
+///  return the source registers in
+/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
+/// compares against in CmpValue. Return true if the comparison instruction
+/// can be analyzed.
+bool HexagonInstrInfo::analyzeLoopTestBlock(MachineBasicBlock &MB,
+                                            unsigned &CmpReg1,
+                                            unsigned &CmpReg2,
+                                            int &CmpMask, int &CmpImm) const {
+  SmallVector<MachineOperand,2> Cond;
+  MachineBasicBlock *TB = nullptr, *FB = nullptr;
+  bool NotAnalyzed = analyzeBranch(MB, TB, FB, Cond, false);
+  if (NotAnalyzed)
+    return false;
+
+  unsigned PredR, PredPos, PredRegFlags;
+  if (!getPredReg(Cond, PredR, PredPos, PredRegFlags))
+    return false;
+
+  MachineRegisterInfo &MRI = MB.getParent()->getRegInfo();
+  MachineInstr *PredI = MRI.getVRegDef(PredR);
+  if (!PredI->isCompare())
+    return false;
+
+  // Fail if the compare was not analyzed, or it's not comparing a register
+  // with an immediate value.  Not checking the mask here, since we handle
+  // the individual compare opcodes (including A4_cmpb*) later on.
+  if (!analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm))
+    return false;
+
+  return true;
+}
 
 /// \brief For a comparison instruction, return the source registers in
 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
 /// compares against in CmpValue. Return true if the comparison instruction
 /// can be analyzed.
 bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                                       unsigned &SrcReg2, int &Mask,
                                       int &Value) const {