AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument

[jvesely]

Summary

wbinvl.* are vector instructions that do not use vector registers.

[• tstellarAMD]

LGTM.

[arsenm]

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

399–403

Could you invert this so it's an if (== -1) return -1

[jvesely]

cleanup

[arsenm]

LGTM

[jvesely]

v2: only checks for M?BUF instructions.

fixes regression in inserted-wait-states.mir

[arsenm]

LGTM

lib/Target/AMDGPU/GCNHazardRecognizer.cpp

if (!MI.mayStore())
     return -1;
 
   const SIInstrInfo *TII = ST.getInstrInfo();
   unsigned Opcode = MI.getOpcode();
   const MCInstrDesc &Desc = MI.getDesc();
 
   int VDataIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdata);
   int VDataRCID = -1;
   if (VDataIdx != -1)
     VDataRCID = Desc.OpInfo[VDataIdx].RegClass;
+  else
+    return -1;
 
   if (TII->isMUBUF(MI) || TII->isMTBUF(MI)) {
     // For MUBUF/MTBUF instructions this hazard only exists if the
     // instruction is not using a register in the soffset field.
     const MachineOperand *SOffset =
         TII->getNamedOperand(MI, AMDGPU::OpName::soffset);
     // If we have no soffset operand, then assume this field has been
     // hardcoded to zero.
     if (AMDGPU::getRegBitWidth(VDataRCID) > 64 &&

test/CodeGen/AMDGPU/llvm.amdgcn.buffer.wbinvl1.vol.ll

 ; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
 
 declare void @llvm.amdgcn.buffer.wbinvl1.vol() #0
 
 ; GCN-LABEL: {{^}}test_buffer_wbinvl1_vol:
 ; GCN-NEXT: ; BB#0:
 ; CI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
 ; VI-NEXT: buffer_wbinvl1_vol ; encoding: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
-; GCN-NEXT: s_endpgm
+; GCN: s_endpgm
 define void @test_buffer_wbinvl1_vol() #0 {
   call void @llvm.amdgcn.buffer.wbinvl1.vol()
+; This used to crash in hazard recognizer
+  store i8 0, i8 addrspace(1)* undef, align 1
   ret void
 }
 
 attributes #0 = { nounwind }