[InstCombine] don't widen most selects by hoisting an extend

[spatel]

Summary

This is related to the discussion in PR28160:
https://llvm.org/bugs/show_bug.cgi?id=28160

...but it's not the same example. It will help PR30773 more directly:
https://llvm.org/bugs/show_bug.cgi?id=30773

...because we handle selects with a constant operand on a different path than selects with two variables. Assuming this is the right thing to do, the next step will be to allow shrinking selects by sinking an extend after the select. That's easy because we already do that transform in InstCombiner::foldSelectExtConst(), but it's artificially limited to i1 types currently.

An example of the AVX2 codegen improvement from this patch using one of the vector regression tests:

Sext before:

define <4 x i64> @g1vec(<4 x i32> %a, <4 x i1> %cmp) {
  %ext = sext <4 x i32> %a to <4 x i64>
  %sel = select <4 x i1> %cmp, <4 x i64> %ext, <4 x i64> <i64 42, i64 42, i64 42, i64 42>
  ret <4 x i64> %ext
}

vpslld	$31, %xmm1, %xmm1
vpmovsxdq	%xmm1, %ymm1
vpmovsxdq	%xmm0, %ymm0
vbroadcastsd	LCPI1_0(%rip), %ymm2
vblendvpd	%ymm1, %ymm0, %ymm2, %ymm0
retq

Sext after:

define <4 x i64> @g1vec(<4 x i32> %a, <4 x i1> %cmp) {
  %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
  %ext = sext <4 x i32> %sel to <4 x i64>
  ret <4 x i64> %ext
}

vpslld	$31, %xmm1, %xmm1
vbroadcastss	LCPI1_0(%rip), %xmm2  <-- smaller load
vblendvps	%xmm1, %xmm0, %xmm2, %xmm0 <-- smaller select
vpmovsxdq	%xmm0, %ymm0
retq

The check for a leading trunc is to avoid regressing this test in test/Transforms/InstCombine/sext.ll:

define i32 @test8(i8 %a, i32 %f, i1 %p, i32* %z) {
; CHECK-LABEL: @test8(
; CHECK-NEXT:    [[D:%.*]] = lshr i32 %f, 24
; CHECK-NEXT:    [[N:%.*]] = select i1 %p, i32 [[D]], i32 0
; CHECK-NEXT:    ret i32 [[N]]
;
  %d = lshr i32 %f, 24
  %e = select i1 %p, i32 %d, i32 0
  %s = trunc i32 %e to i16
  %n = sext i16 %s to i32
  ret i32 %n
}

[filcab]

lib/Transforms/InstCombine/InstructionCombining.cpp

797

Do you want to match type sizes, though? Or at least make sure you're truncating more (or the same) as you're extending?
Like this:

[build-debug]% cat | ./bin/opt -O3 - -o - -S
define <4 x i64> @g3vec(<4 x i32> %_a, <4 x i1> %cmp) {
  %a = trunc <4 x i32> %_a to <4 x i24>
  %sel = select <4 x i1> %cmp, <4 x i24> %a, <4 x i24> <i24 42, i24 42, i24 42, i24 42>
  %ext = zext <4 x i24> %sel to <4 x i64>
  ret <4 x i64> %ext
}


; ModuleID = '<stdin>'
source_filename = "<stdin>"

; Function Attrs: norecurse nounwind readnone
define <4 x i64> @g3vec(<4 x i32> %_a, <4 x i1> %cmp) local_unnamed_addr #0 {
  %1 = and <4 x i32> %_a, <i32 16777215, i32 16777215, i32 16777215, i32 16777215>
  %2 = zext <4 x i32> %1 to <4 x i64>
  %ext = select <4 x i1> %cmp, <4 x i64> %2, <4 x i64> <i64 42, i64 42, i64 42, i64 42>
  ret <4 x i64> %ext
}

attributes #0 = { norecurse nounwind readnone }

vs just select + zext (using sext will make it even worse :-)

[spatel]

lib/Transforms/InstCombine/InstructionCombining.cpp

797

This case would be another improvement over the current behavior, right? Ok if I add a 'TODO' comment in this patch and follow up with another test case plus that refinement?

[spatel]

Patch updated:
0. Preliminary: added a pile of tests for permutations of trunc/sel/ext with rL287400 .

1. Added a function specifically to handle widening of select, so (in theory) we have this transform in one place and can do it in a principled way.
2. But some of the tests still show the (unwanted?) changes noted in Filipe's example.
3. Added TODO comments where those happen (we treat vectors differently than scalars).
4. Added a FIXME because we're dropping profile metadata for all of these select transforms.

[spatel]

Ping.

Patch updated:

1. Rebase after rL287980 (no need to add FIXME comment now).
2. Propagate metadata with SelectInst::Create() ( rL287976 ).
3. Update trunc_sel_equal_zext / trunc_sel_equal_zext_vec tests to show that metadata is not dropped.

[spatel]

Ping * 2.

[spatel]

Ping * 3.

[efriedma]

I'm not sure this approach is really right... narrower isn't always better. You're just getting lucky with your AVX2 example: <4 x i1> as an argument happens to get passed as a 128-bit vector. If the compare operand were a 64-bit comparison, you'd be making the code worse; consider:

define <4 x i64> @f(<4 x i32> %a, <4 x i64> %b, <4 x i64> %c) {
  %cmp = icmp sgt <4 x i64> %b, %c
  %ext = sext <4 x i32> %a to <4 x i64>
  %sel = select <4 x i1> %cmp, <4 x i64> %ext, <4 x i64> <i64 42, i64 42, i64 42, i64 42>
  ret <4 x i64> %sel
}

This is perfectly straightforward code of the sort you could write using intrinsics in C. Move the sext, and the generated code becomes worse.

[spatel]

In D26556#620167, @efriedma wrote:

I'm not sure this approach is really right... narrower isn't always better. You're just getting lucky with your AVX2 example: <4 x i1> as an argument happens to get passed as a 128-bit vector. If the compare operand were a 64-bit comparison, you'd be making the code worse; consider:

define <4 x i64> @f(<4 x i32> %a, <4 x i64> %b, <4 x i64> %c) {
  %cmp = icmp sgt <4 x i64> %b, %c
  %ext = sext <4 x i32> %a to <4 x i64>
  %sel = select <4 x i1> %cmp, <4 x i64> %ext, <4 x i64> <i64 42, i64 42, i64 42, i64 42>
  ret <4 x i64> %sel
}

This is perfectly straightforward code of the sort you could write using intrinsics in C. Move the sext, and the generated code becomes worse.

Would you say this is a backend pattern-matching hole, or do you object to the IR transform itself? Ie, if we can fix the backend, would this be a valid patch? My view is that a narrower op in IR is better in terms of value tracking and could be thought of as a strength reduction optimization, so this is the theoretically correct approach to the IR...but as always, let me know if I'm off in the weeds. :)

For reference, if we're looking at AVX2 codegen, we have this:

define <4 x i64> @f(<4 x i32> %a, <4 x i64> %b, <4 x i64> %c) {
  %cmp = icmp sgt <4 x i64> %b, %c
  %ext = sext <4 x i32> %a to <4 x i64>
  %sel = select <4 x i1> %cmp, <4 x i64> %ext, <4 x i64> <i64 42, i64 42, i64 42, i64 42>
  ret <4 x i64> %sel
}

define <4 x i64> @g(<4 x i32> %a, <4 x i64> %b, <4 x i64> %c) {
  %cmp = icmp sgt <4 x i64> %b, %c
  %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
  %ext = sext <4 x i32> %sel to <4 x i64>
  ret <4 x i64> %ext
}

Which becomes:

_f:                                     ## @f
vpcmpgtq	%ymm2, %ymm1, %ymm1
vpmovsxdq	%xmm0, %ymm0
vbroadcastsd	LCPI0_0(%rip), %ymm2
vblendvpd	%ymm1, %ymm0, %ymm2, %ymm0
retq
_g:                                     ## @g
vpcmpgtq	%ymm2, %ymm1, %ymm1
vextracti128	$1, %ymm1, %xmm2
vpacksswb	%xmm2, %xmm1, %xmm1
vbroadcastss	LCPI1_0(%rip), %xmm2
vblendvps	%xmm1, %xmm0, %xmm2, %xmm0
vpmovsxdq	%xmm0, %ymm0
retq

[efriedma]

If we could pattern-match our way out, it might be okay... but I don't think that's realistic in more complicated cases. The sign-extend could be pushed forward through another operation or land in a different basic block. I think it makes more sense to just try to make selects use the "right" width for the target (the width of the compare operands for most targets).

[spatel]

In D26556#620417, @efriedma wrote:

If we could pattern-match our way out, it might be okay... but I don't think that's realistic in more complicated cases. The sign-extend could be pushed forward through another operation or land in a different basic block. I think it makes more sense to just try to make selects use the "right" width for the target (the width of the compare operands for most targets).

Sorry for the 18 month delay. Let's do that. :)
D47163

Abandoning.

lib/Transforms/InstCombine/InstCombineCasts.cpp

Instruction::CastOps InstCombiner::isEliminableCastPair(const CastInst *CI1,
   // type that differs from the pointer size.
   if ((Res == Instruction::IntToPtr && SrcTy != DstIntPtrTy) ||
       (Res == Instruction::PtrToInt && DstTy != SrcIntPtrTy))
     Res = 0;
 
   return Instruction::CastOps(Res);
 }
 
+/// If a cast widens the result, only widen the select when we are sure that it
+/// will remove a preceding truncate or remove the widening cast.
+static Instruction *
+foldWideningCastIntoSelect(CastInst &Cast, SelectInst &Sel,
+                           InstCombiner::BuilderTy &Builder) {
+  Type *SrcTy = Sel.getType();
+  Type *DstTy = Cast.getType();
+  unsigned SrcWidth = SrcTy->getScalarSizeInBits();
+  unsigned DstWidth = DstTy->getScalarSizeInBits();
+  if (SrcWidth >= DstWidth)
+    return nullptr;
+
+  Value *Cond = Sel.getCondition();
+  Value *TVal = Sel.getTrueValue();
+  Value *FVal = Sel.getFalseValue();
+  Instruction::CastOps CastOpc = Cast.getOpcode();
+
+  // If both arms of the select are constants, widen the select and eliminate
+  // the cast.
+  Constant *TC, *FC;
+  if (match(TVal, m_Constant(TC)) && match(FVal, m_Constant(FC))) {
+    Constant *WideTC = ConstantExpr::getCast(CastOpc, TC, DstTy);
+    Constant *WideFC = ConstantExpr::getCast(CastOpc, FC, DstTy);
+    return SelectInst::Create(Cond, WideTC, WideFC, "", nullptr, &Sel);
+  }
+
+  if (!Sel.hasOneUse() || CastOpc != Instruction::ZExt)
+    return nullptr;
+
+  // Look through the select to find a truncate. The trunc+zext is replaced by
+  // an 'and', and the select is widened.
+  Constant *C;
+  Value *X;
+  if (((match(TVal, m_Constant(C)) &&
+        match(FVal, m_OneUse(m_Trunc(m_Value(X))))) ||
+       (match(FVal, m_Constant(C)) &&
+        match(TVal, m_OneUse(m_Trunc(m_Value(X)))))) &&
+      X->getType() == DstTy) {
+    // zext (select Cond, C, (trunc X)) --> select Cond, C', (and X, Mask)
+    // zext (select Cond, (trunc X), C) --> select Cond, (and X, Mask), C'
+    Constant *Mask =
+        ConstantInt::get(DstTy, APInt::getLowBitsSet(DstWidth, SrcWidth));
+    Value *And = Builder.CreateAnd(X, Mask);
+    Constant *ExtC = ConstantExpr::getCast(CastOpc, C, DstTy);
+    return TVal == C ? SelectInst::Create(Cond, ExtC, And, "", nullptr, &Sel) :
+                       SelectInst::Create(Cond, And, ExtC, "", nullptr, &Sel);
+  }
+
+  return nullptr;
+}
+
 /// @brief Implement the transforms common to all CastInst visitors.
 Instruction *InstCombiner::commonCastTransforms(CastInst &CI) {
   Value *Src = CI.getOperand(0);
 
   // Try to eliminate a cast of a cast.
   if (auto *CSrc = dyn_cast<CastInst>(Src)) {   // A->B->C cast
     if (Instruction::CastOps NewOpc = isEliminableCastPair(CSrc, &CI)) {
       // The first cast (CSrc) is eliminable so we need to fix up or replace
       // the second cast (CI). CSrc will then have a good chance of being dead.
       return CastInst::Create(NewOpc, CSrc->getOperand(0), CI.getType());
     }
   }
 
   // If we are casting a select, then fold the cast into the select.
-  if (auto *SI = dyn_cast<SelectInst>(Src))
+  if (auto *SI = dyn_cast<SelectInst>(Src)) {
     if (Instruction *NV = FoldOpIntoSelect(CI, SI))
       return NV;
 
+    if (Instruction *NV = foldWideningCastIntoSelect(CI, *SI, *Builder))
+      return NV;
+  }
+
   // If we are casting a PHI, then fold the cast into the PHI.
   if (isa<PHINode>(Src)) {
     // Don't do this if it would create a PHI node with an illegal type from a
     // legal type.
     if (!Src->getType()->isIntegerTy() || !CI.getType()->isIntegerTy() ||
         ShouldChangeType(CI.getType(), Src->getType()))
       if (Instruction *NV = FoldOpIntoPhi(CI))
         return NV;
Instruction *InstCombiner::visitZExt(ZExtInst &CI) {
 
   Value *Src = CI.getOperand(0);
   Type *SrcTy = Src->getType(), *DestTy = CI.getType();
 
   // Attempt to extend the entire input expression tree to the destination
   // type.   Only do this if the dest type is a simple type, don't convert the
   // expression tree to something weird like i93 unless the source is also
   // strange.
+  // TODO: Should all vectors be transformed?
   unsigned BitsToClear;
   if ((DestTy->isVectorTy() || ShouldChangeType(SrcTy, DestTy)) &&
       canEvaluateZExtd(Src, DestTy, BitsToClear, *this, &CI)) {
     assert(BitsToClear < SrcTy->getScalarSizeInBits() &&
            "Unreasonable BitsToClear");
 
     // Okay, we can transform this!  Insert the new expression now.
     DEBUG(dbgs() << "ICE: EvaluateInDifferentType converting expression type"
if (KnownZero) {
     Value *ZExt = Builder->CreateZExt(Src, DestTy);
     return replaceInstUsesWith(CI, ZExt);
   }
 
   // Attempt to extend the entire input expression tree to the destination
   // type.   Only do this if the dest type is a simple type, don't convert the
   // expression tree to something weird like i93 unless the source is also
   // strange.
+  // TODO: Should all vectors be transformed?
   if ((DestTy->isVectorTy() || ShouldChangeType(SrcTy, DestTy)) &&
       canEvaluateSExtd(Src, DestTy)) {
     // Okay, we can transform this!  Insert the new expression now.
     DEBUG(dbgs() << "ICE: EvaluateInDifferentType converting expression type"
           " to avoid sign extend: " << CI << '\n');
     Value *Res = EvaluateInDifferentType(Src, DestTy, true);
     assert(Res->getType() == DestTy);
 

lib/Transforms/InstCombine/InstructionCombining.cpp

static Value *foldOperationIntoSelectOperand(Instruction &I, Value *SO,
   auto *FPInst = dyn_cast<Instruction>(RI);
   if (FPInst && isa<FPMathOperator>(FPInst))
     FPInst->copyFastMathFlags(BO);
   return RI;
 }
 
 /// Given an instruction with a select as one operand and a constant as the
 /// other operand, try to fold the binary operator into the select arguments.
-/// This also works for Cast instructions, which obviously do not have a second
-/// operand.
+/// This also works for some Cast instructions, which obviously do not have a
+/// second operand.
 Instruction *InstCombiner::FoldOpIntoSelect(Instruction &Op, SelectInst *SI) {
   // Don't modify shared select instructions.
   if (!SI->hasOneUse())
     return nullptr;
 
   Value *TV = SI->getTrueValue();
   Value *FV = SI->getFalseValue();
   if (!(isa<Constant>(TV) || isa<Constant>(FV)))
     return nullptr;
 
   // Bool selects with constant operands can be folded to logical ops.
   if (SI->getType()->getScalarType()->isIntegerTy(1))
     return nullptr;
 
+  // If Op is an extend, do not grow the select operand sizes by pulling the
+  // extend into or ahead of the select. This is particularly important for
+  // vectors because we want to use the narrowest operations possible for a
+  // given number of vector lanes.
+  unsigned SrcWidth = SI->getType()->getScalarSizeInBits();
+  unsigned DstWidth = Op.getType()->getScalarSizeInBits();
+  if (SrcWidth < DstWidth)
+    return nullptr;
+
   // If it's a bitcast involving vectors, make sure it has the same number of
   // elements on both sides.
   if (auto *BC = dyn_cast<BitCastInst>(&Op)) {
     VectorType *DestTy = dyn_cast<VectorType>(BC->getDestTy());
     VectorType *SrcTy = dyn_cast<VectorType>(BC->getSrcTy());
 
     // Verify that either both or neither are vectors.
     if ((SrcTy == nullptr) != (DestTy == nullptr))

test/Transforms/InstCombine/select-bitext.ll

 ; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, double -2.550000e+02, double 4.200000e+01
 ; CHECK-NEXT:    ret double [[EXT]]
 ;
   %sel = select i1 %cmp, float -255.0, float 42.0
   %ext = fpext float %sel to double
   ret double %ext
 }
 
-; FIXME: We should not grow the size of the select in the next 4 cases.
-
 define i64 @sel_sext(i32 %a, i1 %cmp) {
 ; CHECK-LABEL: @sel_sext(
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i32 %a to i64
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i32 %a, i32 42
+; CHECK-NEXT:    [[EXT:%.*]] = sext i32 [[SEL]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   %sel = select i1 %cmp, i32 %a, i32 42
   %ext = sext i32 %sel to i64
   ret i64 %ext
 }
 
 define <4 x i64> @sel_sext_vec(<4 x i32> %a, <4 x i1> %cmp) {
 ; CHECK-LABEL: @sel_sext_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = sext <4 x i32> %a to <4 x i64>
-; CHECK-NEXT:    [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
+; CHECK-NEXT:    [[EXT:%.*]] = sext <4 x i32> [[SEL]] to <4 x i64>
 ; CHECK-NEXT:    ret <4 x i64> [[EXT]]
 ;
   %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
   %ext = sext <4 x i32> %sel to <4 x i64>
   ret <4 x i64> %ext
 }
 
 define i64 @sel_zext(i32 %a, i1 %cmp) {
 ; CHECK-LABEL: @sel_zext(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 %a to i64
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i32 %a, i32 42
+; CHECK-NEXT:    [[EXT:%.*]] = zext i32 [[SEL]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   %sel = select i1 %cmp, i32 %a, i32 42
   %ext = zext i32 %sel to i64
   ret i64 %ext
 }
 
 define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {
 ; CHECK-LABEL: @sel_zext_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext <4 x i32> %a to <4 x i64>
-; CHECK-NEXT:    [[EXT:%.*]] = select <4 x i1> %cmp, <4 x i64> [[TMP1]], <4 x i64> <i64 42, i64 42, i64 42, i64 42>
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
+; CHECK-NEXT:    [[EXT:%.*]] = zext <4 x i32> [[SEL]] to <4 x i64>
 ; CHECK-NEXT:    ret <4 x i64> [[EXT]]
 ;
   %sel = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> <i32 42, i32 42, i32 42, i32 42>
   %ext = zext <4 x i32> %sel to <4 x i64>
   ret <4 x i64> %ext
 }
 
-; FIXME: The next 18 tests cycle through trunc+select and {larger,smaller,equal} {sext,zext,fpext} {scalar,vector}.
-; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only
-; way to justify widening the select.
+; The next 18 tests cycle through trunc+select and {larger,smaller,equal} {sext,zext,fpext} {scalar,vector}.
+; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's the only
+; way to justify widening the select? Except all sext/zext with vectors are transformed to use a wider select
+; even if it means adding IR instructions?
 
 define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_larger_sext(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 %a to i16
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i16 [[TRUNC]], i16 42
+; CHECK-NEXT:    [[EXT:%.*]] = sext i16 [[SEL]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   %trunc = trunc i32 %a to i16
   %sel = select i1 %cmp, i16 %trunc, i16 42
   %ext = sext i16 %sel to i64
   ret i64 %ext
 }
 
 define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_larger_sext_vec(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48>
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[SEXT]], <i64 48, i64 48>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
+; CHECK-NEXT:    [[TRUNC_OP:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48>
+; CHECK-NEXT:    [[TRUNC_OP_OP:%.*]] = ashr <2 x i64> [[TRUNC_OP]], <i64 48, i64 48>
+; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TRUNC_OP_OP]], <2 x i64> <i64 42, i64 43>
 ; CHECK-NEXT:    ret <2 x i64> [[EXT]]
 ;
   %trunc = trunc <2 x i32> %a to <2 x i16>
   %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
   %ext = sext <2 x i16> %sel to <2 x i64>
   ret <2 x i64> %ext
 }
 
 define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_smaller_sext(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i64 %a to i16
-; CHECK-NEXT:    [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i16 [[TRUNC]], i16 42
+; CHECK-NEXT:    [[EXT:%.*]] = sext i16 [[SEL]] to i32
 ; CHECK-NEXT:    ret i32 [[EXT]]
 ;
   %trunc = trunc i64 %a to i16
   %sel = select i1 %cmp, i16 %trunc, i16 42
   %ext = sext i16 %sel to i32
   ret i32 %ext
 }
 
 define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_smaller_sext_vec(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
-; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16>
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], <i32 16, i32 16>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT:    [[TRUNC_OP:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16>
+; CHECK-NEXT:    [[TRUNC_OP_OP:%.*]] = ashr <2 x i32> [[TRUNC_OP]], <i32 16, i32 16>
+; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TRUNC_OP_OP]], <2 x i32> <i32 42, i32 43>
 ; CHECK-NEXT:    ret <2 x i32> [[EXT]]
 ;
   %trunc = trunc <2 x i64> %a to <2 x i16>
   %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
   %ext = sext <2 x i16> %sel to <2 x i32>
   ret <2 x i32> %ext
 }
 
 define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_equal_sext(
-; CHECK-NEXT:    [[SEXT:%.*]] = shl i32 %a, 16
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr exact i32 [[SEXT]], 16
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 %a to i16
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i16 [[TRUNC]], i16 42
+; CHECK-NEXT:    [[EXT:%.*]] = sext i16 [[SEL]] to i32
 ; CHECK-NEXT:    ret i32 [[EXT]]
 ;
   %trunc = trunc i32 %a to i16
   %sel = select i1 %cmp, i16 %trunc, i16 42
   %ext = sext i16 %sel to i32
   ret i32 %ext
 }
 
 define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_equal_sext_vec(
-; CHECK-NEXT:    [[SEXT:%.*]] = shl <2 x i32> %a, <i32 16, i32 16>
-; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], <i32 16, i32 16>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT:    [[A_OP:%.*]] = shl <2 x i32> %a, <i32 16, i32 16>
+; CHECK-NEXT:    [[A_OP_OP:%.*]] = ashr <2 x i32> [[A_OP]], <i32 16, i32 16>
+; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[A_OP_OP]], <2 x i32> <i32 42, i32 43>
 ; CHECK-NEXT:    ret <2 x i32> [[EXT]]
 ;
   %trunc = trunc <2 x i32> %a to <2 x i16>
   %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
   %ext = sext <2 x i16> %sel to <2 x i32>
   ret <2 x i32> %ext
 }
 
 define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_larger_zext(
-; CHECK-NEXT:    [[TRUNC_MASK:%.*]] = and i32 %a, 65535
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i32 %a to i16
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i16 [[TRUNC]], i16 42
+; CHECK-NEXT:    [[EXT:%.*]] = zext i16 [[SEL]] to i64
 ; CHECK-NEXT:    ret i64 [[EXT]]
 ;
   %trunc = trunc i32 %a to i16
   %sel = select i1 %cmp, i16 %trunc, i16 42
   %ext = zext i16 %sel to i64
   ret i64 %ext
 }
 
 define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_larger_zext_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535>
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP2]], <2 x i64> <i64 42, i64 43>
+; CHECK-NEXT:    [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64>
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TRUNC]], <2 x i64> <i64 42, i64 43>
+; CHECK-NEXT:    [[EXT:%.*]] = and <2 x i64> [[SEL]], <i64 65535, i64 65535>
 ; CHECK-NEXT:    ret <2 x i64> [[EXT]]
 ;
   %trunc = trunc <2 x i32> %a to <2 x i16>
   %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
   %ext = zext <2 x i16> %sel to <2 x i64>
   ret <2 x i64> %ext
 }
 
 define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_smaller_zext(
-; CHECK-NEXT:    [[TMP1:%.*]] = trunc i64 %a to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], 65535
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i32 [[TMP2]], i32 42
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc i64 %a to i16
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, i16 [[TRUNC]], i16 42
+; CHECK-NEXT:    [[EXT:%.*]] = zext i16 [[SEL]] to i32
 ; CHECK-NEXT:    ret i32 [[EXT]]
 ;
   %trunc = trunc i64 %a to i16
   %sel = select i1 %cmp, i16 %trunc, i16 42
   %ext = zext i16 %sel to i32
   ret i32 %ext
 }
 
 define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_smaller_zext_vec(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[TRUNC]], <i32 65535, i32 65535>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TRUNC]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT:    [[EXT:%.*]] = and <2 x i32> [[SEL]], <i32 65535, i32 65535>
 ; CHECK-NEXT:    ret <2 x i32> [[EXT]]
 ;
   %trunc = trunc <2 x i64> %a to <2 x i16>
   %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
   %ext = zext <2 x i16> %sel to <2 x i32>
   ret <2 x i32> %ext
 }
 
 define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_equal_zext(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 %a, 65535
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
+; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42, !prof !0
 ; CHECK-NEXT:    ret i32 [[EXT]]
 ;
   %trunc = trunc i32 %a to i16
-  %sel = select i1 %cmp, i16 %trunc, i16 42
+  %sel = select i1 %cmp, i16 %trunc, i16 42, !prof !0
   %ext = zext i16 %sel to i32
   ret i32 %ext
 }
 
 define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_equal_zext_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
+; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>, !prof !0
 ; CHECK-NEXT:    ret <2 x i32> [[EXT]]
 ;
   %trunc = trunc <2 x i32> %a to <2 x i16>
-  %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
+  %sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>, !prof !0
   %ext = zext <2 x i16> %sel to <2 x i32>
   ret <2 x i32> %ext
 }
 
 define double @trunc_sel_larger_fpext(float %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_larger_fpext(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc float %a to half
-; CHECK-NEXT:    [[TMP1:%.*]] = fpext half [[TRUNC]] to double
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, double [[TMP1]], double 4.200000e+01
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, half [[TRUNC]], half 0xH5140
+; CHECK-NEXT:    [[EXT:%.*]] = fpext half [[SEL]] to double
 ; CHECK-NEXT:    ret double [[EXT]]
 ;
   %trunc = fptrunc float %a to half
   %sel = select i1 %cmp, half %trunc, half 42.0
   %ext = fpext half %sel to double
   ret double %ext
 }
 
 define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_larger_fpext_vec(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half>
-; CHECK-NEXT:    [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01>
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> %cmp, <2 x half> [[TRUNC]], <2 x half> <half 0xH5140, half 0xH5160>
+; CHECK-NEXT:    [[EXT:%.*]] = fpext <2 x half> [[SEL]] to <2 x double>
 ; CHECK-NEXT:    ret <2 x double> [[EXT]]
 ;
   %trunc = fptrunc <2 x float> %a to <2 x half>
   %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
   %ext = fpext <2 x half> %sel to <2 x double>
   ret <2 x double> %ext
 }
 
 define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_smaller_fpext(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc double %a to half
-; CHECK-NEXT:    [[TMP1:%.*]] = fpext half [[TRUNC]] to float
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, half [[TRUNC]], half 0xH5140
+; CHECK-NEXT:    [[EXT:%.*]] = fpext half [[SEL]] to float
 ; CHECK-NEXT:    ret float [[EXT]]
 ;
   %trunc = fptrunc double %a to half
   %sel = select i1 %cmp, half %trunc, half 42.0
   %ext = fpext half %sel to float
   ret float %ext
 }
 
 define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_smaller_fpext_vec(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc <2 x double> %a to <2 x half>
-; CHECK-NEXT:    [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> %cmp, <2 x half> [[TRUNC]], <2 x half> <half 0xH5140, half 0xH5160>
+; CHECK-NEXT:    [[EXT:%.*]] = fpext <2 x half> [[SEL]] to <2 x float>
 ; CHECK-NEXT:    ret <2 x float> [[EXT]]
 ;
   %trunc = fptrunc <2 x double> %a to <2 x half>
   %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
   %ext = fpext <2 x half> %sel to <2 x float>
   ret <2 x float> %ext
 }
 
 define float @trunc_sel_equal_fpext(float %a, i1 %cmp) {
 ; CHECK-LABEL: @trunc_sel_equal_fpext(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc float %a to half
-; CHECK-NEXT:    [[TMP1:%.*]] = fpext half [[TRUNC]] to float
-; CHECK-NEXT:    [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 %cmp, half [[TRUNC]], half 0xH5140
+; CHECK-NEXT:    [[EXT:%.*]] = fpext half [[SEL]] to float
 ; CHECK-NEXT:    ret float [[EXT]]
 ;
   %trunc = fptrunc float %a to half
   %sel = select i1 %cmp, half %trunc, half 42.0
   %ext = fpext half %sel to float
   ret float %ext
 }
 
 define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
 ; CHECK-LABEL: @trunc_sel_equal_fpext_vec(
 ; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half>
-; CHECK-NEXT:    [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
-; CHECK-NEXT:    [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
+; CHECK-NEXT:    [[SEL:%.*]] = select <2 x i1> %cmp, <2 x half> [[TRUNC]], <2 x half> <half 0xH5140, half 0xH5160>
+; CHECK-NEXT:    [[EXT:%.*]] = fpext <2 x half> [[SEL]] to <2 x float>
 ; CHECK-NEXT:    ret <2 x float> [[EXT]]
 ;
   %trunc = fptrunc <2 x float> %a to <2 x half>
   %sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
   %ext = fpext <2 x half> %sel to <2 x float>
   ret <2 x float> %ext
 }