Skip to content

Commit 47e577e

Browse files
rotaterightrotateright
committedNov 18, 2016
[InstCombine] add tests to show likely unwanted select widening; NFC
This is a prerequisite patch for D26556: https://reviews.llvm.org/D26556 ...because there was no direct coverage for these folds (which in some cases are adding instructions). llvm-svn: 287400
1 parent 93fa186 commit 47e577e

File tree

1 file changed

+270
-0
lines changed

1 file changed

+270
-0
lines changed
 

‎llvm/test/Transforms/InstCombine/select-bitext.ll

+270
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,38 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
22
; RUN: opt < %s -instcombine -S | FileCheck %s
33

4+
; Widen a select of constants to eliminate an extend.
5+
6+
define i16 @sel_sext_constants(i1 %cmp) {
7+
; CHECK-LABEL: @sel_sext_constants(
8+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i16 -1, i16 42
9+
; CHECK-NEXT: ret i16 [[EXT]]
10+
;
11+
%sel = select i1 %cmp, i8 255, i8 42
12+
%ext = sext i8 %sel to i16
13+
ret i16 %ext
14+
}
15+
16+
define i16 @sel_zext_constants(i1 %cmp) {
17+
; CHECK-LABEL: @sel_zext_constants(
18+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i16 255, i16 42
19+
; CHECK-NEXT: ret i16 [[EXT]]
20+
;
21+
%sel = select i1 %cmp, i8 255, i8 42
22+
%ext = zext i8 %sel to i16
23+
ret i16 %ext
24+
}
25+
26+
define double @sel_fpext_constants(i1 %cmp) {
27+
; CHECK-LABEL: @sel_fpext_constants(
28+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, double -2.550000e+02, double 4.200000e+01
29+
; CHECK-NEXT: ret double [[EXT]]
30+
;
31+
%sel = select i1 %cmp, float -255.0, float 42.0
32+
%ext = fpext float %sel to double
33+
ret double %ext
34+
}
35+
436
; FIXME: We should not grow the size of the select in the next 4 cases.
537

638
define i64 @sel_sext(i32 %a, i1 %cmp) {
@@ -47,6 +79,244 @@ define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {
4779
ret <4 x i64> %ext
4880
}
4981

82+
; FIXME: The next 18 tests cycle through trunc+select and {larger,smaller,equal} {sext,zext,fpext} {scalar,vector}.
83+
; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only
84+
; way to justify widening the select.
85+
86+
define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) {
87+
; CHECK-LABEL: @trunc_sel_larger_sext(
88+
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 %a to i16
89+
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64
90+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
91+
; CHECK-NEXT: ret i64 [[EXT]]
92+
;
93+
%trunc = trunc i32 %a to i16
94+
%sel = select i1 %cmp, i16 %trunc, i16 42
95+
%ext = sext i16 %sel to i64
96+
ret i64 %ext
97+
}
98+
99+
define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
100+
; CHECK-LABEL: @trunc_sel_larger_sext_vec(
101+
; CHECK-NEXT: [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64>
102+
; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48>
103+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[SEXT]], <i64 48, i64 48>
104+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
105+
; CHECK-NEXT: ret <2 x i64> [[EXT]]
106+
;
107+
%trunc = trunc <2 x i32> %a to <2 x i16>
108+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
109+
%ext = sext <2 x i16> %sel to <2 x i64>
110+
ret <2 x i64> %ext
111+
}
112+
113+
define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) {
114+
; CHECK-LABEL: @trunc_sel_smaller_sext(
115+
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 %a to i16
116+
; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32
117+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
118+
; CHECK-NEXT: ret i32 [[EXT]]
119+
;
120+
%trunc = trunc i64 %a to i16
121+
%sel = select i1 %cmp, i16 %trunc, i16 42
122+
%ext = sext i16 %sel to i32
123+
ret i32 %ext
124+
}
125+
126+
define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) {
127+
; CHECK-LABEL: @trunc_sel_smaller_sext_vec(
128+
; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
129+
; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16>
130+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], <i32 16, i32 16>
131+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
132+
; CHECK-NEXT: ret <2 x i32> [[EXT]]
133+
;
134+
%trunc = trunc <2 x i64> %a to <2 x i16>
135+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
136+
%ext = sext <2 x i16> %sel to <2 x i32>
137+
ret <2 x i32> %ext
138+
}
139+
140+
define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) {
141+
; CHECK-LABEL: @trunc_sel_equal_sext(
142+
; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %a, 16
143+
; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i32 [[SEXT]], 16
144+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
145+
; CHECK-NEXT: ret i32 [[EXT]]
146+
;
147+
%trunc = trunc i32 %a to i16
148+
%sel = select i1 %cmp, i16 %trunc, i16 42
149+
%ext = sext i16 %sel to i32
150+
ret i32 %ext
151+
}
152+
153+
define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
154+
; CHECK-LABEL: @trunc_sel_equal_sext_vec(
155+
; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> %a, <i32 16, i32 16>
156+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], <i32 16, i32 16>
157+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
158+
; CHECK-NEXT: ret <2 x i32> [[EXT]]
159+
;
160+
%trunc = trunc <2 x i32> %a to <2 x i16>
161+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
162+
%ext = sext <2 x i16> %sel to <2 x i32>
163+
ret <2 x i32> %ext
164+
}
165+
166+
define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) {
167+
; CHECK-LABEL: @trunc_sel_larger_zext(
168+
; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 %a, 65535
169+
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64
170+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
171+
; CHECK-NEXT: ret i64 [[EXT]]
172+
;
173+
%trunc = trunc i32 %a to i16
174+
%sel = select i1 %cmp, i16 %trunc, i16 42
175+
%ext = zext i16 %sel to i64
176+
ret i64 %ext
177+
}
178+
179+
define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
180+
; CHECK-LABEL: @trunc_sel_larger_zext_vec(
181+
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535>
182+
; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
183+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP2]], <2 x i64> <i64 42, i64 43>
184+
; CHECK-NEXT: ret <2 x i64> [[EXT]]
185+
;
186+
%trunc = trunc <2 x i32> %a to <2 x i16>
187+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
188+
%ext = zext <2 x i16> %sel to <2 x i64>
189+
ret <2 x i64> %ext
190+
}
191+
192+
define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) {
193+
; CHECK-LABEL: @trunc_sel_smaller_zext(
194+
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 %a to i32
195+
; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65535
196+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP2]], i32 42
197+
; CHECK-NEXT: ret i32 [[EXT]]
198+
;
199+
%trunc = trunc i64 %a to i16
200+
%sel = select i1 %cmp, i16 %trunc, i16 42
201+
%ext = zext i16 %sel to i32
202+
ret i32 %ext
203+
}
204+
205+
define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) {
206+
; CHECK-LABEL: @trunc_sel_smaller_zext_vec(
207+
; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
208+
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TRUNC]], <i32 65535, i32 65535>
209+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
210+
; CHECK-NEXT: ret <2 x i32> [[EXT]]
211+
;
212+
%trunc = trunc <2 x i64> %a to <2 x i16>
213+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
214+
%ext = zext <2 x i16> %sel to <2 x i32>
215+
ret <2 x i32> %ext
216+
}
217+
218+
define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) {
219+
; CHECK-LABEL: @trunc_sel_equal_zext(
220+
; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, 65535
221+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
222+
; CHECK-NEXT: ret i32 [[EXT]]
223+
;
224+
%trunc = trunc i32 %a to i16
225+
%sel = select i1 %cmp, i16 %trunc, i16 42
226+
%ext = zext i16 %sel to i32
227+
ret i32 %ext
228+
}
229+
230+
define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
231+
; CHECK-LABEL: @trunc_sel_equal_zext_vec(
232+
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535>
233+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
234+
; CHECK-NEXT: ret <2 x i32> [[EXT]]
235+
;
236+
%trunc = trunc <2 x i32> %a to <2 x i16>
237+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
238+
%ext = zext <2 x i16> %sel to <2 x i32>
239+
ret <2 x i32> %ext
240+
}
241+
242+
define double @trunc_sel_larger_fpext(float %a, i1 %cmp) {
243+
; CHECK-LABEL: @trunc_sel_larger_fpext(
244+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float %a to half
245+
; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to double
246+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, double [[TMP1]], double 4.200000e+01
247+
; CHECK-NEXT: ret double [[EXT]]
248+
;
249+
%trunc = fptrunc float %a to half
250+
%sel = select i1 %cmp, half %trunc, half 42.0
251+
%ext = fpext half %sel to double
252+
ret double %ext
253+
}
254+
255+
define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
256+
; CHECK-LABEL: @trunc_sel_larger_fpext_vec(
257+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half>
258+
; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double>
259+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01>
260+
; CHECK-NEXT: ret <2 x double> [[EXT]]
261+
;
262+
%trunc = fptrunc <2 x float> %a to <2 x half>
263+
%sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
264+
%ext = fpext <2 x half> %sel to <2 x double>
265+
ret <2 x double> %ext
266+
}
267+
268+
define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) {
269+
; CHECK-LABEL: @trunc_sel_smaller_fpext(
270+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double %a to half
271+
; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
272+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01
273+
; CHECK-NEXT: ret float [[EXT]]
274+
;
275+
%trunc = fptrunc double %a to half
276+
%sel = select i1 %cmp, half %trunc, half 42.0
277+
%ext = fpext half %sel to float
278+
ret float %ext
279+
}
280+
281+
define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) {
282+
; CHECK-LABEL: @trunc_sel_smaller_fpext_vec(
283+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x double> %a to <2 x half>
284+
; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
285+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
286+
; CHECK-NEXT: ret <2 x float> [[EXT]]
287+
;
288+
%trunc = fptrunc <2 x double> %a to <2 x half>
289+
%sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
290+
%ext = fpext <2 x half> %sel to <2 x float>
291+
ret <2 x float> %ext
292+
}
293+
294+
define float @trunc_sel_equal_fpext(float %a, i1 %cmp) {
295+
; CHECK-LABEL: @trunc_sel_equal_fpext(
296+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float %a to half
297+
; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
298+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01
299+
; CHECK-NEXT: ret float [[EXT]]
300+
;
301+
%trunc = fptrunc float %a to half
302+
%sel = select i1 %cmp, half %trunc, half 42.0
303+
%ext = fpext half %sel to float
304+
ret float %ext
305+
}
306+
307+
define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
308+
; CHECK-LABEL: @trunc_sel_equal_fpext_vec(
309+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half>
310+
; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
311+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
312+
; CHECK-NEXT: ret <2 x float> [[EXT]]
313+
;
314+
%trunc = fptrunc <2 x float> %a to <2 x half>
315+
%sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
316+
%ext = fpext <2 x half> %sel to <2 x float>
317+
ret <2 x float> %ext
318+
}
319+
50320
define i32 @test_sext1(i1 %cca, i1 %ccb) {
51321
; CHECK-LABEL: @test_sext1(
52322
; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca

0 commit comments

Comments
 (0)
Please sign in to comment.