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rotaterightrotateright
committedNov 18, 2016
[InstCombine] add tests to show likely unwanted select widening; NFC
This is a prerequisite patch for D26556: https://reviews.llvm.org/D26556 ...because there was no direct coverage for these folds (which in some cases are adding instructions). llvm-svn: 287400
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‎llvm/test/Transforms/InstCombine/select-bitext.ll

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@@ -1,6 +1,38 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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; Widen a select of constants to eliminate an extend.
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define i16 @sel_sext_constants(i1 %cmp) {
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; CHECK-LABEL: @sel_sext_constants(
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i16 -1, i16 42
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; CHECK-NEXT: ret i16 [[EXT]]
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;
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%sel = select i1 %cmp, i8 255, i8 42
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%ext = sext i8 %sel to i16
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ret i16 %ext
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}
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define i16 @sel_zext_constants(i1 %cmp) {
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; CHECK-LABEL: @sel_zext_constants(
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i16 255, i16 42
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; CHECK-NEXT: ret i16 [[EXT]]
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;
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%sel = select i1 %cmp, i8 255, i8 42
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%ext = zext i8 %sel to i16
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ret i16 %ext
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}
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define double @sel_fpext_constants(i1 %cmp) {
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; CHECK-LABEL: @sel_fpext_constants(
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, double -2.550000e+02, double 4.200000e+01
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; CHECK-NEXT: ret double [[EXT]]
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;
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%sel = select i1 %cmp, float -255.0, float 42.0
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%ext = fpext float %sel to double
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ret double %ext
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}
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; FIXME: We should not grow the size of the select in the next 4 cases.
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define i64 @sel_sext(i32 %a, i1 %cmp) {
@@ -47,6 +79,244 @@ define <4 x i64> @sel_zext_vec(<4 x i32> %a, <4 x i1> %cmp) {
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ret <4 x i64> %ext
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}
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; FIXME: The next 18 tests cycle through trunc+select and {larger,smaller,equal} {sext,zext,fpext} {scalar,vector}.
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; The only cases where we eliminate an instruction are equal zext with scalar/vector, so that's probably the only
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; way to justify widening the select.
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define i64 @trunc_sel_larger_sext(i32 %a, i1 %cmp) {
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; CHECK-LABEL: @trunc_sel_larger_sext(
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 %a to i16
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; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i64
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
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; CHECK-NEXT: ret i64 [[EXT]]
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;
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%trunc = trunc i32 %a to i16
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%sel = select i1 %cmp, i16 %trunc, i16 42
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%ext = sext i16 %sel to i64
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ret i64 %ext
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}
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define <2 x i64> @trunc_sel_larger_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
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; CHECK-LABEL: @trunc_sel_larger_sext_vec(
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; CHECK-NEXT: [[TRUNC:%.*]] = zext <2 x i32> %a to <2 x i64>
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; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i64> [[TRUNC]], <i64 48, i64 48>
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[SEXT]], <i64 48, i64 48>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP1]], <2 x i64> <i64 42, i64 43>
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; CHECK-NEXT: ret <2 x i64> [[EXT]]
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;
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%trunc = trunc <2 x i32> %a to <2 x i16>
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%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
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%ext = sext <2 x i16> %sel to <2 x i64>
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ret <2 x i64> %ext
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}
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define i32 @trunc_sel_smaller_sext(i64 %a, i1 %cmp) {
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; CHECK-LABEL: @trunc_sel_smaller_sext(
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 %a to i16
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; CHECK-NEXT: [[TMP1:%.*]] = sext i16 [[TRUNC]] to i32
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
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; CHECK-NEXT: ret i32 [[EXT]]
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;
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%trunc = trunc i64 %a to i16
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%sel = select i1 %cmp, i16 %trunc, i16 42
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%ext = sext i16 %sel to i32
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ret i32 %ext
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}
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define <2 x i32> @trunc_sel_smaller_sext_vec(<2 x i64> %a, <2 x i1> %cmp) {
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; CHECK-LABEL: @trunc_sel_smaller_sext_vec(
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
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; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> [[TRUNC]], <i32 16, i32 16>
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], <i32 16, i32 16>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
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; CHECK-NEXT: ret <2 x i32> [[EXT]]
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;
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%trunc = trunc <2 x i64> %a to <2 x i16>
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%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
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%ext = sext <2 x i16> %sel to <2 x i32>
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ret <2 x i32> %ext
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}
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define i32 @trunc_sel_equal_sext(i32 %a, i1 %cmp) {
141+
; CHECK-LABEL: @trunc_sel_equal_sext(
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; CHECK-NEXT: [[SEXT:%.*]] = shl i32 %a, 16
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; CHECK-NEXT: [[TMP1:%.*]] = ashr exact i32 [[SEXT]], 16
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
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; CHECK-NEXT: ret i32 [[EXT]]
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;
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%trunc = trunc i32 %a to i16
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%sel = select i1 %cmp, i16 %trunc, i16 42
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%ext = sext i16 %sel to i32
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ret i32 %ext
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}
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define <2 x i32> @trunc_sel_equal_sext_vec(<2 x i32> %a, <2 x i1> %cmp) {
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; CHECK-LABEL: @trunc_sel_equal_sext_vec(
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; CHECK-NEXT: [[SEXT:%.*]] = shl <2 x i32> %a, <i32 16, i32 16>
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; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[SEXT]], <i32 16, i32 16>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
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; CHECK-NEXT: ret <2 x i32> [[EXT]]
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;
160+
%trunc = trunc <2 x i32> %a to <2 x i16>
161+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
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%ext = sext <2 x i16> %sel to <2 x i32>
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ret <2 x i32> %ext
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}
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define i64 @trunc_sel_larger_zext(i32 %a, i1 %cmp) {
167+
; CHECK-LABEL: @trunc_sel_larger_zext(
168+
; CHECK-NEXT: [[TRUNC_MASK:%.*]] = and i32 %a, 65535
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; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TRUNC_MASK]] to i64
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i64 [[TMP1]], i64 42
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; CHECK-NEXT: ret i64 [[EXT]]
172+
;
173+
%trunc = trunc i32 %a to i16
174+
%sel = select i1 %cmp, i16 %trunc, i16 42
175+
%ext = zext i16 %sel to i64
176+
ret i64 %ext
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}
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179+
define <2 x i64> @trunc_sel_larger_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
180+
; CHECK-LABEL: @trunc_sel_larger_zext_vec(
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535>
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; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i64> [[TMP2]], <2 x i64> <i64 42, i64 43>
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; CHECK-NEXT: ret <2 x i64> [[EXT]]
185+
;
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%trunc = trunc <2 x i32> %a to <2 x i16>
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%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
188+
%ext = zext <2 x i16> %sel to <2 x i64>
189+
ret <2 x i64> %ext
190+
}
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define i32 @trunc_sel_smaller_zext(i64 %a, i1 %cmp) {
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; CHECK-LABEL: @trunc_sel_smaller_zext(
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; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 %a to i32
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; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 65535
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP2]], i32 42
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; CHECK-NEXT: ret i32 [[EXT]]
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;
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%trunc = trunc i64 %a to i16
200+
%sel = select i1 %cmp, i16 %trunc, i16 42
201+
%ext = zext i16 %sel to i32
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ret i32 %ext
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}
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define <2 x i32> @trunc_sel_smaller_zext_vec(<2 x i64> %a, <2 x i1> %cmp) {
206+
; CHECK-LABEL: @trunc_sel_smaller_zext_vec(
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc <2 x i64> %a to <2 x i32>
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; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> [[TRUNC]], <i32 65535, i32 65535>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
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; CHECK-NEXT: ret <2 x i32> [[EXT]]
211+
;
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%trunc = trunc <2 x i64> %a to <2 x i16>
213+
%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
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%ext = zext <2 x i16> %sel to <2 x i32>
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ret <2 x i32> %ext
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}
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define i32 @trunc_sel_equal_zext(i32 %a, i1 %cmp) {
219+
; CHECK-LABEL: @trunc_sel_equal_zext(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 %a, 65535
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, i32 [[TMP1]], i32 42
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; CHECK-NEXT: ret i32 [[EXT]]
223+
;
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%trunc = trunc i32 %a to i16
225+
%sel = select i1 %cmp, i16 %trunc, i16 42
226+
%ext = zext i16 %sel to i32
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ret i32 %ext
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}
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define <2 x i32> @trunc_sel_equal_zext_vec(<2 x i32> %a, <2 x i1> %cmp) {
231+
; CHECK-LABEL: @trunc_sel_equal_zext_vec(
232+
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i32> %a, <i32 65535, i32 65535>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x i32> [[TMP1]], <2 x i32> <i32 42, i32 43>
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; CHECK-NEXT: ret <2 x i32> [[EXT]]
235+
;
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%trunc = trunc <2 x i32> %a to <2 x i16>
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%sel = select <2 x i1> %cmp, <2 x i16> %trunc, <2 x i16> <i16 42, i16 43>
238+
%ext = zext <2 x i16> %sel to <2 x i32>
239+
ret <2 x i32> %ext
240+
}
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define double @trunc_sel_larger_fpext(float %a, i1 %cmp) {
243+
; CHECK-LABEL: @trunc_sel_larger_fpext(
244+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float %a to half
245+
; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to double
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; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, double [[TMP1]], double 4.200000e+01
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; CHECK-NEXT: ret double [[EXT]]
248+
;
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%trunc = fptrunc float %a to half
250+
%sel = select i1 %cmp, half %trunc, half 42.0
251+
%ext = fpext half %sel to double
252+
ret double %ext
253+
}
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define <2 x double> @trunc_sel_larger_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
256+
; CHECK-LABEL: @trunc_sel_larger_fpext_vec(
257+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half>
258+
; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x double>
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; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x double> [[TMP1]], <2 x double> <double 4.200000e+01, double 4.300000e+01>
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; CHECK-NEXT: ret <2 x double> [[EXT]]
261+
;
262+
%trunc = fptrunc <2 x float> %a to <2 x half>
263+
%sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
264+
%ext = fpext <2 x half> %sel to <2 x double>
265+
ret <2 x double> %ext
266+
}
267+
268+
define float @trunc_sel_smaller_fpext(double %a, i1 %cmp) {
269+
; CHECK-LABEL: @trunc_sel_smaller_fpext(
270+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc double %a to half
271+
; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
272+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01
273+
; CHECK-NEXT: ret float [[EXT]]
274+
;
275+
%trunc = fptrunc double %a to half
276+
%sel = select i1 %cmp, half %trunc, half 42.0
277+
%ext = fpext half %sel to float
278+
ret float %ext
279+
}
280+
281+
define <2 x float> @trunc_sel_smaller_fpext_vec(<2 x double> %a, <2 x i1> %cmp) {
282+
; CHECK-LABEL: @trunc_sel_smaller_fpext_vec(
283+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x double> %a to <2 x half>
284+
; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
285+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
286+
; CHECK-NEXT: ret <2 x float> [[EXT]]
287+
;
288+
%trunc = fptrunc <2 x double> %a to <2 x half>
289+
%sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
290+
%ext = fpext <2 x half> %sel to <2 x float>
291+
ret <2 x float> %ext
292+
}
293+
294+
define float @trunc_sel_equal_fpext(float %a, i1 %cmp) {
295+
; CHECK-LABEL: @trunc_sel_equal_fpext(
296+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc float %a to half
297+
; CHECK-NEXT: [[TMP1:%.*]] = fpext half [[TRUNC]] to float
298+
; CHECK-NEXT: [[EXT:%.*]] = select i1 %cmp, float [[TMP1]], float 4.200000e+01
299+
; CHECK-NEXT: ret float [[EXT]]
300+
;
301+
%trunc = fptrunc float %a to half
302+
%sel = select i1 %cmp, half %trunc, half 42.0
303+
%ext = fpext half %sel to float
304+
ret float %ext
305+
}
306+
307+
define <2 x float> @trunc_sel_equal_fpext_vec(<2 x float> %a, <2 x i1> %cmp) {
308+
; CHECK-LABEL: @trunc_sel_equal_fpext_vec(
309+
; CHECK-NEXT: [[TRUNC:%.*]] = fptrunc <2 x float> %a to <2 x half>
310+
; CHECK-NEXT: [[TMP1:%.*]] = fpext <2 x half> [[TRUNC]] to <2 x float>
311+
; CHECK-NEXT: [[EXT:%.*]] = select <2 x i1> %cmp, <2 x float> [[TMP1]], <2 x float> <float 4.200000e+01, float 4.300000e+01>
312+
; CHECK-NEXT: ret <2 x float> [[EXT]]
313+
;
314+
%trunc = fptrunc <2 x float> %a to <2 x half>
315+
%sel = select <2 x i1> %cmp, <2 x half> %trunc, <2 x half> <half 42.0, half 43.0>
316+
%ext = fpext <2 x half> %sel to <2 x float>
317+
ret <2 x float> %ext
318+
}
319+
50320
define i32 @test_sext1(i1 %cca, i1 %ccb) {
51321
; CHECK-LABEL: @test_sext1(
52322
; CHECK-NEXT: [[FOLD_R:%.*]] = and i1 %ccb, %cca

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