[LLD][PPC] Small data section handling with synthetic _SDA_BASE_ symbols

[jackoalan]

Summary

LLD-side extension of D26344.

This implements R_PPC_EMB_SDA21 relocations in executable targets. C runtime init implementations may use _SDA_BASE_ and _SDA2_BASE_ symbols to globally initialize r13 and r2 respectively.

This patch also adds other relocations that LLVM itself may emit during PPC target lowering, and also enables target bi-endianness.

[jackoalan]

Rebase with upstream master. Add -sda-base= and -sda2-base= linker options for overriding synthetic values.

[jackoalan]

_SDA_BASE_ symbols need direct calls to ElfSym<ELFT>::addSynthetic to be initially created.

[jackoalan]

Add PPCTargetInfo::relocateOne() R_PPC_ADDR14 and R_PPC_REL14 handling.

[jackoalan]

Make PPC target bi-endian in the same manner as MIPS. Tidy up PPCTargetInfo::relocateOne(). Rebase with latest master

[jackoalan]

Ensure Config->OSABI == ELF::ELFOSABI_STANDALONE is true when synthesizing _SDA_BASE_ symbols.

Also add relocation tests for ADDR14 and REL14.

[jackoalan]

Test now uses sda21 symbol variant as changed from sdarx.

[jackoalan]

Implement getBitcodeOSABIKind, which just responds to Triple::EABI for now.

[jackoalan]

Rebase against upstream master. Cleanup PPCTargetInfo::relocateOne() with mask constants.

ELF/Config.h

struct Configuration {
   Target2Policy Target2 = Target2Policy::GotRel;
   BuildIdKind BuildId = BuildIdKind::None;
   ELFKind EKind = ELFNoneKind;
   uint16_t DefaultSymbolVersion = llvm::ELF::VER_NDX_GLOBAL;
   uint16_t EMachine = llvm::ELF::EM_NONE;
   uint64_t EntryAddr = 0;
   uint64_t ImageBase;
   uint64_t MaxPageSize;
+  uint64_t SdaBase = ~0;
+  uint64_t Sda2Base = ~0;
   uint64_t ZStackSize;
   unsigned LtoPartitions;
   unsigned LtoO;
   unsigned Optimize;
   unsigned ThinLtoJobs;
 };
 
 // The only instance of Configuration struct.
 extern Configuration *Config;
 
 } // namespace elf
 } // namespace lld
 
 #endif

ELF/Driver.cpp

if (S.getAsInteger(0, V)) {
     error("-image-base: number expected, but got " + S);
     return 0;
   }
   if ((V % Target->MaxPageSize) != 0)
     warn("-image-base: address isn't multiple of page size: " + S);
   return V;
 }
 
+// Parses -sda-base options.
+static std::pair<uint64_t, uint64_t> getSdaBases(opt::InputArgList &Args) {
+  // If argument not given or invalid, use ~0 value; triggering
+  // midpoint calculation in the first matching small output section.
+  auto CheckSdaArg = [](opt::Arg *Arg) -> uint64_t {
+    if (Arg) {
+      StringRef S = Arg->getValue();
+      uint64_t V;
+      if (S.getAsInteger(0, V))
+        error(Arg->getOption().getPrefixedName() +
+              ": number expected, but got " + S);
+      else
+        return V;
+    }
+    return ~0;
+  };
+
+  return std::make_pair(CheckSdaArg(Args.getLastArg(OPT_sda_base)),
+                        CheckSdaArg(Args.getLastArg(OPT_sda2_base)));
+}
+
 // Do actual linking. Note that when this function is called,
 // all linker scripts have already been parsed.
 template <class ELFT> void LinkerDriver::link(opt::InputArgList &Args) {
   SymbolTable<ELFT> Symtab;
   elf::Symtab<ELFT>::X = &Symtab;
 
   std::unique_ptr<TargetInfo> TI(createTarget());
   Target = TI.get();
   LinkerScript<ELFT> LS;
   ScriptBase = Script<ELFT>::X = &LS;
 
   Config->Rela =
       ELFT::Is64Bits || Config->EMachine == EM_X86_64 || Config->MipsN32Abi;
   Config->Mips64EL =
       (Config->EMachine == EM_MIPS && Config->EKind == ELF64LEKind);
   Config->ImageBase = getImageBase(Args);
+  std::tie(Config->SdaBase, Config->Sda2Base) = getSdaBases(Args);
 
   // Default output filename is "a.out" by the Unix tradition.
   if (Config->OutputFile.empty())
     Config->OutputFile = "a.out";
 
   // Handle --trace-symbol.
   for (auto *Arg : Args.filtered(OPT_trace_symbol))
     Symtab.trace(Arg->getValue());

ELF/InputSection.cpp

static typename ELFT::uint getSymVA(uint32_t Type, typename ELFT::uint A,
   case R_TLSLD_PC:
     return In<ELFT>::Got->getTlsIndexVA() + A - P;
   case R_THUNK_ABS:
     return Body.getThunkVA<ELFT>() + A;
   case R_THUNK_PC:
   case R_THUNK_PLT_PC:
     return Body.getThunkVA<ELFT>() + A - P;
   case R_PPC_TOC:
-    return getPPC64TocBase() + A;
+    return getPPC64TocBase<ELFT>() + A;
   case R_TLSGD:
     return In<ELFT>::Got->getGlobalDynOffset(Body) + A -
            In<ELFT>::Got->getSize();
   case R_TLSGD_PC:
     return In<ELFT>::Got->getGlobalDynAddr(Body) + A - P;
   case R_TLSDESC:
     return In<ELFT>::Got->getGlobalDynAddr(Body) + A;
   case R_TLSDESC_PAGE:
case R_PC:
     }
   case R_RELAX_GOT_PC:
     return Body.getVA<ELFT>(A) - P;
   case R_PLT_PAGE_PC:
   case R_PAGE_PC:
     if (Body.isUndefined() && !Body.isLocal() && Body.symbol()->isWeak())
       return getAArch64Page(A);
     return getAArch64Page(Body.getVA<ELFT>(A)) - getAArch64Page(P);
+  case R_PPC_SDA: {
+    auto CheckReturn = [](int64_t Val, uint32_t Reg) -> typename ELFT::uint {
+      if (Val > 32767 || Val < -32768)
+        error("Small data relocation delta exceeds 16-bit value");
+      return (Val & 0xffff) | (Reg << 16);
+    };
+    const DefinedRegular<ELFT> *RelSym = dyn_cast<DefinedRegular<ELFT>>(&Body);
+    if (RelSym && RelSym->Section) {
+      const InputSectionBase<ELFT> *Section = RelSym->Section;
+      if (Section->OutSec) {
+        // Relocate relative to _SDA_BASE_ or _SDA2_BASE_ synthetic symbols.
+        const OutputSectionBase *OutSec = RelSym->Section->OutSec;
+        if (ElfSym<ELFT>::SdaBase &&
+            (OutSec->getName() == ".sdata" || OutSec->getName() == ".sbss"))
+          return CheckReturn(Body.getVA<ELFT>(A) -
+                             int64_t(ElfSym<ELFT>::SdaBase->Value), 13);
+        if (ElfSym<ELFT>::Sda2Base && OutSec->getName() == ".sdata2")
+          return CheckReturn(Body.getVA<ELFT>(A) -
+                             int64_t(ElfSym<ELFT>::Sda2Base->Value), 2);
+      }
+    }
+    error("Unable to perform small data relocation without designated section");
+    return 0;
+  }
   }
   llvm_unreachable("Invalid expression");
 }
 
 // This function applies relocations to sections without SHF_ALLOC bit.
 // Such sections are never mapped to memory at runtime. Debug sections are
 // an example. Relocations in non-alloc sections are much easier to
 // handle than in allocated sections because it will never need complex

ELF/Options.td

def reproduce: S<"reproduce">,
   HelpText<"Dump linker invocation and input files for debugging">;
 
 def rpath: S<"rpath">, HelpText<"Add a DT_RUNPATH to the output">;
 
 def relocatable: F<"relocatable">, HelpText<"Create relocatable object file">;
 
 def script: S<"script">, HelpText<"Read linker script">;
 
+def sda_base : J<"sda-base=">, HelpText<"Set the small data base address">;
+
+def sda2_base : J<"sda2-base=">, HelpText<"Set the second small data base address">;
+
 def section_start: S<"section-start">, MetaVarName<"<address>">,
   HelpText<"Set address of section">;
 
 def shared: F<"shared">, HelpText<"Build a shared object">;
 
 def soname: J<"soname=">, HelpText<"Set DT_SONAME">;
 
 def sort_section: S<"sort-section">, HelpText<"Specifies sections sorting rule when linkerscript is used">;

ELF/Relocations.h

enum RelExpr {
   R_PAGE_PC,
   R_PC,
   R_PLT,
   R_PLT_PC,
   R_PLT_PAGE_PC,
   R_PPC_OPD,
   R_PPC_PLT_OPD,
   R_PPC_TOC,
+  R_PPC_SDA,
   R_RELAX_GOT_PC,
   R_RELAX_GOT_PC_NOPIC,
   R_RELAX_TLS_GD_TO_IE,
   R_RELAX_TLS_GD_TO_IE_END,
   R_RELAX_TLS_GD_TO_IE_ABS,
   R_RELAX_TLS_GD_TO_IE_PAGE_PC,
   R_RELAX_TLS_GD_TO_LE,
   R_RELAX_TLS_GD_TO_LE_NEG,

ELF/Relocations.cpp

if (Type == R_MIPS_LO16 && Expr == R_PC)
       // calculation "AHL + GP - P + 4". Let's add 4 right here.
       // For details see p. 4-19 at
       // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
       Addend += 4;
     if (Expr == R_MIPS_GOTREL && Body.isLocal())
       Addend += File.MipsGp0;
   }
   if (Config->Pic && Config->EMachine == EM_PPC64 && Type == R_PPC64_TOC)
-    Addend += getPPC64TocBase();
+    Addend += getPPC64TocBase<ELFT>();
   return Addend;
 }
 
 // Find symbol that encloses given offset. Used for error reporting.
 template <class ELFT>
 static DefinedRegular<ELFT> *getSymbolAt(InputSectionBase<ELFT> *S,
                                          typename ELFT::uint Offset) {
   for (SymbolBody *B : S->getFile()->getSymbols())

ELF/Symbols.h

template <class ELFT> struct ElfSym {
   static DefinedRegular<ELFT> *Edata2;
 
   // The content for _end and end symbols.
   static DefinedRegular<ELFT> *End;
   static DefinedRegular<ELFT> *End2;
 
   // The content for _gp_disp symbol for MIPS target.
   static SymbolBody *MipsGpDisp;
+
+  // The content for _SDA_BASE_ and _SDA2_BASE_ symbols.
+  static DefinedSynthetic<ELFT> *SdaBase;
+  static DefinedSynthetic<ELFT> *Sda2Base;
 };
 
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::EhdrStart;
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::Etext;
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::Etext2;
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::Edata;
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::Edata2;
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::End;
 template <class ELFT> DefinedRegular<ELFT> *ElfSym<ELFT>::End2;
 template <class ELFT> SymbolBody *ElfSym<ELFT>::MipsGpDisp;
+template <class ELFT> DefinedSynthetic<ELFT> *ElfSym<ELFT>::SdaBase;
+template <class ELFT> DefinedSynthetic<ELFT> *ElfSym<ELFT>::Sda2Base;
 
 // A real symbol object, SymbolBody, is usually stored within a Symbol. There's
 // always one Symbol for each symbol name. The resolver updates the SymbolBody
 // stored in the Body field of this object as it resolves symbols. Symbol also
 // holds computed properties of symbol names.
 struct Symbol {
   // Symbol binding. This is on the Symbol to track changes during resolution.
   // In particular:

ELF/Target.h

public:
   virtual void relaxGot(uint8_t *Loc, uint64_t Val) const;
   virtual void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
   virtual void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
   virtual void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
   virtual void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const;
 };
 
 StringRef getRelName(uint32_t Type);
+template <class ELFT>
 uint64_t getPPC64TocBase();
 
 const unsigned MipsGPOffset = 0x7ff0;
 
 extern TargetInfo *Target;
 TargetInfo *createTarget();
 }
 }
 
 #endif

ELF/Target.cpp

 using namespace llvm::ELF;
 
 namespace lld {
 namespace elf {
 
 TargetInfo *Target;
 
 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
-static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); }
 
 StringRef getRelName(uint32_t Type) {
   return getELFRelocationTypeName(Config->EMachine, Type);
 }
 
 template <unsigned N> static void checkInt(int64_t V, uint32_t Type) {
   if (!isInt<N>(V))
     error("relocation " + getRelName(Type) + " out of range");
public:
   void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 
 private:
   void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
                      uint8_t ModRm) const;
 };
 
-class PPCTargetInfo final : public TargetInfo {
+template <class ELFT> class PPCTargetInfo final : public TargetInfo {
 public:
   PPCTargetInfo();
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
 };
 
-class PPC64TargetInfo final : public TargetInfo {
+template <class ELFT> class PPC64TargetInfo final : public TargetInfo {
 public:
   PPC64TargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 
case EM_MIPS:
     case ELF64LEKind:
       return new MipsTargetInfo<ELF64LE>();
     case ELF64BEKind:
       return new MipsTargetInfo<ELF64BE>();
     default:
       fatal("unsupported MIPS target");
     }
   case EM_PPC:
-    return new PPCTargetInfo();
+    switch (Config->EKind) {
+    case ELF32LEKind:
+      return new PPCTargetInfo<ELF32LE>();
+    case ELF32BEKind:
+      return new PPCTargetInfo<ELF32BE>();
+    default:
+      fatal("unsupported PPC target");
+    }
   case EM_PPC64:
-    return new PPC64TargetInfo();
+    switch (Config->EKind) {
+    case ELF64LEKind:
+      return new PPC64TargetInfo<ELF64LE>();
+    case ELF64BEKind:
+      return new PPC64TargetInfo<ELF64BE>();
+    default:
+      fatal("unsupported PPC target");
+    }
   case EM_X86_64:
     if (Config->EKind == ELF32LEKind)
       return new X86_64TargetInfo<ELF32LE>();
     return new X86_64TargetInfo<ELF64LE>();
   }
   fatal("unknown target machine");
 }
 

 static uint16_t applyPPCLo(uint64_t V) { return V; }
 static uint16_t applyPPCHi(uint64_t V) { return V >> 16; }
 static uint16_t applyPPCHa(uint64_t V) { return (V + 0x8000) >> 16; }
 static uint16_t applyPPCHigher(uint64_t V) { return V >> 32; }
 static uint16_t applyPPCHighera(uint64_t V) { return (V + 0x8000) >> 32; }
 static uint16_t applyPPCHighest(uint64_t V) { return V >> 48; }
 static uint16_t applyPPCHighesta(uint64_t V) { return (V + 0x8000) >> 48; }
 
-PPCTargetInfo::PPCTargetInfo() {}
+template <class ELFT>
+PPCTargetInfo<ELFT>::PPCTargetInfo() {}
 
-void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
+template <class ELFT>
+void PPCTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
                                       uint64_t Val) const {
+  const endianness E = ELFT::TargetEndianness;
   switch (Type) {
+  case R_PPC_ADDR16_HI:
+    write16<E>(Loc, applyPPCHi(Val));
+    break;
   case R_PPC_ADDR16_HA:
-    write16be(Loc, applyPPCHa(Val));
+    write16<E>(Loc, applyPPCHa(Val));
     break;
   case R_PPC_ADDR16_LO:
-    write16be(Loc, applyPPCLo(Val));
+    write16<E>(Loc, applyPPCLo(Val));
     break;
   case R_PPC_ADDR32:
   case R_PPC_REL32:
-    write32be(Loc, Val);
+    write32<E>(Loc, Val);
     break;
-  case R_PPC_REL24:
-    or32be(Loc, Val & 0x3FFFFFC);
+  case R_PPC_ADDR24:
+  case R_PPC_REL24: {
+    checkAlignment<4>(Val, Type);
+    uint32_t Inst = read32<E>(Loc) & ~0x3FFFFFC;
+    Inst |= Val & 0x3FFFFFC;
+    write32<E>(Loc, Inst);
     break;
+  }
+  case R_PPC_ADDR14:
+  case R_PPC_REL14: {
+    checkAlignment<4>(Val, Type);
+    uint32_t Inst = read32<E>(Loc) & ~0xFFFC;
+    Inst |= Val & 0xFFFC;
+    write32<E>(Loc, Inst);
+    break;
+  }
+  case R_PPC_EMB_SDA21: {
+    // SDA21 relocation entry is offset one byte into instruction
+    uint8_t *InstLoc = Loc - (E == llvm::support::big ? 1 : 0);
+    uint32_t Inst = read32<E>(InstLoc) & ~0x1FFFFF;
+    Inst |= Val & 0x1FFFFF;
+    write32<E>(InstLoc, Inst);
+    break;
+  }
   default:
     fatal("unrecognized reloc " + Twine(Type));
   }
 }
 
-RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
+template <class ELFT>
+RelExpr PPCTargetInfo<ELFT>::getRelExpr(uint32_t Type,
+                                        const SymbolBody &S) const {
   switch (Type) {
   case R_PPC_REL24:
   case R_PPC_REL32:
+  case R_PPC_REL14:
     return R_PC;
+  case R_PPC_EMB_SDA21:
+    return R_PPC_SDA;
   default:
     return R_ABS;
   }
 }
 
-PPC64TargetInfo::PPC64TargetInfo() {
+template <class ELFT>
+PPC64TargetInfo<ELFT>::PPC64TargetInfo() {
   PltRel = GotRel = R_PPC64_GLOB_DAT;
   RelativeRel = R_PPC64_RELATIVE;
   GotEntrySize = 8;
   GotPltEntrySize = 8;
   PltEntrySize = 32;
   PltHeaderSize = 0;
 
   // We need 64K pages (at least under glibc/Linux, the loader won't
   // set different permissions on a finer granularity than that).
   MaxPageSize = 65536;
 
   // The PPC64 ELF ABI v1 spec, says:
   //
   //   It is normally desirable to put segments with different characteristics
   //   in separate 256 Mbyte portions of the address space, to give the
   //   operating system full paging flexibility in the 64-bit address space.
   //
   // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
   // use 0x10000000 as the starting address.
   DefaultImageBase = 0x10000000;
 }
 
 static uint64_t PPC64TocOffset = 0x8000;
 
+template <class ELFT>
 uint64_t getPPC64TocBase() {
   // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
   // TOC starts where the first of these sections starts. We always create a
   // .got when we see a relocation that uses it, so for us the start is always
   // the .got.
-  uint64_t TocVA = In<ELF64BE>::Got->getVA();
+  uint64_t TocVA = In<ELFT>::Got->getVA();
 
   // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
   // thus permitting a full 64 Kbytes segment. Note that the glibc startup
   // code (crt1.o) assumes that you can get from the TOC base to the
   // start of the .toc section with only a single (signed) 16-bit relocation.
   return TocVA + PPC64TocOffset;
 }
 
-RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
+template uint64_t getPPC64TocBase<ELF64BE>();
+template uint64_t getPPC64TocBase<ELF64LE>();
+template uint64_t getPPC64TocBase<ELF32BE>();
+template uint64_t getPPC64TocBase<ELF32LE>();
+
+template <class ELFT>
+RelExpr PPC64TargetInfo<ELFT>::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   switch (Type) {
   default:
     return R_ABS;
   case R_PPC64_TOC16:
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HA:
   case R_PPC64_TOC16_HI:
   case R_PPC64_TOC16_LO:
   case R_PPC64_TOC16_LO_DS:
     return R_GOTREL;
   case R_PPC64_TOC:
     return R_PPC_TOC;
   case R_PPC64_REL24:
     return R_PPC_PLT_OPD;
   }
 }
 
-void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
+template <class ELFT>
+void PPC64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
                                      uint64_t PltEntryAddr, int32_t Index,
                                      unsigned RelOff) const {
-  uint64_t Off = GotEntryAddr - getPPC64TocBase();
+  uint64_t Off = GotEntryAddr - getPPC64TocBase<ELFT>();
+  const endianness E = ELFT::TargetEndianness;
 
   // FIXME: What we should do, in theory, is get the offset of the function
   // descriptor in the .opd section, and use that as the offset from %r2 (the
   // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
   // be a pointer to the function descriptor in the .opd section. Using
   // this scheme is simpler, but requires an extra indirection per PLT dispatch.
 
-  write32be(Buf, 0xf8410028);                       // std %r2, 40(%r1)
-  write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
-  write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
-  write32be(Buf + 12, 0xe96c0000);                  // ld %r11,0(%r12)
-  write32be(Buf + 16, 0x7d6903a6);                  // mtctr %r11
-  write32be(Buf + 20, 0xe84c0008);                  // ld %r2,8(%r12)
-  write32be(Buf + 24, 0xe96c0010);                  // ld %r11,16(%r12)
-  write32be(Buf + 28, 0x4e800420);                  // bctr
+  write32<E>(Buf, 0xf8410028);                       // std %r2, 40(%r1)
+  write32<E>(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
+  write32<E>(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
+  write32<E>(Buf + 12, 0xe96c0000);                  // ld %r11,0(%r12)
+  write32<E>(Buf + 16, 0x7d6903a6);                  // mtctr %r11
+  write32<E>(Buf + 20, 0xe84c0008);                  // ld %r2,8(%r12)
+  write32<E>(Buf + 24, 0xe96c0010);                  // ld %r11,16(%r12)
+  write32<E>(Buf + 28, 0x4e800420);                  // bctr
 }
 
 static std::pair<uint32_t, uint64_t> toAddr16Rel(uint32_t Type, uint64_t Val) {
   uint64_t V = Val - PPC64TocOffset;
   switch (Type) {
   case R_PPC64_TOC16:
     return {R_PPC64_ADDR16, V};
   case R_PPC64_TOC16_DS:
     return {R_PPC64_ADDR16_DS, V};
   case R_PPC64_TOC16_HA:
     return {R_PPC64_ADDR16_HA, V};
   case R_PPC64_TOC16_HI:
     return {R_PPC64_ADDR16_HI, V};
   case R_PPC64_TOC16_LO:
     return {R_PPC64_ADDR16_LO, V};
   case R_PPC64_TOC16_LO_DS:
     return {R_PPC64_ADDR16_LO_DS, V};
   default:
     return {Type, Val};
   }
 }
 
-void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
+template <class ELFT>
+void PPC64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
                                         uint64_t Val) const {
   // For a TOC-relative relocation, proceed in terms of the corresponding
   // ADDR16 relocation type.
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
+  const endianness E = ELFT::TargetEndianness;
   switch (Type) {
   case R_PPC64_ADDR14: {
     checkAlignment<4>(Val, Type);
     // Preserve the AA/LK bits in the branch instruction
-    uint8_t AALK = Loc[3];
-    write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc));
+    uint8_t AALK = Loc[E == llvm::support::big ? 3 : 0];
+    write16<E>(Loc + (E == llvm::support::big ? 2 : 0),
+               (AALK & 3) | (Val & 0xfffc));
     break;
   }
   case R_PPC64_ADDR16:
     checkInt<16>(Val, Type);
-    write16be(Loc, Val);
+    write16<E>(Loc, Val);
     break;
   case R_PPC64_ADDR16_DS:
     checkInt<16>(Val, Type);
-    write16be(Loc, (read16be(Loc) & 3) | (Val & ~3));
+    write16<E>(Loc, (read16<E>(Loc) & 3) | (Val & ~3));
     break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
-    write16be(Loc, applyPPCHa(Val));
+    write16<E>(Loc, applyPPCHa(Val));
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
-    write16be(Loc, applyPPCHi(Val));
+    write16<E>(Loc, applyPPCHi(Val));
     break;
   case R_PPC64_ADDR16_HIGHER:
-    write16be(Loc, applyPPCHigher(Val));
+    write16<E>(Loc, applyPPCHigher(Val));
     break;
   case R_PPC64_ADDR16_HIGHERA:
-    write16be(Loc, applyPPCHighera(Val));
+    write16<E>(Loc, applyPPCHighera(Val));
     break;
   case R_PPC64_ADDR16_HIGHEST:
-    write16be(Loc, applyPPCHighest(Val));
+    write16<E>(Loc, applyPPCHighest(Val));
     break;
   case R_PPC64_ADDR16_HIGHESTA:
-    write16be(Loc, applyPPCHighesta(Val));
+    write16<E>(Loc, applyPPCHighesta(Val));
     break;
   case R_PPC64_ADDR16_LO:
-    write16be(Loc, applyPPCLo(Val));
+    write16<E>(Loc, applyPPCLo(Val));
     break;
   case R_PPC64_ADDR16_LO_DS:
   case R_PPC64_REL16_LO:
-    write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3));
+    write16<E>(Loc, (read16<E>(Loc) & 3) | (applyPPCLo(Val) & ~3));
     break;
   case R_PPC64_ADDR32:
   case R_PPC64_REL32:
     checkInt<32>(Val, Type);
-    write32be(Loc, Val);
+    write32<E>(Loc, Val);
     break;
   case R_PPC64_ADDR64:
   case R_PPC64_REL64:
   case R_PPC64_TOC:
-    write64be(Loc, Val);
+    write64<E>(Loc, Val);
     break;
   case R_PPC64_REL24: {
     uint32_t Mask = 0x03FFFFFC;
     checkInt<24>(Val, Type);
-    write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask));
+    write32<E>(Loc, (read32<E>(Loc) & ~Mask) | (Val & Mask));
     break;
   }
   default:
     fatal("unrecognized reloc " + Twine(Type));
   }
 }
 
 AArch64TargetInfo::AArch64TargetInfo() {

ELF/Writer.cpp

 
 StringRef elf::getOutputSectionName(StringRef Name) {
   if (Config->Relocatable)
     return Name;
 
   for (StringRef V :
        {".text.", ".rodata.", ".data.rel.ro.", ".data.", ".bss.",
         ".init_array.", ".fini_array.", ".ctors.", ".dtors.", ".tbss.",
-        ".gcc_except_table.", ".tdata.", ".ARM.exidx."}) {
+        ".sdata.", ".sdata2.", ".sbss.", ".gcc_except_table.",
+        ".tdata.", ".ARM.exidx."}) {
     StringRef Prefix = V.drop_back();
     if (Name.startswith(V) || Name == Prefix)
       return Prefix;
   }
 
   // CommonSection is identified as "COMMON" in linker scripts.
   // By default, it should go to .bss section.
   if (Name == "COMMON")
if (Config->EMachine == EM_MIPS) {
 
     // The __gnu_local_gp is a magic symbol equal to the current value of 'gp'
     // pointer. This symbol is used in the code generated by .cpload pseudo-op
     // in case of using -mno-shared option.
     // https://sourceware.org/ml/binutils/2004-12/msg00094.html
     addOptionalRegular("__gnu_local_gp", In<ELFT>::MipsGot, MipsGPOffset);
   }
 
+  if (Config->EMachine == EM_PPC &&
+      Config->OSABI == ELF::ELFOSABI_STANDALONE &&
+      !Config->Shared && !Config->Relocatable) {
+    // In the event a non-relocatable, embedded PPC32 target is being built,
+    // reserve Small Data base registers. These will be relocated midway through
+    // the .sdata and .sdata2 sections (if used). This symbol is meant to
+    // be applied in EABI systems, where r13 and r2 are initialized to these
+    // linker-generated symbols by the C runtime initialization.
+    Symbol *Sym;
+    Sym = Symtab<ELFT>::X->addSynthetic("_SDA_BASE_", nullptr, 0, STV_HIDDEN);
+    ElfSym<ELFT>::SdaBase = cast<DefinedSynthetic<ELFT>>(Sym->body());
+    Sym = Symtab<ELFT>::X->addSynthetic("_SDA2_BASE_", nullptr, 0, STV_HIDDEN);
+    ElfSym<ELFT>::Sda2Base = cast<DefinedSynthetic<ELFT>>(Sym->body());
+  }
+
   // In the assembly for 32 bit x86 the _GLOBAL_OFFSET_TABLE_ symbol
   // is magical and is used to produce a R_386_GOTPC relocation.
   // The R_386_GOTPC relocation value doesn't actually depend on the
   // symbol value, so it could use an index of STN_UNDEF which, according
   // to the spec, means the symbol value is 0.
   // Unfortunately both gas and MC keep the _GLOBAL_OFFSET_TABLE_ symbol in
   // the object file.
   // The situation is even stranger on x86_64 where the assembly doesn't

 // This function is called after we have assigned address and size
 // to each section. This function fixes some predefined absolute
 // symbol values that depend on section address and size.
 template <class ELFT> void Writer<ELFT>::fixAbsoluteSymbols() {
   // __ehdr_start is the location of program headers.
   if (ElfSym<ELFT>::EhdrStart)
     ElfSym<ELFT>::EhdrStart->Value = Out<ELFT>::ProgramHeaders->Addr;
 
+  auto SectionMidpoint = [](OutputSectionBase *Sec) ->
+  typename ELFT::uint {
+    return ((Sec->Size / 2) & ~0x3) + Sec->Addr;
+  };
+
+  // PPC-EABI systems will need the _SDA_BASE_ and _SDA2_BASE_ symbols
+  // synthesized for use by C runtime init. The section midpoints are used
+  // to maximize addressing range. If these values are defined with
+  // -sda-base/-sda2-base options, those are overridden accordingly.
+  if (ElfSym<ELFT>::SdaBase) {
+    if (Config->SdaBase != uint64_t(~0))
+      ElfSym<ELFT>::SdaBase->Value = Config->SdaBase;
+    else {
+      OutputSectionBase *Sec = findSection(".sdata");
+      if (!Sec)
+        Sec = findSection(".sbss");
+      if (Sec)
+        ElfSym<ELFT>::SdaBase->Value = SectionMidpoint(Sec);
+    }
+  }
+  if (ElfSym<ELFT>::Sda2Base) {
+    if (Config->Sda2Base != uint64_t(~0))
+      ElfSym<ELFT>::Sda2Base->Value = Config->Sda2Base;
+    else {
+      OutputSectionBase *Sec = findSection(".sdata2");
+      if (Sec)
+        ElfSym<ELFT>::Sda2Base->Value = SectionMidpoint(Sec);
+    }
+  }
+
   auto Set = [](DefinedRegular<ELFT> *S1, DefinedRegular<ELFT> *S2, uintX_t V) {
     if (S1)
       S1->Value = V;
     if (S2)
       S2->Value = V;
   };
 
   // _etext is the first location after the last read-only loadable segment.

test/ELF/ppc-eabi-relocs.s

+# RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-unknown-eabi %s -o %t
+# RUN: ld.lld %t -o %t2
+# RUN: llvm-objdump -disassemble-all %t2 | FileCheck %s
+# REQUIRES: ppc
+
+.sdata2
+smallstr2:
+  .long 0xDEADD00D
+  .long 0xABCDEFAB
+
+# CHECK: Disassembly of section .sdata2:
+# CHECK: smallstr2:
+# CHECK:    100d4:  de ad d0 0d   stfdu 21, -12275(13)
+# CHECK:    100d8:  ab cd ef ab   lha 30, -4181(13)
+
+.section .R_PPC_EMB_SDA21,"ax",@progbits
+  lis 13, _SDA_BASE_@ha
+  ori 13, 13, _SDA_BASE_@l
+  lis 2, _SDA2_BASE_@ha
+  ori 2, 2, _SDA2_BASE_@l
+  lwz 4, smallstr@sdarx(0)
+  lwz 5, smallstr2@sdarx(0)
+
+# CHECK: Disassembly of section .R_PPC_EMB_SDA21:
+# CHECK: .R_PPC_EMB_SDA21:
+# CHECK: 11000: 3d a0 00 01   lis 13, 1
+# CHECK: 11004: 61 ad 20 04   ori 13, 13, 8196
+# CHECK: 11008: 3c 40 00 01   lis 2, 1
+# CHECK: 1100c: 60 42 00 d8   ori 2, 2, 216
+# CHECK: 11010: 80 8d 00 00   lwz 4, 0(13)
+# CHECK: 11014: 80 a2 ff fc   lwz 5, -4(2)
+
+.sdata
+  .long 0xABCDEFAB
+smallstr:
+  .long 0xDEADBEEF
+
+# CHECK: Disassembly of section .sdata:
+# CHECK: .sdata:
+# CHECK:    12000:  ab cd ef ab   lha 30, -4181(13)
+# CHECK: smallstr:
+# CHECK:    12004:  de ad be ef   stfdu 21, -16657(13)

test/ELF/ppc-relocs.s

 # RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-freebsd %s -o %t
 # RUN: ld.lld %t -o %t2
-# RUN: llvm-objdump -d %t2 | FileCheck %s
+# RUN: llvm-objdump -disassemble-all %t2 | FileCheck %s
 # REQUIRES: ppc
 
 .section .R_PPC_ADDR16_HA,"ax",@progbits
 .globl _start
 _start:
   lis 4, msg@ha
 msg:
   .string "foo"
.FR_PPC_REL24:
   b .Lfoox
 .section .R_PPC_REL24_2,"ax",@progbits
 .Lfoox:
 
 # CHECK: Disassembly of section .R_PPC_REL24:
 # CHECK: .FR_PPC_REL24:
 # CHECK:    11014:       48 00 00 04     b .+4
 
+.section .R_PPC_ADDR32,"ax",@progbits
+.globl .FR_PPC_ADDR32
+.FR_PPC_ADDR32:
+  .long .Lfoox2
+.section .R_PPC_ADDR32_2,"ax",@progbits
+.Lfoox2:
+
+# CHECK: Disassembly of section .R_PPC_ADDR32:
+# CHECK: .FR_PPC_ADDR32:
+# CHECK:    11018:       00 01 10 1c
+
 .section .R_PPC_REL32,"ax",@progbits
 .globl .FR_PPC_REL32
 .FR_PPC_REL32:
   .long .Lfoox3 - .
 .section .R_PPC_REL32_2,"ax",@progbits
 .Lfoox3:
 
 # CHECK: Disassembly of section .R_PPC_REL32:
 # CHECK: .FR_PPC_REL32:
-# CHECK:    11018:       00 00 00 04
+# CHECK:    1101c:       00 00 00 04
 
-.section .R_PPC_ADDR32,"ax",@progbits
-.globl .FR_PPC_ADDR32
-.FR_PPC_ADDR32:
-  .long .Lfoox2
-.section .R_PPC_ADDR32_2,"ax",@progbits
-.Lfoox2:
-
-# CHECK: Disassembly of section .R_PPC_ADDR32:
-# CHECK: .FR_PPC_ADDR32:
-# CHECK:    1101c:       00 01 10 20
+.section .R_PPC_ADDR14,"ax",@progbits
+.globl .FR_PPC_ADDR14
+.FR_PPC_ADDR14:
+  beqa .Lfoox4
+.section .R_PPC_ADDR14_2,"ax",@progbits
+.Lfoox4:
+
+# CHECK: Disassembly of section .R_PPC_ADDR14:
+# CHECK: .FR_PPC_ADDR14:
+# CHECK:    11020:       41 82 10 26     bta 2, 4132
+
+.section .R_PPC_REL14,"ax",@progbits
+.globl .FR_PPC_REL14
+.FR_PPC_REL14:
+  beq .Lfoox5
+.section .R_PPC_REL14_2,"ax",@progbits
+.Lfoox5:
+
+# CHECK: Disassembly of section .R_PPC_REL14:
+# CHECK: .FR_PPC_REL14:
+# CHECK:    11024:       41 82 00 04     bt 2, .+4