[PPC] add intrinsics for vector extract exponent/vector extract significand/vector test data class

[sfertile]

Summary

Adds vector float and vector double intrinsics exposing some instructions that are already implemented:

1. extract exponent --> xvxexpdp/xvxexpsp
2. extract significand --> xvxsigdp/xvxsigsp
3. test data class --> xvtstdcdp/xvtstdcsp

[kbarton]

LGTM

[sfertile]

committed rL286829

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xxleqv :
       PowerPC_VSX_Intrinsic<"xxleqv", [llvm_v4i32_ty],
                             [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xviexpdp :
       PowerPC_VSX_Intrinsic<"xviexpdp",[llvm_v2f64_ty],
                             [llvm_v2i64_ty, llvm_v2i64_ty],[IntrNoMem]>;
 def int_ppc_vsx_xviexpsp :
       PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
                             [llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
+def int_ppc_vsx_xvxexpdp :
+      PowerPC_VSX_Intrinsic<"xvxexpdp", [llvm_v2i64_ty],
+                            [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxexpsp :
+      PowerPC_VSX_Intrinsic<"xvxexpsp", [llvm_v4i32_ty],
+                            [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxsigdp :
+      PowerPC_VSX_Intrinsic<"xvxsigdp", [llvm_v2i64_ty],
+                            [llvm_v2f64_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvxsigsp :
+      PowerPC_VSX_Intrinsic<"xvxsigsp", [llvm_v4i32_ty],
+                            [llvm_v4f32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvtstdcdp :
+      PowerPC_VSX_Intrinsic<"xvtstdcdp", [llvm_v2i64_ty],
+                            [llvm_v2f64_ty, llvm_i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xvtstdcsp :
+      PowerPC_VSX_Intrinsic<"xvtstdcsp", [llvm_v4i32_ty],
+                            [llvm_v4f32_ty,llvm_i32_ty], [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
 
   // Vector Insert Exponent DP/SP
   def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
     IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>;
   def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
     IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;
 
   // Vector Extract Exponent/Significand DP/SP
-  def XVXEXPDP : XX2_XT6_XO5_XB6<60,  0, 475, "xvxexpdp", vsrc, []>;
-  def XVXEXPSP : XX2_XT6_XO5_XB6<60,  8, 475, "xvxexpsp", vsrc, []>;
-  def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", vsrc, []>;
-  def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", vsrc, []>;
+  def XVXEXPDP : XX2_XT6_XO5_XB6<60,  0, 475, "xvxexpdp", vsrc,
+                                 [(set v2i64: $XT,
+                                  (int_ppc_vsx_xvxexpdp v2f64:$XB))]>;
+  def XVXEXPSP : XX2_XT6_XO5_XB6<60,  8, 475, "xvxexpsp", vsrc,
+                                 [(set v4i32: $XT,
+                                  (int_ppc_vsx_xvxexpsp v4f32:$XB))]>;
+  def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", vsrc,
+                                 [(set v2i64: $XT,
+                                  (int_ppc_vsx_xvxsigdp v2f64:$XB))]>;
+  def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", vsrc,
+                                 [(set v4i32: $XT,
+                                  (int_ppc_vsx_xvxsigsp v4f32:$XB))]>;
 
   //===--------------------------------------------------------------------===//
 
   // Test Data Class SP/DP/QP
   let UseVSXReg = 1 in {
   def XSTSTDCSP : XX2_BF3_DCMX7_RS6<60, 298,
                               (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
                               "xststdcsp $BF, $XB, $DCMX", IIC_VecFP, []>;
   def XSTSTDCDP : XX2_BF3_DCMX7_RS6<60, 362,
                               (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB),
                               "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>;
   } // UseVSXReg = 1
   def XSTSTDCQP : X_BF3_DCMX7_RS5  <63, 708,
                               (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB),
                               "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>;
 
   // Vector Test Data Class SP/DP
   let UseVSXReg = 1 in {
   def XVTSTDCSP : XX2_RD6_DCMX7_RS6<60, 13, 5,
                               (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
-                              "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP, []>;
+                              "xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
+                              [(set v4i32: $XT,
+                               (int_ppc_vsx_xvtstdcsp v4f32:$XB, imm:$DCMX))]>;
   def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
                               (outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
-                              "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP, []>;
+                              "xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,
+                              [(set v2i64: $XT,
+                               (int_ppc_vsx_xvtstdcdp v2f64:$XB, imm:$DCMX))]>;
   } // UseVSXReg = 1
 
   //===--------------------------------------------------------------------===//
 
   // Maximum/Minimum Type-C/Type-J DP
   // XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU, so we use vsrc for XT
   def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsrc, vsfrc, vsfrc,
                                  IIC_VecFP, []>;

test/CodeGen/PowerPC/vsx-p9.ll

entry:
   ret <16 x i8> %0
 ; CHECK-LABEL: testVSRV
 ; CHECK: vsrv 2, 2, 3
 ; CHECK: blr
 }
 ; Function Attrs: nounwind readnone
 declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)
 
+; Function Attrs: nounwind readnone
+define <4 x i32> @testXVXEXPSP(<4 x float> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float> %a)
+  ret <4 x i32> %0
+; CHECK-LABEL: testXVXEXPSP
+; CHECK: xvxexpsp 34, 34
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvxexpsp(<4 x float>)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testXVXEXPDP(<2 x double> %a) {
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a)
+  ret <2 x i64> %0
+; CHECK-LABEL: testXVXEXPDP
+; CHECK xvxexpdp 34, 34
+; CHECK blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>)
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @testXVXSIGSP(<4 x float> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a)
+  ret <4 x i32> %0
+; CHECK-LABEL: testXVXSIGSP
+; CHECK xvxsigsp 34, 34
+; CHECK blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testXVXSIGDP(<2 x double> %a) {
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a)
+  ret <2 x i64> %0
+; CHECK-LABEL: testXVXSIGDP
+; CHECK xvxsigdp 34, 34
+; CHECK blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>)
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @testXVTSTDCSP(<4 x float> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 127)
+  ret <4 x i32> %0
+; CHECK-LABEL: testXVTSTDCSP
+; CHECK: xvtstdcsp 34, 34, 127
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.xvtstdcsp(<4 x float> %a, i32 %b)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testXVTSTDCDP(<2 x double> %a) {
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 127)
+  ret <2 x i64> %0
+; CHECK-LABEL: testXVTSTDCDP
+; CHECK: xvtstdcdp 34, 34, 127
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.vsx.xvtstdcdp(<2 x double> %a, i32 %b)
+
 declare void @sink(...)