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Differential D26230

[AddressSanitizer] Add support for (constant-)masked loads and stores.
ClosedPublic

Authored by filcab on Nov 1 2016, 7:36 PM.

Details

Reviewers
kcc
vitalybuka
pgousseau
RKSimon
dvyukov
zaks.anna
Commits
rGec350b71fa69: [AddressSanitizer] Add support for (constant-)masked loads and stores.
rL287047: [AddressSanitizer] Add support for (constant-)masked loads and stores.
Summary

This patch adds support for instrumenting masked loads and stores under
ASan, if they have a constant mask.

isInterestingMemoryAccess now supports returning a mask to be applied to
the loads, and instrumentMop will use it to generate additional checks.

Added tests for v4i32 v8i32, and v4p0i32 (~v4i64) for both loads and
stores (as well as a test to verify we don't add checks to non-constant
masks).

Diff Detail

Repository
rL LLVM

Event Timeline

filcab updated this revision to Diff 76669.Nov 1 2016, 7:36 PM
filcab retitled this revision from to [AddressSanitizer] Add support for (constant-)masked loads and stores..
filcab updated this object.
filcab added reviewers: RKSimon, dvyukov, kcc, zaks.anna.
filcab added a subscriber: llvm-commits.
RKSimon added a reviewer: pgousseau.Nov 5 2016, 10:27 AM
RKSimon added inline comments.Nov 8 2016, 8:38 AM
lib/Transforms/Instrumentation/AddressSanitizer.cpp
505 ↗(On Diff #76669)

Add MaybeMask description to comment.

996 ↗(On Diff #76669)

Add MaybeMask description to comment.

kcc edited edge metadata.Nov 8 2016, 10:05 AM

Could you please also add a test to compiler-rt/test/asan?
(you can do it as a separate Phab patch, if that's more convenient)

lib/Transforms/Instrumentation/AddressSanitizer.cpp
1183 ↗(On Diff #76669)

could you please outline this into its own function, just as you did with doInstrumentAddress?

filcab updated this revision to Diff 77487.Nov 10 2016, 7:56 AM
filcab edited edge metadata.

Update CreateGEP call to add 0 as the first parameter.

filcab planned changes to this revision.Nov 10 2016, 8:06 AM

Forgot to outline part of a function.

filcab updated this revision to Diff 77491.Nov 10 2016, 8:23 AM

Extract instrumentMaskedLoadOrStore()

kcc added a reviewer: vitalybuka.Nov 11 2016, 10:57 AM
RKSimon added inline comments.Nov 11 2016, 11:06 AM
lib/Transforms/Instrumentation/AddressSanitizer.cpp
1055 ↗(On Diff #77491)

Use isa<> instead as we don't use the return value from dyn_cast<> ?

1059 ↗(On Diff #77491)

I don't think we can guarantee ConstantInt type here (UndefValue etc.?)

1152 ↗(On Diff #77491)

I don't think we can guarantee ConstantInt type here (UndefValue etc.?)

filcab updated this revision to Diff 77722.Nov 12 2016, 6:46 AM
filcab marked 6 inline comments as done.

Addressed rksimon's comments:
Basically try to discard undef in a safe way.

Brought back (fixed) test.

vitalybuka accepted this revision.Nov 14 2016, 12:48 PM
vitalybuka edited edge metadata.

LGTM

lib/Transforms/Instrumentation/AddressSanitizer.cpp
1064 ↗(On Diff #77722)

You don't call this with nullptr, so for consistency with other output arguments i'd remove "if (MaybeMask)" check

This revision is now accepted and ready to land.Nov 14 2016, 12:48 PM
filcab marked an inline comment as done.Nov 15 2016, 1:47 PM
filcab added inline comments.
lib/Transforms/Instrumentation/AddressSanitizer.cpp
1064 ↗(On Diff #77722)

It's called in many places outside the function I changed, though.
In the future we will need to refactor this to support scatter/gathers, so I'd like to avoid doing too much now.

996 ↗(On Diff #76669)

Deleted this one, since there's no reason to have those comments on both the prototype and impl.

Closed by commit rL287047: [AddressSanitizer] Add support for (constant-)masked loads and stores. (authored by filcab). · Explain WhyNov 15 2016, 2:47 PM
This revision was automatically updated to reflect the committed changes.
filcab marked an inline comment as done.
filcab mentioned this in rL288162: Compiler-rt part of D26230: Add (constant) masked load/store support.Nov 29 2016, 9:07 AM
filcab mentioned this in rL288173: Revert "Compiler-rt part of D26230: Add (constant) masked load/store support".Nov 29 2016, 10:18 AM
filcab mentioned this in rL288504: Compiler-rt part of D26230: Add (constant) masked load/store support (Try #2).Dec 2 2016, 7:43 AM
filcab mentioned this in rL288507: Revert "Compiler-rt part of D26230: Add (constant) masked load/store support….Dec 2 2016, 8:29 AM

Revision Contents

PathSize
llvm/
trunk/
lib/
Transforms/
Instrumentation/
99 lines
test/
Instrumentation/
AddressSanitizer/
127 lines

Diff 78078

llvm/trunk/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines uint64_t SizeInBytes =
AI.getModule()->getDataLayout().getTypeAllocSize(Ty); AI.getModule()->getDataLayout().getTypeAllocSize(Ty);
return SizeInBytes * ArraySize; return SizeInBytes * ArraySize;
} }
/// Check if we want (and can) handle this alloca. /// Check if we want (and can) handle this alloca.
bool isInterestingAlloca(const AllocaInst &AI); bool isInterestingAlloca(const AllocaInst &AI);
/// If it is an interesting memory access, return the PointerOperand /// If it is an interesting memory access, return the PointerOperand
/// and set IsWrite/Alignment. Otherwise return nullptr. /// and set IsWrite/Alignment. Otherwise return nullptr.
/// MaybeMask is an output parameter for the mask Value, if we're looking at a
/// masked load/store.
Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite, Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
uint64_t *TypeSize, unsigned *Alignment); uint64_t *TypeSize, unsigned *Alignment,
Value **MaybeMask = nullptr);
void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis, Instruction *I, void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis, Instruction *I,
bool UseCalls, const DataLayout &DL); bool UseCalls, const DataLayout &DL);
void instrumentPointerComparisonOrSubtraction(Instruction *I); void instrumentPointerComparisonOrSubtraction(Instruction *I);
void instrumentAddress(Instruction *OrigIns, Instruction *InsertBefore, void instrumentAddress(Instruction *OrigIns, Instruction *InsertBefore,
Value *Addr, uint32_t TypeSize, bool IsWrite, Value *Addr, uint32_t TypeSize, bool IsWrite,
Value *SizeArgument, bool UseCalls, uint32_t Exp); Value *SizeArgument, bool UseCalls, uint32_t Exp);
void instrumentUnusualSizeOrAlignment(Instruction *I, Value *Addr, void instrumentUnusualSizeOrAlignment(Instruction *I, Value *Addr,
uint32_t TypeSize, bool IsWrite, uint32_t TypeSize, bool IsWrite,
▲ Show 20 Lines • Show All 477 Lines • ▼ Show 20 Lines bool IsInteresting =
// inalloca allocas are not treated as static, and we don't want // inalloca allocas are not treated as static, and we don't want
// dynamic alloca instrumentation for them as well. // dynamic alloca instrumentation for them as well.
!AI.isUsedWithInAlloca()); !AI.isUsedWithInAlloca());
ProcessedAllocas[&AI] = IsInteresting; ProcessedAllocas[&AI] = IsInteresting;
return IsInteresting; return IsInteresting;
} }
/// If I is an interesting memory access, return the PointerOperand
/// and set IsWrite/Alignment. Otherwise return nullptr.
Value *AddressSanitizer::isInterestingMemoryAccess(Instruction *I, Value *AddressSanitizer::isInterestingMemoryAccess(Instruction *I,
bool *IsWrite, bool *IsWrite,
uint64_t *TypeSize, uint64_t *TypeSize,
unsigned *Alignment) { unsigned *Alignment,
Value **MaybeMask) {
// Skip memory accesses inserted by another instrumentation. // Skip memory accesses inserted by another instrumentation.
if (I->getMetadata("nosanitize")) return nullptr; if (I->getMetadata("nosanitize")) return nullptr;
// Do not instrument the load fetching the dynamic shadow address. // Do not instrument the load fetching the dynamic shadow address.
if (LocalDynamicShadow == I) if (LocalDynamicShadow == I)
return nullptr; return nullptr;
Value *PtrOperand = nullptr; Value *PtrOperand = nullptr;
Show All 17 Lines if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
*Alignment = 0; *Alignment = 0;
PtrOperand = RMW->getPointerOperand(); PtrOperand = RMW->getPointerOperand();
} else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) { } else if (AtomicCmpXchgInst *XCHG = dyn_cast<AtomicCmpXchgInst>(I)) {
if (!ClInstrumentAtomics) return nullptr; if (!ClInstrumentAtomics) return nullptr;
*IsWrite = true; *IsWrite = true;
*TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType()); *TypeSize = DL.getTypeStoreSizeInBits(XCHG->getCompareOperand()->getType());
*Alignment = 0; *Alignment = 0;
PtrOperand = XCHG->getPointerOperand(); PtrOperand = XCHG->getPointerOperand();
} else if (auto CI = dyn_cast<CallInst>(I)) {
auto *F = dyn_cast<Function>(CI->getCalledValue());
if (F && (F->getName().startswith("llvm.masked.load.") ||
F->getName().startswith("llvm.masked.store."))) {
unsigned OpOffset = 0;
if (F->getName().startswith("llvm.masked.store.")) {
// Masked store has an initial operand for the value.
OpOffset = 1;
*IsWrite = true;
} else {
*IsWrite = false;
}
// Only instrument if the mask is constant for now.
if (isa<ConstantVector>(CI->getOperand(2 + OpOffset))) {
auto BasePtr = CI->getOperand(0 + OpOffset);
auto Ty = cast<PointerType>(BasePtr->getType())->getElementType();
*TypeSize = DL.getTypeStoreSizeInBits(Ty);
if (auto AlignmentConstant =
dyn_cast<ConstantInt>(CI->getOperand(1 + OpOffset)))
*Alignment = (unsigned)AlignmentConstant->getZExtValue();
else
*Alignment = 1; // No alignment guarantees. We probably got Undef
if (MaybeMask)
*MaybeMask = CI->getOperand(2 + OpOffset);
PtrOperand = BasePtr;
}
}
} }
// Do not instrument acesses from different address spaces; we cannot deal // Do not instrument acesses from different address spaces; we cannot deal
// with them. // with them.
if (PtrOperand) { if (PtrOperand) {
Type *PtrTy = cast<PointerType>(PtrOperand->getType()->getScalarType()); Type *PtrTy = cast<PointerType>(PtrOperand->getType()->getScalarType());
if (PtrTy->getPointerAddressSpace() != 0) if (PtrTy->getPointerAddressSpace() != 0)
return nullptr; return nullptr;
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Linesvoid AddressSanitizer::instrumentPointerComparisonOrSubtraction(
Value *Param[2] = {I->getOperand(0), I->getOperand(1)}; Value *Param[2] = {I->getOperand(0), I->getOperand(1)};
for (Value *&i : Param) { for (Value *&i : Param) {
if (i->getType()->isPointerTy()) if (i->getType()->isPointerTy())
i = IRB.CreatePointerCast(i, IntptrTy); i = IRB.CreatePointerCast(i, IntptrTy);
} }
IRB.CreateCall(F, Param); IRB.CreateCall(F, Param);
} }
static void doInstrumentAddress(AddressSanitizer *Pass, Instruction *I,
Value *Addr, unsigned Alignment,
unsigned Granularity, uint32_t TypeSize,
bool IsWrite, Value *SizeArgument,
bool UseCalls, uint32_t Exp) {
// Instrument a 1-, 2-, 4-, 8-, or 16- byte access with one check
// if the data is properly aligned.
if ((TypeSize == 8 || TypeSize == 16 || TypeSize == 32 || TypeSize == 64 ||
TypeSize == 128) &&
(Alignment >= Granularity || Alignment == 0 || Alignment >= TypeSize / 8))
return Pass->instrumentAddress(I, I, Addr, TypeSize, IsWrite, nullptr,
UseCalls, Exp);
Pass->instrumentUnusualSizeOrAlignment(I, Addr, TypeSize, IsWrite, nullptr,
UseCalls, Exp);
}
static void instrumentMaskedLoadOrStore(AddressSanitizer *Pass,
const DataLayout &DL, Type *IntptrTy,
ConstantVector *Mask, Instruction *I,
Value *Addr, unsigned Alignment,
unsigned Granularity, uint32_t TypeSize,
bool IsWrite, Value *SizeArgument,
bool UseCalls, uint32_t Exp) {
auto *VTy = cast<PointerType>(Addr->getType())->getElementType();
uint64_t ElemTypeSize = DL.getTypeStoreSizeInBits(VTy->getScalarType());
unsigned Num = VTy->getVectorNumElements();
auto Zero = ConstantInt::get(IntptrTy, 0);
for (unsigned Idx = 0; Idx < Num; ++Idx) {
// dyn_cast as we might get UndefValue
auto Masked = dyn_cast<ConstantInt>(Mask->getOperand(Idx));
if (Masked && Masked->isAllOnesValue()) {
IRBuilder<> IRB(I);
auto InstrumentedAddress =
IRB.CreateGEP(Addr, {Zero, ConstantInt::get(IntptrTy, Idx)});
doInstrumentAddress(Pass, I, InstrumentedAddress, Alignment, Granularity,
ElemTypeSize, IsWrite, SizeArgument, UseCalls, Exp);
}
}
}
void AddressSanitizer::instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis, void AddressSanitizer::instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
Instruction *I, bool UseCalls, Instruction *I, bool UseCalls,
const DataLayout &DL) { const DataLayout &DL) {
bool IsWrite = false; bool IsWrite = false;
unsigned Alignment = 0; unsigned Alignment = 0;
uint64_t TypeSize = 0; uint64_t TypeSize = 0;
Value *Addr = isInterestingMemoryAccess(I, &IsWrite, &TypeSize, &Alignment); Value *MaybeMask = nullptr;
Value *Addr =
isInterestingMemoryAccess(I, &IsWrite, &TypeSize, &Alignment, &MaybeMask);
assert(Addr); assert(Addr);
// Optimization experiments. // Optimization experiments.
// The experiments can be used to evaluate potential optimizations that remove // The experiments can be used to evaluate potential optimizations that remove
// instrumentation (assess false negatives). Instead of completely removing // instrumentation (assess false negatives). Instead of completely removing
// some instrumentation, you set Exp to a non-zero value (mask of optimization // some instrumentation, you set Exp to a non-zero value (mask of optimization
// experiments that want to remove instrumentation of this instruction). // experiments that want to remove instrumentation of this instruction).
// If Exp is non-zero, this pass will emit special calls into runtime // If Exp is non-zero, this pass will emit special calls into runtime
Show All 25 Linesvoid AddressSanitizer::instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
} }
if (IsWrite) if (IsWrite)
NumInstrumentedWrites++; NumInstrumentedWrites++;
else else
NumInstrumentedReads++; NumInstrumentedReads++;
unsigned Granularity = 1 << Mapping.Scale; unsigned Granularity = 1 << Mapping.Scale;
// Instrument a 1-, 2-, 4-, 8-, or 16- byte access with one check if (MaybeMask) {
// if the data is properly aligned. auto Mask = cast<ConstantVector>(MaybeMask);
if ((TypeSize == 8 || TypeSize == 16 || TypeSize == 32 || TypeSize == 64 || instrumentMaskedLoadOrStore(this, DL, IntptrTy, Mask, I, Addr, Alignment,
TypeSize == 128) && Granularity, TypeSize, IsWrite, nullptr,
(Alignment >= Granularity || Alignment == 0 || Alignment >= TypeSize / 8))
return instrumentAddress(I, I, Addr, TypeSize, IsWrite, nullptr, UseCalls,
Exp);
instrumentUnusualSizeOrAlignment(I, Addr, TypeSize, IsWrite, nullptr,
UseCalls, Exp); UseCalls, Exp);
} else {
doInstrumentAddress(this, I, Addr, Alignment, Granularity, TypeSize,
IsWrite, nullptr, UseCalls, Exp);
}
} }
Instruction *AddressSanitizer::generateCrashCode(Instruction *InsertBefore, Instruction *AddressSanitizer::generateCrashCode(Instruction *InsertBefore,
Value *Addr, bool IsWrite, Value *Addr, bool IsWrite,
size_t AccessSizeIndex, size_t AccessSizeIndex,
Value *SizeArgument, Value *SizeArgument,
uint32_t Exp) { uint32_t Exp) {
IRBuilder<> IRB(InsertBefore); IRBuilder<> IRB(InsertBefore);
▲ Show 20 Lines • Show All 1,436 Lines • Show Last 20 Lines

llvm/trunk/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll

; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s
; Support ASan instrumentation for constant-mask llvm.masked.{load,store}
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@v4f32 = global <4 x float>* zeroinitializer, align 8
@v8i32 = global <8 x i32>* zeroinitializer, align 8
@v4i64 = global <4 x i32*>* zeroinitializer, align 8
;;;;;;;;;;;;;;;; STORE
declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) argmemonly nounwind
declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly nounwind
declare void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*>, <4 x i32*>*, i32, <4 x i1>) argmemonly nounwind
define void @store.v4f32.1110(<4 x float> %arg) sanitize_address {
; CHECK-LABEL: @store.v4f32.1110
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP0]])
; CHECK: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
; CHECK: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP1]])
; CHECK: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
; CHECK: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP2]])
; CHECK: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 false>)
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 false>)
ret void
}
define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address {
; CHECK-LABEL: @store.v8i32.10010110
%p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP0]])
; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3
; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP3]])
; CHECK: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5
; CHECK: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP5]])
; CHECK: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6
; CHECK: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64
; CHECK: call void @__asan_store4(i64 [[PGEP6]])
; CHECK: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>)
tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>)
ret void
}
define void @store.v4i64.0001(<4 x i32*> %arg) sanitize_address {
; CHECK-LABEL: @store.v4i64.0001
%p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
; CHECK: call void @__asan_store8(i64 [[PGEP3]])
; CHECK: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)
tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>)
ret void
}
define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address {
; CHECK-LABEL: @store.v4f32.variable
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
; CHECK-NOT: call void @__asan_store
tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
ret void
}
;;;;;;;;;;;;;;;; LOAD
declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) argmemonly nounwind
declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly nounwind
declare <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>*, i32, <4 x i1>, <4 x i32*>) argmemonly nounwind
define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address {
; CHECK-LABEL: @load.v8i32.11100001
%p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
; CHECK: call void @__asan_load4(i64 [[PGEP0]])
; CHECK: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
; CHECK: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
; CHECK: call void @__asan_load4(i64 [[PGEP1]])
; CHECK: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2
; CHECK: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64
; CHECK: call void @__asan_load4(i64 [[PGEP2]])
; CHECK: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7
; CHECK: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64
; CHECK: call void @__asan_load4(i64 [[PGEP7]])
; CHECK: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> %arg)
%res = tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> %arg)
ret <8 x i32> %res
}
define <4 x float> @load.v4f32.1001(<4 x float> %arg) sanitize_address {
; CHECK-LABEL: @load.v4f32.1001
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
; CHECK: call void @__asan_load4(i64 [[PGEP0]])
; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
; CHECK: call void @__asan_load4(i64 [[PGEP3]])
; CHECK: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %arg)
%res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %arg)
ret <4 x float> %res
}
define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) sanitize_address {
; CHECK-LABEL: @load.v4i64.0001
%p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
; CHECK: call void @__asan_load8(i64 [[PGEP3]])
; CHECK: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32*> %arg)
%res = tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32*> %arg)
ret <4 x i32*> %res
}
define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address {
; CHECK-LABEL: @load.v4f32.variable
%p = load <4 x float>*, <4 x float>** @v4f32, align 8
; CHECK-NOT: call void @__asan_load
%res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
ret <4 x float> %res
}