[PPC] add absolute difference altivec instructions and matching intrinsics

[sfertile]

Summary

adds vabsd* instruction for unsigned byte/halfword/word, and matching intrinsics to expose them.

[amehsan]

lib/Target/PowerPC/PPCInstrAltivec.td

1409–1418

IIRC, when I was doing the patches that I sent you, there was a generic absolute value intrinsic, that I could use. That is better than the PPC intrinsics, because it is more likely that optimizations understand it. Could you use the generic one here?

test/CodeGen/PowerPC/vec_absd.ll

2–3

you should not need -mattr=+altivec when you have -mcpu=pwr9. Does something go wrong when you remove that?

[nemanjai]

include/llvm/IR/IntrinsicsPowerPC.td

697

Been a while since I looked at this, but do the PowerPC_Vec_BBB_Intrinsic and it's halfword and word equivalent not have the same definition as this (and therefore allow you to more concisely define these)? Basically what I'm getting at is using the most specialized class that has the right form.

lib/Target/PowerPC/PPCInstrAltivec.td

454

Please don't add blank lines arbitrarily.

1409–1418

I don't think there is a generic one for integer types, but I might be wrong. I think there's only llvm.fabs.

1411

This is a very minor nit, but the very first characters on the continuation line should line up inside the angle bracket. So the double quote character should line up with the 1 character above.

test/CodeGen/PowerPC/vec_absd.ll

2–3

I agree. If this test case behaves differently with and without -mattr=+altivec, we need to look into why.

21

Please add the register operands here. The ABI locks all 3.
vabsdub 2, 2, 3
The same goes for the other tests as well.

test/MC/Disassembler/PowerPC/ppc64-encoding-p9vector.txt

1 ↗

(On Diff #76183)

Please don't add this file or the one below. The assembler and disassembler do not care about predicates. If they understand an encoding, they will emit what it is. Just add these to the existing test cases.

[sfertile]

Updated based on the review comments:

1. fixed extra blank line/spacing issues
2. switched the intrinsics to use the most derived type that fits the format
3. removed the new test files and put the checks into the existing files
4. removed the unneeded altivec feature to the codegen test

[sfertile]

include/llvm/IR/IntrinsicsPowerPC.td

697

Your right, I've updated them to use the specialized formats.

lib/Target/PowerPC/PPCInstrAltivec.td

1409–1418

I checked, there isn't a generic version of absolute difference to use.

[kbarton]

LGTM

[nemanjai]

Committed revision 285627.
Sean, please close this review if there are no buildbot failures.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_crypto_vpmsumb :
             PowerPC_Vec_BBB_Intrinsic<"crypto_vpmsumb">;
 def int_ppc_altivec_crypto_vpmsumh :
             PowerPC_Vec_HHH_Intrinsic<"crypto_vpmsumh">;
 def int_ppc_altivec_crypto_vpmsumw :
             PowerPC_Vec_WWW_Intrinsic<"crypto_vpmsumw">;
 def int_ppc_altivec_crypto_vpmsumd :
             PowerPC_Vec_DDD_Intrinsic<"crypto_vpmsumd">;
 
+// Absolute Difference intrinsics
+def int_ppc_altivec_vabsdub : PowerPC_Vec_BBB_Intrinsic<"vabsdub">;
+def int_ppc_altivec_vabsduh : PowerPC_Vec_HHH_Intrinsic<"vabsduh">;
+def int_ppc_altivec_vabsduw : PowerPC_Vec_WWW_Intrinsic<"vabsduw">;
+
 //===----------------------------------------------------------------------===//
 // PowerPC VSX Intrinsic Definitions.
 
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
 
 // Vector load.
 def int_ppc_vsx_lxvw4x :
       Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;

lib/Target/PowerPC/PPCInstrAltivec.td

 def STVX  : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
                    "stvx $rS, $dst", IIC_LdStStore,
                    [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
 def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
                    "stvxl $rS, $dst", IIC_LdStStore,
                    [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
 }
 
 let PPC970_Unit = 5 in {  // VALU Operations.
 // VA-Form instructions.  3-input AltiVec ops.
 let isCommutable = 1 in {
 def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
                        "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
                        [(set v4f32:$vD,
                         (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
 
 // FIXME: The fma+fneg pattern won't match because fneg is not legal.

 // Decimal Shift/Unsigned-Shift/Shift-and-Round
 def BCDSo :  VX_VT5_VA5_VB5_PS1_XO9_o<193, "bcds." , []>;
 def BCDUSo : VX_VT5_VA5_VB5_XO9_o    <129, "bcdus.", []>;
 def BCDSRo : VX_VT5_VA5_VB5_PS1_XO9_o<449, "bcdsr.", []>;
 
 // Decimal (Unsigned) Truncate
 def BCDTRUNCo :  VX_VT5_VA5_VB5_PS1_XO9_o<257, "bcdtrunc." , []>;
 def BCDUTRUNCo : VX_VT5_VA5_VB5_XO9_o    <321, "bcdutrunc.", []>;
+
+// Absolute Difference
+def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                       "vabsdub $vD, $vA, $vB", IIC_VecGeneral,
+                       [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>;
+def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                       "vabsduh $vD, $vA, $vB", IIC_VecGeneral,
+                       [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>;
+def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+                       "vabsduw $vD, $vA, $vB", IIC_VecGeneral,
+                       [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>;
 } // end HasP9Altivec

test/CodeGen/PowerPC/vec_absd.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu  < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
+
+; Check the vabsd* instructions that were added in PowerISA V3.0
+
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8>, <16 x i8>)
+
+; Function Attrs: nounwind readnone
+declare <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16>, <8 x i16>)
+
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32>, <4 x i32>)
+
+define <16 x i8> @test_byte(<16 x i8> %a, <16 x i8> %b) {
+entry:
+  %res = tail call <16 x i8> @llvm.ppc.altivec.vabsdub(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %res
+; CHECK-LABEL: @test_byte
+; CHECK: vabsdub 2, 2, 3
+; CHECK blr
+}
+
+define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
+entry:
+  %res = tail call <8 x i16> @llvm.ppc.altivec.vabsduh(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %res
+; CHECK-LABEL: @test_half
+; CHECK: vabsduh 2, 2, 3
+; CHECK blr
+}
+
+define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %res = tail call <4 x i32> @llvm.ppc.altivec.vabsduw(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %res
+; CHECK-LABEL: @test_word
+; CHECK: vabsduw 2, 2, 3
+; CHECK: blr
+}

test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt

 0x10 0x43 0x00 0x01
 
 # CHECK: vmul10euq 2, 3, 4
 0x10 0x43 0x22 0x41
 
 # CHECK: vmul10ecuq 2, 3, 4
 0x10 0x43 0x20 0x41
 
+#CHECK: vabsdub 2, 3, 4
+0x10 0x43 0x24 0x03
+
+#CHECK vabsduh 2, 3, 4
+0x10 0x43 0x24 0x43
+
+#CHECK vabsduw 2, 3, 4
+0x10 0x43 0x24 0x83
+
 # CHECK: bcdcfn. 27, 31, 1
 0x13 0x67 0xff 0x81
 
 # CHECK: bcdcfz. 27, 31, 1
 0x13 0x66 0xff 0x81
 
 # CHECK: bcdctn. 27, 31
 0x13 0x65 0xfd 0x81

test/MC/PowerPC/ppc64-encoding-vmx.s

# CHECK-LE: vmul10cuq 2, 3                  # encoding: [0x01,0x00,0x43,0x10]
             vmul10cuq 2, 3
 # CHECK-BE: vmul10euq 2, 3, 4               # encoding: [0x10,0x43,0x22,0x41]
 # CHECK-LE: vmul10euq 2, 3, 4               # encoding: [0x41,0x22,0x43,0x10]
             vmul10euq 2, 3, 4
 # CHECK-BE: vmul10ecuq 2, 3, 4              # encoding: [0x10,0x43,0x20,0x41]
 # CHECK-LE: vmul10ecuq 2, 3, 4              # encoding: [0x41,0x20,0x43,0x10]
             vmul10ecuq 2, 3, 4
 
+# Vector Absolute Difference
+# CHECK-BE: vabsdub 2, 3, 4                # encoding: [0x10,0x43,0x24,0x03]
+# CHECK-LE: vabsdub 2, 3, 4                # encoding: [0x03,0x24,0x43,0x10]
+            vabsdub 2, 3, 4
+
+# CHECK-BE: vabsduh 2, 3, 4                # encoding: [0x10,0x43,0x24,0x43]
+# CHECK-LE: vabsduh 2, 3, 4                # encoding: [0x43,0x24,0x43,0x10]
+            vabsduh 2, 3, 4
+
+# CHECK-BE: vabsduw 2, 3, 4                # encoding: [0x10,0x43,0x24,0x83]
+# CHECK-LE: vabsduw 2, 3, 4                # encoding: [0x83,0x24,0x43,0x10]
+            vabsduw 2, 3, 4
+
 # Decimal Convert From/to National/Zoned/Signed-QWord
 # CHECK-BE: bcdcfn. 27, 31, 1                  # encoding: [0x13,0x67,0xff,0x81]
 # CHECK-LE: bcdcfn. 27, 31, 1                  # encoding: [0x81,0xff,0x67,0x13]
             bcdcfn. 27, 31, 1
 # CHECK-BE: bcdcfz. 27, 31, 1                  # encoding: [0x13,0x66,0xff,0x81]
 # CHECK-LE: bcdcfz. 27, 31, 1                  # encoding: [0x81,0xff,0x66,0x13]
             bcdcfz. 27, 31, 1
 # CHECK-BE: bcdctn. 27, 31                     # encoding: [0x13,0x65,0xfd,0x81]