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[ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON
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Authored by labrinea on Oct 5 2016, 7:45 AM.

Details

Summary

The instructions VLDM/VSTM can only access word-aligned memory locations and produce alignment fault if the condition is not met.

The compiler currently generates VLDM/VSTM for v2f64 load/store regardless the alignment of the memory access. Instead, if a v2f64 load/store is not word-aligned, the compiler should generate VLD1/VST1. For each non double-word-aligned VLD1/VST1, a VREV instruction should be generated when targeting Big Endian.

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Event Timeline

labrinea updated this revision to Diff 73646.Oct 5 2016, 7:45 AM
labrinea retitled this revision from to [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON.
labrinea updated this object.
labrinea added reviewers: olista01, t.p.northover.
labrinea added subscribers: llvm-commits, jmolloy.
olista01 added inline comments.Oct 7 2016, 5:20 AM
test/CodeGen/ARM/load_store_multiple.ll
1

The code change is for v2f64, but this test doesn't contain any <2 x double>s. Could you add a few tests for them?

labrinea updated this revision to Diff 74122.Oct 10 2016, 6:42 AM
labrinea updated this object.

Added a new codegen test for <2 x double> load/store as suggested.

olista01 accepted this revision.Oct 10 2016, 8:39 AM
olista01 edited edge metadata.

LGTM

This revision is now accepted and ready to land.Oct 10 2016, 8:39 AM
labrinea closed this revision.Oct 10 2016, 9:37 AM

Committed as r283763.