[LLDB][MIPS] fix Floating point register read/write for big endian

[nitesh.jain]

Summary

This patch add fix for reading and writing floating point register based on SR.FR bit.

[labath]

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

1183 ↗

(On Diff #71487)

Why do we need to do this remapping? Couldn't we structure the register infos in a way that reg_info->byte_offset is exactly the offset that ptrace expects?

Or are you saying that ptrace does not accept register offsets, but some random register numbers instead? (I cannot tell, as the comment above is confusing.)

1222 ↗

(On Diff #71487)

This seems like a pretty complicated way to write assert(!reg_info->invalidate_regs);

[nitesh.jain]

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

1183 ↗

(On Diff #71487)

In case of MIPS, ptrace request PTRACE_PEEKUSER/PTRACE_POKEUSER accept register number as an offset. We used reg_info->byte_offset to find register value in the struct GPR_linux_mips. The struct GPR_linux_mips is same for 32 and 64 bit since ptrace always return 64 bit value irrespective of Arch (32 and 64) . Hence we can't modify reg_info->byte_offset to match exactly the offset that ptrace expects.

[nitesh.jain]

Updated diff as per suggestion.

[labath]

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

1161 ↗

(On Diff #71487)

Ok I think I understand this now.
s/has/as/

1183 ↗

(On Diff #71487)

Ok, I see what you mean. byte_offset is out in that case.
However, I am wondering if we couldn't tweak one of the existing numbering schemes to fit that one. For example, the LLDB numbering scheme is completely arbitrary, and under our control, so what if we just reordered that a bit to match what ptrace expects? I feel that we have enough numbering schemes already, so it should be possible to find one that works without introducing a new one.

This is not that bad, as the "scheme" is confined to the single file, but still you have to admit that this function looks very odd: sometimes you return a register index, sometimes a register offset and sometimes a completely made up number...

1207 ↗

(On Diff #71487)

Isn't it possible to match the "config5" register by one of the numbering schemes, instead of by name?

[nitesh.jain]

source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

1183 ↗

(On Diff #71505)

Changing LLDB numbering scheme is not feasible since there are lots of changes both at host and target site. Should I add new numbering scheme ?

[labath]

Ok, lets leave that as-is then.. the issue seem s pretty contained for now.

[clayborg]

So it seems like this can be fixed by doing a few things:
1 - just set the RegisterInfo.offset to the actual offset in the buffer and don't use the offset as the ptrace key used to grab the register
2 - modify the RegisterInfo.kinds[eRegisterKindProcessPlugin] to be the offset to you to use for ptrace

There should be no need what so ever to do manual bit twiddling with src and dst.

[nitesh.jain]

Updated patch as per suggestion.

[nitesh.jain]

In D24603#548902, @clayborg wrote:

So it seems like this can be fixed by doing a few things:
1 - just set the RegisterInfo.offset to the actual offset in the buffer and don't use the offset as the ptrace key used to grab the register
2 - modify the RegisterInfo.kinds[eRegisterKindProcessPlugin] to be the offset to you to use for ptrace

There should be no need what so ever to do manual bit twiddling with src and dst.

The floating point register size can be dynamically changes . Hence following cases are possible when we read registers from ptrace in FPR_linux_mips buffer (In case of MIPS, ptrace always return value in 64 bit container irrespective of Arch).

1. Floating point register size is 32 (SR.FR = 0).
   
   a) In case of big endian system, the FPR_linux_mips.f0 will contains two floating point registers . The $f0 register will be store in upper 32 bit and $f1 register in lower 32 bit of FPR_linux_mips.f0. The FPR_linux_mips.f1 will contain don't care value and similarly for all other registers. Thus each even buffer will contain valid value and represent two registers.
   
   b) In case of liitle endian , the $f0 will be store in lower 32 bit and $f1 in upper 32bit of FPR_linux_mips.f0. The FPR_linux_mips.f1 will contain don't care value and similarly for all other registers.

2. Floating point register size is 64 (SR.FR = 1). In these case all buffer will have valid value.

Hence we need bit twiddling with src and dst (in case of SR.FR = 0) so that each buffer will represent value for single register.

[clayborg]

Please comment why you are manually bit twiddling due to the size of the register that can change. We don't want anyone else copying this kind of code. Another solution would be to update the offset of the register when you change the byte size so none of this would need to be done. We are already updating the byte size of the register in the RegisterInfo, so why not do the same for the offset. You could store the original offset in the RegisterInfo.kinds[eRegisterKindProcessPlugin] as this field is only for the process plug-in's use.

[nitesh.jain]

These diff remove manually bit twiddling due to the size of the floating point register that can change. We use register offset to get floating point register data based on endianess and it's size. We have not remove bit twiddling for MSA register since it's need to be tested( require support in ptrace).

Thanks

[nitesh.jain]

Hi Greg,

The diff is update as per suggestion so should I commit this ?

Thanks

[clayborg]

Commit anytime.

[nitesh.jain]

In D24603#566575, @clayborg wrote:

Commit anytime.

Thanks

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.h

public:
   Error ReadAllRegisterValues(lldb::DataBufferSP &data_sp) override;
 
   Error WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override;
 
   Error ReadCP1();
 
   Error WriteCP1();
 
+  uint8_t *ReturnFPOffset(uint8_t reg_index, uint32_t byte_offset);
+
   Error IsWatchpointHit(uint32_t wp_index, bool &is_hit) override;
 
   Error GetWatchpointHitIndex(uint32_t &wp_index,
                               lldb::addr_t trap_addr) override;
 
   Error IsWatchpointVacant(uint32_t wp_index, bool &is_vacant) override;
 
   bool ClearHardwareWatchpoint(uint32_t wp_index) override;
 
   Error ClearAllHardwareWatchpoints() override;
 
   Error SetHardwareWatchpointWithIndex(lldb::addr_t addr, size_t size,
                                        uint32_t watch_flags, uint32_t wp_index);
 
   uint32_t SetHardwareWatchpoint(lldb::addr_t addr, size_t size,
                                  uint32_t watch_flags) override;
 
   lldb::addr_t GetWatchpointAddress(uint32_t wp_index) override;
 
   uint32_t NumSupportedHardwareWatchpoints() override;
 
   static bool IsMSAAvailable();
 
 protected:
-  Error DoReadRegisterValue(uint32_t offset, const char *reg_name,
-                            uint32_t size, RegisterValue &value) override;
+  Error Read_SR_Config(uint32_t offset, const char *reg_name, uint32_t size,
+                       RegisterValue &value);
+
+  Error ReadRegisterRaw(uint32_t reg_index, RegisterValue &value) override;
 
-  Error DoWriteRegisterValue(uint32_t offset, const char *reg_name,
-                             const RegisterValue &value) override;
+  Error WriteRegisterRaw(uint32_t reg_index,
 
   Error DoReadWatchPointRegisterValue(lldb::tid_t tid, void *watch_readback);
 
   Error DoWriteWatchPointRegisterValue(lldb::tid_t tid, void *watch_readback);
 
   bool IsFR0();
 
   bool IsFRE();

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_mips64.cpp

 #include "Plugins/Process/Utility/RegisterContextLinux_mips64.h"
 #include "lldb/Core/DataBufferHeap.h"
 #include "lldb/Core/EmulateInstruction.h"
 #include "lldb/Core/Error.h"
 #include "lldb/Core/Log.h"
 #include "lldb/Core/RegisterValue.h"
 #include "lldb/Host/Host.h"
 #include "lldb/Host/HostInfo.h"
+#include "lldb/Utility/LLDBAssert.h"
 #include "lldb/lldb-enumerations.h"
 #include "lldb/lldb-private-enumerations.h"
 #define NT_MIPS_MSA 0x600
 #define CONFIG5_FRE (1 << 8)
 #define SR_FR (1 << 26)
 #define NUM_REGISTERS 32
 
 #include <asm/ptrace.h>
NativeRegisterContextLinux_mips64::ReadRegister(const RegisterInfo *reg_info,
   Error error;
 
   if (!reg_info) {
     error.SetErrorString("reg_info NULL");
     return error;
   }
 
   const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB];
+  uint8_t byte_size = reg_info->byte_size;
   if (reg == LLDB_INVALID_REGNUM) {
     // This is likely an internal register for lldb use only and should not be
     // directly queried.
     error.SetErrorStringWithFormat("register \"%s\" is an internal-only lldb "
                                    "register, cannot read directly",
                                    reg_info->name);
     return error;
   }
 
   if (IsMSA(reg) && !IsMSAAvailable()) {
     error.SetErrorString("MSA not available on this processor");
     return error;
   }
 
   if (IsMSA(reg) || IsFPR(reg)) {
-    uint8_t *src;
+    uint8_t *src = nullptr;
+    lldbassert(reg_info->byte_offset < sizeof(UserArea));
 
     error = ReadCP1();
 
     if (!error.Success()) {
       error.SetErrorString("failed to read co-processor 1 register");
       return error;
     }
 
     if (IsFPR(reg)) {
-      assert(reg_info->byte_offset < sizeof(UserArea));
-      src = (uint8_t *)&m_fpr + reg_info->byte_offset - (sizeof(m_gpr));
-    } else {
-      assert(reg_info->byte_offset < sizeof(UserArea));
+      if (IsFR0() && (byte_size != 4)) {
+        byte_size = 4;
+        uint8_t ptrace_index;
+        ptrace_index = reg_info->kinds[lldb::eRegisterKindProcessPlugin];
+        src = ReturnFPOffset(ptrace_index, reg_info->byte_offset);
+      } else
+        src = (uint8_t *)&m_fpr + reg_info->byte_offset - sizeof(m_gpr);
+    } else
       src = (uint8_t *)&m_msa + reg_info->byte_offset -
             (sizeof(m_gpr) + sizeof(m_fpr));
-    }
-    switch (reg_info->byte_size) {
+    switch (byte_size) {
     case 4:
       reg_value.SetUInt32(*(uint32_t *)src);
       break;
     case 8:
       reg_value.SetUInt64(*(uint64_t *)src);
       break;
     case 16:
       reg_value.SetBytes((const void *)src, 16, GetByteOrder());
return Error("no lldb regnum for %s", reg_info && reg_info->name
                                               : "<unknown register>");
 
   if (IsMSA(reg_index) && !IsMSAAvailable()) {
     error.SetErrorString("MSA not available on this processor");
     return error;
   }
 
   if (IsFPR(reg_index) || IsMSA(reg_index)) {
-    uint8_t *dst;
-    uint64_t *src;
+    uint8_t *dst = nullptr;
+    uint64_t *src = nullptr;
+    uint8_t byte_size = reg_info->byte_size;
+    lldbassert(reg_info->byte_offset < sizeof(UserArea));
 
     // Initialise the FP and MSA buffers by reading all co-processor 1 registers
     ReadCP1();
 
     if (IsFPR(reg_index)) {
-      assert(reg_info->byte_offset < sizeof(UserArea));
-      dst = (uint8_t *)&m_fpr + reg_info->byte_offset - (sizeof(m_gpr));
-    } else {
-      assert(reg_info->byte_offset < sizeof(UserArea));
+      if (IsFR0() && (byte_size != 4)) {
+        byte_size = 4;
+        uint8_t ptrace_index;
+        ptrace_index = reg_info->kinds[lldb::eRegisterKindProcessPlugin];
+        dst = ReturnFPOffset(ptrace_index, reg_info->byte_offset);
+      } else
+        dst = (uint8_t *)&m_fpr + reg_info->byte_offset - sizeof(m_gpr);
+    } else
       dst = (uint8_t *)&m_msa + reg_info->byte_offset -
             (sizeof(m_gpr) + sizeof(m_fpr));
-    }
-    switch (reg_info->byte_size) {
+    switch (byte_size) {
     case 4:
       *(uint32_t *)dst = reg_value.GetAsUInt32();
       break;
     case 8:
       *(uint64_t *)dst = reg_value.GetAsUInt64();
       break;
     case 16:
       src = (uint64_t *)reg_value.GetBytes();
Error NativeRegisterContextLinux_mips64::WriteAllRegisterValues(
   }
 
   return error;
 }
 
 Error NativeRegisterContextLinux_mips64::ReadCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   if (IsMSAAvailable()) {
     error = NativeRegisterContextLinux::ReadRegisterSet(
         &m_iovec, sizeof(MSA_linux_mips), NT_MIPS_MSA);
     src = (uint8_t *)&m_msa + (IsBigEndian * 8);
     dst = (uint8_t *)&m_fpr;
     for (int i = 0; i < NUM_REGISTERS; i++) {
       // Copy fp values from msa buffer fetched via ptrace
       *(uint64_t *)dst = *(uint64_t *)src;
       src = src + 16;
       dst = dst + 8;
     }
     m_fpr.fir = m_msa.fir;
     m_fpr.fcsr = m_msa.fcsr;
     m_fpr.config5 = m_msa.config5;
   } else {
     error = NativeRegisterContextLinux::ReadFPR();
   }
-
-  // TODO: Add support for FRE
-  if (IsFR0()) {
-    src = (uint8_t *)&m_fpr + 4 + (IsBigEndian * 4);
-    dst = (uint8_t *)&m_fpr + 8 + (IsBigEndian * 4);
-    for (int i = 0; i < (NUM_REGISTERS / 2); i++) {
-      // copy odd single from top of neighbouring even double
-      *(uint32_t *)dst = *(uint32_t *)src;
-      src = src + 16;
-      dst = dst + 16;
-    }
-  }
+  return error;
 
-  return error;
+uint8_t *
+NativeRegisterContextLinux_mips64::ReturnFPOffset(uint8_t reg_index,
+                                                  uint32_t byte_offset) {
+
+  uint8_t *fp_buffer_ptr = nullptr;
+  lldb::ByteOrder byte_order = GetByteOrder();
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
+  if (reg_index % 2) {
+    uint8_t offset_diff = (IsBigEndian) ? 8 : 4;
+    fp_buffer_ptr =
+        (uint8_t *)&m_fpr + byte_offset - offset_diff - sizeof(m_gpr);
+  } else {
+    fp_buffer_ptr =
+        (uint8_t *)&m_fpr + byte_offset + 4 * (IsBigEndian) - sizeof(m_gpr);
+  }
+  return fp_buffer_ptr;
 }
 
 Error NativeRegisterContextLinux_mips64::WriteCP1() {
   Error error;
 
-  uint8_t *src, *dst;
+  uint8_t *src = nullptr;
+  uint8_t *dst = nullptr;
 
   lldb::ByteOrder byte_order = GetByteOrder();
 
-  uint32_t IsBigEndian = (byte_order == lldb::eByteOrderBig);
-
-  // TODO: Add support for FRE
-  if (IsFR0()) {
-    src = (uint8_t *)&m_fpr + 8 + (IsBigEndian * 4);
-    dst = (uint8_t *)&m_fpr + 4 + (IsBigEndian * 4);
-    for (int i = 0; i < (NUM_REGISTERS / 2); i++) {
-      // copy odd single to top of neighbouring even double
-      *(uint32_t *)dst = *(uint32_t *)src;
-      src = src + 16;
-      dst = dst + 16;
-    }
-  }
+  bool IsBigEndian = (byte_order == lldb::eByteOrderBig);
 
   if (IsMSAAvailable()) {
     dst = (uint8_t *)&m_msa + (IsBigEndian * 8);
     src = (uint8_t *)&m_fpr;
     for (int i = 0; i < NUM_REGISTERS; i++) {
       // Copy fp values to msa buffer for ptrace
       *(uint64_t *)dst = *(uint64_t *)src;
       dst = dst + 16;
default:
         log->Printf("NativeRegisterContextLinux_mips64::%s Error: Unrecognized "
                     "watch register style",
                     __FUNCTION__);
     }
     return 0;
   }
   return num_valid;
 }
-Error NativeRegisterContextLinux_mips64::DoReadRegisterValue(
-    uint32_t offset, const char *reg_name, uint32_t size,
+
+Error NativeRegisterContextLinux_mips64::ReadRegisterRaw(uint32_t reg_index,
                                                          RegisterValue &value) {
-  GPR_linux_mips regs;
-  ::memset(&regs, 0, sizeof(GPR_linux_mips));
+  const RegisterInfo *const reg_info = GetRegisterInfoAtIndex(reg_index);
 
-  // Clear all bits in RegisterValue before writing actual value read from
-  // ptrace to avoid garbage value in 32-bit MSB
-  value.SetBytes((void *)(((unsigned char *)&regs) + offset), 8,
-                 GetByteOrder());
-  Error error = NativeProcessLinux::PtraceWrapper(
-      PTRACE_GETREGS, m_thread.GetID(), NULL, &regs, sizeof regs);
-  if (error.Success()) {
-    lldb_private::ArchSpec arch;
-    if (m_thread.GetProcess()->GetArchitecture(arch)) {
-      void *target_address = ((uint8_t *)&regs) + offset +
-                             4 * (arch.GetMachine() == llvm::Triple::mips);
-      uint32_t target_size;
-      if ((::strcmp(reg_name, "sr") == 0) ||
-          (::strcmp(reg_name, "cause") == 0) ||
-          (::strcmp(reg_name, "config5") == 0))
-        target_size = 4;
-      else
-        target_size =
-            arch.GetFlags() & lldb_private::ArchSpec::eMIPSABI_O32 ? 4 : 8;
-      value.SetBytes(target_address, target_size, arch.GetByteOrder());
-    } else
-      error.SetErrorString("failed to get architecture");
-  }
-  return error;
+  if (!reg_info)
+    return Error("register %" PRIu32 " not found", reg_index);
+
+  uint32_t offset = reg_info->kinds[lldb::eRegisterKindProcessPlugin];
+
+  if ((offset == ptrace_sr_mips) || (offset == ptrace_config5_mips))
+    return Read_SR_Config(reg_info->byte_offset, reg_info->name,
+                          reg_info->byte_size, value);
+
+  return DoReadRegisterValue(offset, reg_info->name, reg_info->byte_size,
+                             value);
+
+Error NativeRegisterContextLinux_mips64::WriteRegisterRaw(
+    uint32_t reg_index, const RegisterValue &value) {
+  const RegisterInfo *const reg_info = GetRegisterInfoAtIndex(reg_index);
+
+  if (!reg_info)
+    return Error("register %" PRIu32 " not found", reg_index);
+
+  if (reg_info->invalidate_regs)
+    lldbassert(false && "reg_info->invalidate_regs is unhandled");
+
+  uint32_t offset = reg_info->kinds[lldb::eRegisterKindProcessPlugin];
+  return DoWriteRegisterValue(offset, reg_info->name, value);
 }
 
-Error NativeRegisterContextLinux_mips64::DoWriteRegisterValue(
-    uint32_t offset, const char *reg_name, const RegisterValue &value) {
+Error NativeRegisterContextLinux_mips64::Read_SR_Config(uint32_t offset,
+                                                        const char *reg_name,
+                                                        uint32_t size,
+                                                        RegisterValue &value) {
   GPR_linux_mips regs;
+  ::memset(&regs, 0, sizeof(GPR_linux_mips));
+
   Error error = NativeProcessLinux::PtraceWrapper(
       PTRACE_GETREGS, m_thread.GetID(), NULL, &regs, sizeof regs);
   if (error.Success()) {
     lldb_private::ArchSpec arch;
     if (m_thread.GetProcess()->GetArchitecture(arch)) {
-      ::memcpy((void *)(((unsigned char *)(&regs)) + offset), value.GetBytes(),
-               arch.GetFlags() & lldb_private::ArchSpec::eMIPSABI_O32 ? 4 : 8);
-      error = NativeProcessLinux::PtraceWrapper(
-          PTRACE_SETREGS, m_thread.GetID(), NULL, &regs, sizeof regs);
+      void *target_address = ((uint8_t *)&regs) + offset +
+                             4 * (arch.GetMachine() == llvm::Triple::mips);
+      value.SetUInt(*(uint32_t *)target_address, size);
     } else
       error.SetErrorString("failed to get architecture");
   }
   return error;
 }
 
 Error NativeRegisterContextLinux_mips64::DoReadWatchPointRegisterValue(
     lldb::tid_t tid, void *watch_readback) {

lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips.h

#define FPR_OFFSET(regname)                                                    \
    LLVM_EXTENSION offsetof(FPR_linux_mips, regname))
 
 // Computes the offset of the given MSA in the extended data area.
 #define MSA_OFFSET(regname)                                                    \
   (LLVM_EXTENSION offsetof(UserArea, msa) +                                    \
    LLVM_EXTENSION offsetof(MSA_linux_mips, regname))
 
 // Note that the size and offset will be updated by platform-specific classes.
-#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)                       \
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3)                              \
   {                                                                            \
     #reg, alt, sizeof(((GPR_linux_mips *) NULL)->reg) / 2,                     \
                       GPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   gpr_##reg##_mips },                          \
                                   NULL, NULL, NULL, 0                          \
   }
 
 const uint8_t dwarf_opcode_mips[] = {
     llvm::dwarf::DW_OP_regx,  dwarf_sr_mips,          llvm::dwarf::DW_OP_lit1,
     llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shl, llvm::dwarf::DW_OP_and,
     llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shr};
 
-#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)                       \
+#define DEFINE_FPR(reg, alt, kind1, kind2, kind3)                              \
   {                                                                            \
     #reg, alt, sizeof(((FPR_linux_mips *) NULL)->reg),                         \
                       FPR_OFFSET(reg), eEncodingIEEE754, eFormatFloat,         \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   fpr_##reg##_mips },                          \
                                   NULL, NULL, dwarf_opcode_mips,               \
                                   sizeof(dwarf_opcode_mips)                    \
   }
 
-#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3, kind4)                  \
+#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3)                         \
   {                                                                            \
     #reg, alt, sizeof(((FPR_linux_mips *) NULL)->reg),                         \
                       FPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   fpr_##reg##_mips },                          \
                                   NULL, NULL, NULL, 0                          \
   }
 
 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4)                       \
   {                                                                            \
     #reg, alt, sizeof(((MSA_linux_mips *) 0)->reg),                            \
                       MSA_OFFSET(reg), eEncodingVector, eFormatVectorOfUInt8,  \
#reg, alt, sizeof(((MSA_linux_mips *) 0)->reg),                            \
                                   msa_##reg##_mips },                          \
                                   NULL, NULL, NULL, 0                          \
   }
 
 // RegisterKind: EH_Frame, DWARF, Generic, Procss Plugin, LLDB
 
 static RegisterInfo g_register_infos_mips[] = {
     DEFINE_GPR(zero, "zero", dwarf_zero_mips, dwarf_zero_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
-    DEFINE_GPR(r1, "at", dwarf_r1_mips, dwarf_r1_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_GPR(r2, nullptr, dwarf_r2_mips, dwarf_r2_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_GPR(r3, nullptr, dwarf_r3_mips, dwarf_r3_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),
+    DEFINE_GPR(r1, "at", dwarf_r1_mips, dwarf_r1_mips, LLDB_INVALID_REGNUM),
+    DEFINE_GPR(r2, nullptr, dwarf_r2_mips, dwarf_r2_mips, LLDB_INVALID_REGNUM),
+    DEFINE_GPR(r3, nullptr, dwarf_r3_mips, dwarf_r3_mips, LLDB_INVALID_REGNUM),
     DEFINE_GPR(r4, nullptr, dwarf_r4_mips, dwarf_r4_mips,
-               LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG1),
     DEFINE_GPR(r5, nullptr, dwarf_r5_mips, dwarf_r5_mips,
-               LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG2),
     DEFINE_GPR(r6, nullptr, dwarf_r6_mips, dwarf_r6_mips,
-               LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG3),
     DEFINE_GPR(r7, nullptr, dwarf_r7_mips, dwarf_r7_mips,
-               LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM),
-    DEFINE_GPR(r8, nullptr, dwarf_r8_mips, dwarf_r8_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_GPR(r9, nullptr, dwarf_r9_mips, dwarf_r9_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG4),
+    DEFINE_GPR(r8, nullptr, dwarf_r8_mips, dwarf_r8_mips, LLDB_INVALID_REGNUM),
+    DEFINE_GPR(r9, nullptr, dwarf_r9_mips, dwarf_r9_mips, LLDB_INVALID_REGNUM),
     DEFINE_GPR(r10, nullptr, dwarf_r10_mips, dwarf_r10_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r11, nullptr, dwarf_r11_mips, dwarf_r11_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r12, nullptr, dwarf_r12_mips, dwarf_r12_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r13, nullptr, dwarf_r13_mips, dwarf_r13_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r14, nullptr, dwarf_r14_mips, dwarf_r14_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r15, nullptr, dwarf_r15_mips, dwarf_r15_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r16, nullptr, dwarf_r16_mips, dwarf_r16_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r17, nullptr, dwarf_r17_mips, dwarf_r17_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r18, nullptr, dwarf_r18_mips, dwarf_r18_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r19, nullptr, dwarf_r19_mips, dwarf_r19_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r20, nullptr, dwarf_r20_mips, dwarf_r20_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r21, nullptr, dwarf_r21_mips, dwarf_r21_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r22, nullptr, dwarf_r22_mips, dwarf_r22_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r23, nullptr, dwarf_r23_mips, dwarf_r23_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r24, nullptr, dwarf_r24_mips, dwarf_r24_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r25, nullptr, dwarf_r25_mips, dwarf_r25_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r26, nullptr, dwarf_r26_mips, dwarf_r26_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
-    DEFINE_GPR(r27, nullptr, dwarf_r27_mips, dwarf_r27_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
-    DEFINE_GPR(gp, "gp", dwarf_gp_mips, dwarf_gp_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),
-    DEFINE_GPR(sp, "sp", dwarf_sp_mips, dwarf_sp_mips, LLDB_REGNUM_GENERIC_SP,
+    DEFINE_GPR(r27, nullptr, dwarf_r27_mips, dwarf_r27_mips,
                LLDB_INVALID_REGNUM),
+    DEFINE_GPR(gp, "gp", dwarf_gp_mips, dwarf_gp_mips, LLDB_INVALID_REGNUM),
+    DEFINE_GPR(sp, "sp", dwarf_sp_mips, dwarf_sp_mips, LLDB_REGNUM_GENERIC_SP),
     DEFINE_GPR(r30, "fp", dwarf_r30_mips, dwarf_r30_mips,
-               LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM),
-    DEFINE_GPR(ra, "ra", dwarf_ra_mips, dwarf_ra_mips, LLDB_REGNUM_GENERIC_RA,
-               LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_FP),
+    DEFINE_GPR(ra, "ra", dwarf_ra_mips, dwarf_ra_mips, LLDB_REGNUM_GENERIC_RA),
     DEFINE_GPR(sr, "status", dwarf_sr_mips, dwarf_sr_mips,
-               LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_FLAGS),
     DEFINE_GPR(mullo, nullptr, dwarf_lo_mips, dwarf_lo_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(mulhi, nullptr, dwarf_hi_mips, dwarf_hi_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(badvaddr, nullptr, dwarf_bad_mips, dwarf_bad_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(cause, nullptr, dwarf_cause_mips, dwarf_cause_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(pc, nullptr, dwarf_pc_mips, dwarf_pc_mips,
-               LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_PC),
     DEFINE_GPR(config5, nullptr, dwarf_config5_mips, dwarf_config5_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f0, nullptr, dwarf_f0_mips, dwarf_f0_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f1, nullptr, dwarf_f1_mips, dwarf_f1_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f2, nullptr, dwarf_f2_mips, dwarf_f2_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f3, nullptr, dwarf_f3_mips, dwarf_f3_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f4, nullptr, dwarf_f4_mips, dwarf_f4_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f5, nullptr, dwarf_f5_mips, dwarf_f5_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f6, nullptr, dwarf_f6_mips, dwarf_f6_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f7, nullptr, dwarf_f7_mips, dwarf_f7_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f8, nullptr, dwarf_f8_mips, dwarf_f8_mips, LLDB_INVALID_REGNUM,
-               LLDB_INVALID_REGNUM),
-    DEFINE_FPR(f9, nullptr, dwarf_f9_mips, dwarf_f9_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f0, nullptr, dwarf_f0_mips, dwarf_f0_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f1, nullptr, dwarf_f1_mips, dwarf_f1_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f2, nullptr, dwarf_f2_mips, dwarf_f2_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f3, nullptr, dwarf_f3_mips, dwarf_f3_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f4, nullptr, dwarf_f4_mips, dwarf_f4_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f5, nullptr, dwarf_f5_mips, dwarf_f5_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f6, nullptr, dwarf_f6_mips, dwarf_f6_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f7, nullptr, dwarf_f7_mips, dwarf_f7_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f8, nullptr, dwarf_f8_mips, dwarf_f8_mips, LLDB_INVALID_REGNUM),
+    DEFINE_FPR(f9, nullptr, dwarf_f9_mips, dwarf_f9_mips, LLDB_INVALID_REGNUM),
     DEFINE_FPR(f10, nullptr, dwarf_f10_mips, dwarf_f10_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f11, nullptr, dwarf_f11_mips, dwarf_f11_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f12, nullptr, dwarf_f12_mips, dwarf_f12_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f13, nullptr, dwarf_f13_mips, dwarf_f13_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f14, nullptr, dwarf_f14_mips, dwarf_f14_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f15, nullptr, dwarf_f15_mips, dwarf_f15_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f16, nullptr, dwarf_f16_mips, dwarf_f16_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f17, nullptr, dwarf_f17_mips, dwarf_f17_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f18, nullptr, dwarf_f18_mips, dwarf_f18_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f19, nullptr, dwarf_f19_mips, dwarf_f19_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f20, nullptr, dwarf_f20_mips, dwarf_f20_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f21, nullptr, dwarf_f21_mips, dwarf_f21_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f22, nullptr, dwarf_f22_mips, dwarf_f22_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f23, nullptr, dwarf_f23_mips, dwarf_f23_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f24, nullptr, dwarf_f24_mips, dwarf_f24_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f25, nullptr, dwarf_f25_mips, dwarf_f25_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f26, nullptr, dwarf_f26_mips, dwarf_f26_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f27, nullptr, dwarf_f27_mips, dwarf_f27_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f28, nullptr, dwarf_f28_mips, dwarf_f28_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f29, nullptr, dwarf_f29_mips, dwarf_f29_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f30, nullptr, dwarf_f30_mips, dwarf_f30_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f31, nullptr, dwarf_f31_mips, dwarf_f31_mips,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
-                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+                    LLDB_INVALID_REGNUM),
     DEFINE_FPR_INFO(fir, nullptr, dwarf_fir_mips, dwarf_fir_mips,
-                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+                    LLDB_INVALID_REGNUM),
     DEFINE_FPR_INFO(config5, nullptr, dwarf_config5_mips, dwarf_config5_mips,
-                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+                    LLDB_INVALID_REGNUM),
     DEFINE_MSA(w0, nullptr, dwarf_w0_mips, dwarf_w0_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),
     DEFINE_MSA(w1, nullptr, dwarf_w1_mips, dwarf_w1_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),
     DEFINE_MSA(w2, nullptr, dwarf_w2_mips, dwarf_w2_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),
     DEFINE_MSA(w3, nullptr, dwarf_w3_mips, dwarf_w3_mips, LLDB_INVALID_REGNUM,
                LLDB_INVALID_REGNUM),

lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_mips64.h

 #define MSA_OFFSET(regname)                                                    \
   (LLVM_EXTENSION offsetof(UserArea, msa) +                                    \
    LLVM_EXTENSION offsetof(MSA_linux_mips, regname))
 
 // RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB
 
 // Note that the size and offset will be updated by platform-specific classes.
 #ifdef LINUX_MIPS64
-#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)                       \
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3)                              \
   {                                                                            \
     #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg),                            \
                       GPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   gpr_##reg##_mips64 },                        \
                                   NULL, NULL, NULL, 0                          \
   }
 #else
 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)                       \
   {                                                                            \
     #reg, alt, sizeof(((GPR_freebsd_mips *) 0)->reg),                          \
                       GPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
                                  {kind1, kind2, kind3, kind4,                  \
                                   gpr_##reg##_mips64 },                        \
                                   NULL, NULL, NULL, 0                          \
   }
 #endif
 
-#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3, kind4)                  \
+#define DEFINE_GPR_INFO(reg, alt, kind1, kind2, kind3)                         \
   {                                                                            \
     #reg, alt, sizeof(((GPR_linux_mips *) 0)->reg) / 2,                        \
                       GPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   gpr_##reg##_mips64 },                        \
                                   NULL, NULL, NULL, 0                          \
   }
 
 const uint8_t dwarf_opcode_mips64[] = {
     llvm::dwarf::DW_OP_regx,  dwarf_sr_mips64,        llvm::dwarf::DW_OP_lit1,
     llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shl, llvm::dwarf::DW_OP_and,
     llvm::dwarf::DW_OP_lit26, llvm::dwarf::DW_OP_shr};
 
-#define DEFINE_FPR(reg, alt, kind1, kind2, kind3, kind4)                       \
+#define DEFINE_FPR(reg, alt, kind1, kind2, kind3)                              \
   {                                                                            \
     #reg, alt, sizeof(((FPR_linux_mips *) 0)->reg),                            \
                       FPR_OFFSET(reg), eEncodingIEEE754, eFormatFloat,         \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   fpr_##reg##_mips64 },                        \
                                   NULL, NULL, dwarf_opcode_mips64,             \
                                   sizeof(dwarf_opcode_mips64)                  \
   }
 
-#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3, kind4)                  \
+#define DEFINE_FPR_INFO(reg, alt, kind1, kind2, kind3)                         \
   {                                                                            \
     #reg, alt, sizeof(((FPR_linux_mips *) 0)->reg),                            \
                       FPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
-                                 {kind1, kind2, kind3, kind4,                  \
+                                 {kind1, kind2, kind3, ptrace_##reg##_mips,    \
                                   fpr_##reg##_mips64 },                        \
                                   NULL, NULL, NULL, 0                          \
   }
 
 #define DEFINE_MSA(reg, alt, kind1, kind2, kind3, kind4)                       \
   {                                                                            \
     #reg, alt, sizeof(((MSA_linux_mips *) 0)->reg),                            \
                       MSA_OFFSET(reg), eEncodingVector, eFormatVectorOfUInt8,  \
#ifndef LINUX_MIPS64
     DEFINE_GPR(pc, "pc", dwarf_pc_mips64, dwarf_pc_mips64,
                LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
     DEFINE_GPR(ic, nullptr, dwarf_ic_mips64, dwarf_ic_mips64,
                LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
     DEFINE_GPR(dummy, nullptr, dwarf_dummy_mips64, dwarf_dummy_mips64,
                LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
 #else
     DEFINE_GPR(zero, "r0", dwarf_zero_mips64, dwarf_zero_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r1, nullptr, dwarf_r1_mips64, dwarf_r1_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r2, nullptr, dwarf_r2_mips64, dwarf_r2_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r3, nullptr, dwarf_r3_mips64, dwarf_r3_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r4, nullptr, dwarf_r4_mips64, dwarf_r4_mips64,
-               LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG1),
     DEFINE_GPR(r5, nullptr, dwarf_r5_mips64, dwarf_r5_mips64,
-               LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG2),
     DEFINE_GPR(r6, nullptr, dwarf_r6_mips64, dwarf_r6_mips64,
-               LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG3),
     DEFINE_GPR(r7, nullptr, dwarf_r7_mips64, dwarf_r7_mips64,
-               LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG4),
     DEFINE_GPR(r8, nullptr, dwarf_r8_mips64, dwarf_r8_mips64,
-               LLDB_REGNUM_GENERIC_ARG5, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG5),
     DEFINE_GPR(r9, nullptr, dwarf_r9_mips64, dwarf_r9_mips64,
-               LLDB_REGNUM_GENERIC_ARG6, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG6),
     DEFINE_GPR(r10, nullptr, dwarf_r10_mips64, dwarf_r10_mips64,
-               LLDB_REGNUM_GENERIC_ARG7, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG7),
     DEFINE_GPR(r11, nullptr, dwarf_r11_mips64, dwarf_r11_mips64,
-               LLDB_REGNUM_GENERIC_ARG8, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_ARG8),
     DEFINE_GPR(r12, nullptr, dwarf_r12_mips64, dwarf_r12_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r13, nullptr, dwarf_r13_mips64, dwarf_r13_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r14, nullptr, dwarf_r14_mips64, dwarf_r14_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r15, nullptr, dwarf_r15_mips64, dwarf_r15_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r16, nullptr, dwarf_r16_mips64, dwarf_r16_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r17, nullptr, dwarf_r17_mips64, dwarf_r17_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r18, nullptr, dwarf_r18_mips64, dwarf_r18_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r19, nullptr, dwarf_r19_mips64, dwarf_r19_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r20, nullptr, dwarf_r20_mips64, dwarf_r20_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r21, nullptr, dwarf_r21_mips64, dwarf_r21_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r22, nullptr, dwarf_r22_mips64, dwarf_r22_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r23, nullptr, dwarf_r23_mips64, dwarf_r23_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r24, nullptr, dwarf_r24_mips64, dwarf_r24_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r25, nullptr, dwarf_r25_mips64, dwarf_r25_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r26, nullptr, dwarf_r26_mips64, dwarf_r26_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(r27, nullptr, dwarf_r27_mips64, dwarf_r27_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
-    DEFINE_GPR(gp, "r28", dwarf_gp_mips64, dwarf_gp_mips64, LLDB_INVALID_REGNUM,
+               LLDB_INVALID_REGNUM),
+    DEFINE_GPR(gp, "r28", dwarf_gp_mips64, dwarf_gp_mips64,
                LLDB_INVALID_REGNUM),
     DEFINE_GPR(sp, "r29", dwarf_sp_mips64, dwarf_sp_mips64,
-               LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_SP),
     DEFINE_GPR(r30, nullptr, dwarf_r30_mips64, dwarf_r30_mips64,
-               LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_FP),
     DEFINE_GPR(ra, "r31", dwarf_ra_mips64, dwarf_ra_mips64,
-               LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_RA),
     DEFINE_GPR_INFO(sr, nullptr, dwarf_sr_mips64, dwarf_sr_mips64,
-                    LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM),
+                    LLDB_REGNUM_GENERIC_FLAGS),
     DEFINE_GPR(mullo, nullptr, dwarf_lo_mips64, dwarf_lo_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(mulhi, nullptr, dwarf_hi_mips64, dwarf_hi_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR(badvaddr, nullptr, dwarf_bad_mips64, dwarf_bad_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_GPR_INFO(cause, nullptr, dwarf_cause_mips64, dwarf_cause_mips64,
-                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+                    LLDB_INVALID_REGNUM),
     DEFINE_GPR(pc, "pc", dwarf_pc_mips64, dwarf_pc_mips64,
-               LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
+               LLDB_REGNUM_GENERIC_PC),
     DEFINE_GPR_INFO(config5, nullptr, dwarf_config5_mips64,
-                    dwarf_config5_mips64, LLDB_INVALID_REGNUM,
-                    LLDB_INVALID_REGNUM),
+                    dwarf_config5_mips64, LLDB_INVALID_REGNUM),
     DEFINE_FPR(f0, nullptr, dwarf_f0_mips64, dwarf_f0_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f1, nullptr, dwarf_f1_mips64, dwarf_f1_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f2, nullptr, dwarf_f2_mips64, dwarf_f2_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f3, nullptr, dwarf_f3_mips64, dwarf_f3_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f4, nullptr, dwarf_f4_mips64, dwarf_f4_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f5, nullptr, dwarf_f5_mips64, dwarf_f5_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f6, nullptr, dwarf_f6_mips64, dwarf_f6_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f7, nullptr, dwarf_f7_mips64, dwarf_f7_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f8, nullptr, dwarf_f8_mips64, dwarf_f8_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f9, nullptr, dwarf_f9_mips64, dwarf_f9_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f10, nullptr, dwarf_f10_mips64, dwarf_f10_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f11, nullptr, dwarf_f11_mips64, dwarf_f11_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f12, nullptr, dwarf_f12_mips64, dwarf_f12_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f13, nullptr, dwarf_f13_mips64, dwarf_f13_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f14, nullptr, dwarf_f14_mips64, dwarf_f14_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f15, nullptr, dwarf_f15_mips64, dwarf_f15_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f16, nullptr, dwarf_f16_mips64, dwarf_f16_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f17, nullptr, dwarf_f17_mips64, dwarf_f17_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f18, nullptr, dwarf_f18_mips64, dwarf_f18_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f19, nullptr, dwarf_f19_mips64, dwarf_f19_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f20, nullptr, dwarf_f20_mips64, dwarf_f20_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f21, nullptr, dwarf_f21_mips64, dwarf_f21_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f22, nullptr, dwarf_f22_mips64, dwarf_f22_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f23, nullptr, dwarf_f23_mips64, dwarf_f23_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f24, nullptr, dwarf_f24_mips64, dwarf_f24_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f25, nullptr, dwarf_f25_mips64, dwarf_f25_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f26, nullptr, dwarf_f26_mips64, dwarf_f26_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f27, nullptr, dwarf_f27_mips64, dwarf_f27_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f28, nullptr, dwarf_f28_mips64, dwarf_f28_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f29, nullptr, dwarf_f29_mips64, dwarf_f29_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f30, nullptr, dwarf_f30_mips64, dwarf_f30_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR(f31, nullptr, dwarf_f31_mips64, dwarf_f31_mips64,
-               LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+               LLDB_INVALID_REGNUM),
     DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
-                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+                    LLDB_INVALID_REGNUM),
     DEFINE_FPR_INFO(fir, nullptr, dwarf_fir_mips64, dwarf_fir_mips64,
-                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
-    DEFINE_FPR_INFO(config5, nullptr, dwarf_config5_mips64,
-                    dwarf_config5_mips64, LLDB_INVALID_REGNUM,
                     LLDB_INVALID_REGNUM),
+    DEFINE_FPR_INFO(config5, nullptr, dwarf_config5_mips64,
+                    dwarf_config5_mips64, LLDB_INVALID_REGNUM),
     DEFINE_MSA(w0, nullptr, dwarf_w0_mips64, dwarf_w0_mips64,
                LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
     DEFINE_MSA(w1, nullptr, dwarf_w1_mips64, dwarf_w1_mips64,
                LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
     DEFINE_MSA(w2, nullptr, dwarf_w2_mips64, dwarf_w2_mips64,
                LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
     DEFINE_MSA(w3, nullptr, dwarf_w3_mips64, dwarf_w3_mips64,
                LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),

lldb/trunk/source/Plugins/Process/Utility/lldb-mips-linux-register-enums.h

enum {
 
   k_num_gpr_registers_mips64 = k_last_gpr_mips64 - k_first_gpr_mips64 + 1,
   k_num_fpr_registers_mips64 = k_last_fpr_mips64 - k_first_fpr_mips64 + 1,
   k_num_msa_registers_mips64 = k_last_msa_mips64 - k_first_msa_mips64 + 1,
   k_num_user_registers_mips64 = k_num_gpr_registers_mips64 +
                                 k_num_fpr_registers_mips64 +
                                 k_num_msa_registers_mips64
 };
+
+// Register no. for RegisterKind = eRegisterKindProcessPlugin
+// The ptrace request PTRACE_PEEKUSER/PTRACE_POKEUSER used this number
+enum {
+  ptrace_zero_mips,
+  ptrace_r1_mips,
+  ptrace_r2_mips,
+  ptrace_r3_mips,
+  ptrace_r4_mips,
+  ptrace_r5_mips,
+  ptrace_r6_mips,
+  ptrace_r7_mips,
+  ptrace_r8_mips,
+  ptrace_r9_mips,
+  ptrace_r10_mips,
+  ptrace_r11_mips,
+  ptrace_r12_mips,
+  ptrace_r13_mips,
+  ptrace_r14_mips,
+  ptrace_r15_mips,
+  ptrace_r16_mips,
+  ptrace_r17_mips,
+  ptrace_r18_mips,
+  ptrace_r19_mips,
+  ptrace_r20_mips,
+  ptrace_r21_mips,
+  ptrace_r22_mips,
+  ptrace_r23_mips,
+  ptrace_r24_mips,
+  ptrace_r25_mips,
+  ptrace_r26_mips,
+  ptrace_r27_mips,
+  ptrace_gp_mips,
+  ptrace_sp_mips,
+  ptrace_r30_mips,
+  ptrace_ra_mips,
+  ptrace_f0_mips,
+  ptrace_f1_mips,
+  ptrace_f2_mips,
+  ptrace_f3_mips,
+  ptrace_f4_mips,
+  ptrace_f5_mips,
+  ptrace_f6_mips,
+  ptrace_f7_mips,
+  ptrace_f8_mips,
+  ptrace_f9_mips,
+  ptrace_f10_mips,
+  ptrace_f11_mips,
+  ptrace_f12_mips,
+  ptrace_f13_mips,
+  ptrace_f14_mips,
+  ptrace_f15_mips,
+  ptrace_f16_mips,
+  ptrace_f17_mips,
+  ptrace_f18_mips,
+  ptrace_f19_mips,
+  ptrace_f20_mips,
+  ptrace_f21_mips,
+  ptrace_f22_mips,
+  ptrace_f23_mips,
+  ptrace_f24_mips,
+  ptrace_f25_mips,
+  ptrace_f26_mips,
+  ptrace_f27_mips,
+  ptrace_f28_mips,
+  ptrace_f29_mips,
+  ptrace_f30_mips,
+  ptrace_f31_mips,
+  ptrace_pc_mips,
+  ptrace_cause_mips,
+  ptrace_badvaddr_mips,
+  ptrace_mulhi_mips,
+  ptrace_mullo_mips,
+  ptrace_fcsr_mips,
+  ptrace_fir_mips,
+  ptrace_sr_mips,
+  ptrace_config5_mips
+};
 }
 
 #endif // #ifndef lldb_mips_linux_register_enums_h