[X86][SSE] Improve recognition of uitofp conversions that can be performed as sitofp

[RKSimon]

Summary

With D24253 we can now use SelectionDAG::SignBitIsZero with vector operations.

This patch uses SelectionDAG::SignBitIsZero to recognise that a zero sign bit means that we can use a sitofp instead of a uitofp (which is not directly support on pre-AVX512 hardware).

While AVX512 does provide support for uitofp, the conversion to sitofp should not cause any regressions.

[RKSimon]

ping?

[majnemer]

test/CodeGen/X86/i64-to-float.ll

49–52

Was this here before?

51–54

Ditto.

[RKSimon]

test/CodeGen/X86/i64-to-float.ll

49–52

The stack spill/restore is a mess but the (f64 sitofp(i64)) fpu approach appears to be the better performing option on 32-bit targets.

Its also what gcc / icc does: https://godbolt.org/g/CMPJrA

[RKSimon]

Updated now that D24345 has been committed

[zvi]

LGTM

[delena]

Please update the cost of this conversion. You may do this in a separate patch, if you want.

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2,
 
   // Could not fold it.
   return SDValue();
 }
 
 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero.  We
 /// use this predicate to simplify operations downstream.
 bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
-  // This predicate is not safe for vector operations.
-  if (Op.getValueType().isVector())
-    return false;
-
   unsigned BitWidth = Op.getScalarValueSizeInBits();
   return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
 }
 
 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero.  We use
 /// this predicate to simplify operations downstream.  Mask is known to be zero
 /// for bits that V cannot have.
 bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,

lib/Target/X86/X86ISelLowering.cpp

 }
 
 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
                                            SelectionDAG &DAG) const {
   SDValue N0 = Op.getOperand(0);
   SDLoc dl(Op);
   auto PtrVT = getPointerTy(DAG.getDataLayout());
 
-  if (Op.getSimpleValueType().isVector())
-    return lowerUINT_TO_FP_vec(Op, DAG);
-
   // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
   // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
   // the optimization here.
   if (DAG.SignBitIsZero(N0))
     return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
 
+  if (Op.getSimpleValueType().isVector())
+    return lowerUINT_TO_FP_vec(Op, DAG);
+
   MVT SrcVT = N0.getSimpleValueType();
   MVT DstVT = Op.getSimpleValueType();
 
   if (Subtarget.hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
       (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget.is64Bit()))) {
     // Conversions from unsigned i32 to f32/f64 are legal,
     // using VCVTUSI2SS/SD.  Same for i64 in 64-bit mode.
     return Op;
if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
     SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
 
     if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
       return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
 
     return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
   }
 
+  // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
+  // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
+  // the optimization here.
+  if (DAG.SignBitIsZero(Op0))
+    return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, Op0);
+
   return SDValue();
 }
 
 static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
                                const X86Subtarget &Subtarget) {
   // First try to optimize away the conversion entirely when it's
   // conditionally from a constant. Vectors only.
   if (SDValue Res = combineVectorCompareAndMaskUnaryOp(N, DAG))

test/CodeGen/X86/avx512-cvt.ll

; SKX-NEXT:    retq
   %1 = sitofp <2 x i1> %cmpres to <2 x double>
   ret <2 x double> %1
 }
 
 define <16 x float> @uitofp_16i8(<16 x i8>%a) {
 ; ALL-LABEL: uitofp_16i8:
 ; ALL:       ## BB#0:
 ; ALL-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; ALL-NEXT:    vcvtudq2ps %zmm0, %zmm0
+; ALL-NEXT:    vcvtdq2ps %zmm0, %zmm0
 ; ALL-NEXT:    retq
   %b = uitofp <16 x i8> %a to <16 x float>
   ret <16 x float>%b
 }
 
 define <16 x float> @uitofp_16i16(<16 x i16>%a) {
 ; ALL-LABEL: uitofp_16i16:
 ; ALL:       ## BB#0:
 ; ALL-NEXT:    vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
-; ALL-NEXT:    vcvtudq2ps %zmm0, %zmm0
+; ALL-NEXT:    vcvtdq2ps %zmm0, %zmm0
 ; ALL-NEXT:    retq
   %b = uitofp <16 x i16> %a to <16 x float>
   ret <16 x float>%b
 }
 
 define <16 x float> @uitofp_16i1_float(<16 x i32> %a) {
 ; ALL-LABEL: uitofp_16i1_float:
 ; ALL:       ## BB#0:
; SKX-NEXT:    retq
   ret <8 x double> %1
 }
 
 define <4 x float> @uitofp_4i1_float(<4 x i32> %a) {
 ; KNL-LABEL: uitofp_4i1_float:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; KNL-NEXT:    vpcmpgtd %xmm0, %xmm1, %xmm0
-; KNL-NEXT:    vpsrld $31, %xmm0, %xmm0
-; KNL-NEXT:    vcvtudq2ps %zmm0, %zmm0
-; KNL-NEXT:    ## kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
+; KNL-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm1
+; KNL-NEXT:    vpand %xmm1, %xmm0, %xmm0
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: uitofp_4i1_float:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpxord %xmm1, %xmm1, %xmm1
 ; SKX-NEXT:    vpcmpgtd %xmm0, %xmm1, %k1
 ; SKX-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
 ; SKX-NEXT:    vcvtudq2ps %xmm0, %xmm0
 ; SKX-NEXT:    retq
   %mask = icmp slt <4 x i32> %a, zeroinitializer
   %1 = uitofp <4 x i1> %mask to <4 x float>
   ret <4 x float> %1
 }
 
 define <4 x double> @uitofp_4i1_double(<4 x i32> %a) {
 ; KNL-LABEL: uitofp_4i1_double:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; KNL-NEXT:    vpcmpgtd %xmm0, %xmm1, %xmm0
 ; KNL-NEXT:    vpsrld $31, %xmm0, %xmm0
-; KNL-NEXT:    vcvtudq2pd %ymm0, %zmm0
-; KNL-NEXT:    ## kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
+; KNL-NEXT:    vcvtdq2pd %xmm0, %ymm0
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: uitofp_4i1_double:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpxord %xmm1, %xmm1, %xmm1
 ; SKX-NEXT:    vpcmpgtd %xmm0, %xmm1, %k1
 ; SKX-NEXT:    vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
 ; SKX-NEXT:    vcvtudq2pd %xmm0, %ymm0

 define <2 x double> @uitofp_2i1_double(<2 x i32> %a) {
 ; KNL-LABEL: uitofp_2i1_double:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vpxor %xmm1, %xmm1, %xmm1
 ; KNL-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
 ; KNL-NEXT:    vmovdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
 ; KNL-NEXT:    vpxor %xmm1, %xmm0, %xmm0
 ; KNL-NEXT:    vpcmpgtq %xmm0, %xmm1, %xmm0
-; KNL-NEXT:    vpsrlq $63, %xmm0, %xmm0
-; KNL-NEXT:    vpextrq $1, %xmm0, %rax
-; KNL-NEXT:    vcvtusi2sdq %rax, %xmm0, %xmm1
-; KNL-NEXT:    vmovq %xmm0, %rax
-; KNL-NEXT:    vcvtusi2sdq %rax, %xmm0, %xmm0
-; KNL-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; KNL-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: uitofp_2i1_double:
 ; SKX:       ## BB#0:
 ; SKX-NEXT:    vpxord %xmm1, %xmm1, %xmm1
 ; SKX-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
 ; SKX-NEXT:    vpcmpltuq %xmm1, %xmm0, %k1
 ; SKX-NEXT:    vmovdqa64 {{.*}}(%rip), %xmm0 {%k1} {z}
 ; SKX-NEXT:    vcvtuqq2pd %xmm0, %xmm0
 ; SKX-NEXT:    retq
   %mask = icmp ult <2 x i32> %a, zeroinitializer
   %1 = uitofp <2 x i1> %mask to <2 x double>
   ret <2 x double> %1
 }

test/CodeGen/X86/i64-to-float.ll

; X64-AVX-NEXT:    retq
   %and = and <2 x i64> %a, <i64 255, i64 65535>
   %cvt = sitofp <2 x i64> %and to <2 x double>
   ret <2 x double> %cvt
 }
 
 define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind {
 ; X32-SSE-LABEL: mask_uitofp_2i64_2f64:
 ; X32-SSE:       # BB#0:
+; X32-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
 ; X32-SSE-NEXT:    pand {{\.LCPI.*}}, %xmm0
-; X32-SSE-NEXT:    movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X32-SSE-NEXT:    movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
-; X32-SSE-NEXT:    subpd %xmm3, %xmm0
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; X32-SSE-NEXT:    addpd %xmm4, %xmm0
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
-; X32-SSE-NEXT:    subpd %xmm3, %xmm2
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
-; X32-SSE-NEXT:    addpd %xmm2, %xmm1
-; X32-SSE-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X32-SSE-NEXT:    cvtdq2pd %xmm0, %xmm0
 ; X32-SSE-NEXT:    retl
 ;
 ; X32-AVX-LABEL: mask_uitofp_2i64_2f64:
 ; X32-AVX:       # BB#0:
-; X32-AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
-; X32-AVX-NEXT:    vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X32-AVX-NEXT:    vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
-; X32-AVX-NEXT:    vsubpd %xmm3, %xmm2, %xmm2
-; X32-AVX-NEXT:    vhaddpd %xmm2, %xmm2, %xmm2
-; X32-AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; X32-AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X32-AVX-NEXT:    vsubpd %xmm3, %xmm0, %xmm0
-; X32-AVX-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
-; X32-AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; X32-AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u]
+; X32-AVX-NEXT:    vcvtdq2pd %xmm0, %xmm0
 ; X32-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: mask_uitofp_2i64_2f64:
 ; X64-SSE:       # BB#0:
+; X64-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
 ; X64-SSE-NEXT:    pand {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT:    movdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-SSE-NEXT:    movapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
-; X64-SSE-NEXT:    subpd %xmm3, %xmm0
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; X64-SSE-NEXT:    addpd %xmm4, %xmm0
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
-; X64-SSE-NEXT:    subpd %xmm3, %xmm2
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
-; X64-SSE-NEXT:    addpd %xmm2, %xmm1
-; X64-SSE-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-SSE-NEXT:    cvtdq2pd %xmm0, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX-LABEL: mask_uitofp_2i64_2f64:
 ; X64-AVX:       # BB#0:
-; X64-AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT:    vmovdqa {{.*#+}} xmm1 = [1127219200,1160773632,0,0]
-; X64-AVX-NEXT:    vpunpckldq {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-AVX-NEXT:    vmovapd {{.*#+}} xmm3 = [4.503600e+15,1.934281e+25]
-; X64-AVX-NEXT:    vsubpd %xmm3, %xmm2, %xmm2
-; X64-AVX-NEXT:    vhaddpd %xmm2, %xmm2, %xmm2
-; X64-AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; X64-AVX-NEXT:    vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-AVX-NEXT:    vsubpd %xmm3, %xmm0, %xmm0
-; X64-AVX-NEXT:    vhaddpd %xmm0, %xmm0, %xmm0
-; X64-AVX-NEXT:    vunpcklpd {{.*#+}} xmm0 = xmm2[0],xmm0[0]
+; X64-AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u]
+; X64-AVX-NEXT:    vcvtdq2pd %xmm0, %xmm0
 ; X64-AVX-NEXT:    retq
   %and = and <2 x i64> %a, <i64 255, i64 65535>
   %cvt = uitofp <2 x i64> %and to <2 x double>
   ret <2 x double> %cvt
 }
 
 define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
 ; X32-SSE-LABEL: mask_sitofp_4i64_4f32:
; X64-AVX-NEXT:    retq
   %and = and <4 x i64> %a, <i64 127, i64 255, i64 4095, i64 65535>
   %cvt = sitofp <4 x i64> %and to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
 ; X32-SSE-LABEL: mask_uitofp_4i64_4f32:
 ; X32-SSE:       # BB#0:
-; X32-SSE-NEXT:    pushl %ebp
-; X32-SSE-NEXT:    movl %esp, %ebp
-; X32-SSE-NEXT:    andl $-8, %esp
-; X32-SSE-NEXT:    subl $48, %esp
 ; X32-SSE-NEXT:    pand {{\.LCPI.*}}, %xmm0
 ; X32-SSE-NEXT:    pand {{\.LCPI.*}}, %xmm1
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
-; X32-SSE-NEXT:    movq %xmm2, {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; X32-SSE-NEXT:    movq %xmm2, {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    movq %xmm1, {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    movq %xmm0, {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
-; X32-SSE-NEXT:    movd %xmm2, %eax
-; X32-SSE-NEXT:    xorl %ecx, %ecx
-; X32-SSE-NEXT:    testl %eax, %eax
-; X32-SSE-NEXT:    setns %cl
-; X32-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
-; X32-SSE-NEXT:    fstps {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
-; X32-SSE-NEXT:    movd %xmm2, %eax
-; X32-SSE-NEXT:    xorl %ecx, %ecx
-; X32-SSE-NEXT:    testl %eax, %eax
-; X32-SSE-NEXT:    setns %cl
-; X32-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
-; X32-SSE-NEXT:    fstps (%esp)
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
-; X32-SSE-NEXT:    movd %xmm1, %eax
-; X32-SSE-NEXT:    xorl %ecx, %ecx
-; X32-SSE-NEXT:    testl %eax, %eax
-; X32-SSE-NEXT:    setns %cl
-; X32-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
-; X32-SSE-NEXT:    fstps {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
-; X32-SSE-NEXT:    movd %xmm0, %eax
-; X32-SSE-NEXT:    xorl %ecx, %ecx
-; X32-SSE-NEXT:    testl %eax, %eax
-; X32-SSE-NEXT:    setns %cl
-; X32-SSE-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    fadds {{\.LCPI.*}}(,%ecx,4)
-; X32-SSE-NEXT:    fstps {{[0-9]+}}(%esp)
-; X32-SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-SSE-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; X32-SSE-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; X32-SSE-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; X32-SSE-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
-; X32-SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X32-SSE-NEXT:    movl %ebp, %esp
-; X32-SSE-NEXT:    popl %ebp
+; X32-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; X32-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X32-SSE-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X32-SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; X32-SSE-NEXT:    retl
 ;
 ; X32-AVX-LABEL: mask_uitofp_4i64_4f32:
 ; X32-AVX:       # BB#0:
-; X32-AVX-NEXT:    pushl %ebp
-; X32-AVX-NEXT:    movl %esp, %ebp
-; X32-AVX-NEXT:    pushl %ebx
-; X32-AVX-NEXT:    pushl %esi
-; X32-AVX-NEXT:    andl $-8, %esp
-; X32-AVX-NEXT:    subl $48, %esp
 ; X32-AVX-NEXT:    vandps {{\.LCPI.*}}, %ymm0, %ymm0
-; X32-AVX-NEXT:    vpextrd $1, %xmm0, %eax
-; X32-AVX-NEXT:    vpinsrd $1, %eax, %xmm0, %xmm1
-; X32-AVX-NEXT:    vmovq %xmm1, {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    vpextrd $3, %xmm0, %ecx
-; X32-AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; X32-AVX-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
-; X32-AVX-NEXT:    vmovq %xmm1, {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; X32-AVX-NEXT:    vpextrd $1, %xmm0, %edx
-; X32-AVX-NEXT:    vpinsrd $1, %edx, %xmm0, %xmm1
-; X32-AVX-NEXT:    vmovq %xmm1, {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    vpextrd $3, %xmm0, %esi
-; X32-AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; X32-AVX-NEXT:    vpinsrd $1, %esi, %xmm0, %xmm0
-; X32-AVX-NEXT:    vmovq %xmm0, {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    xorl %ebx, %ebx
-; X32-AVX-NEXT:    testl %eax, %eax
-; X32-AVX-NEXT:    setns %bl
-; X32-AVX-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    fadds {{\.LCPI.*}}(,%ebx,4)
-; X32-AVX-NEXT:    fstps (%esp)
-; X32-AVX-NEXT:    xorl %eax, %eax
-; X32-AVX-NEXT:    testl %ecx, %ecx
-; X32-AVX-NEXT:    setns %al
-; X32-AVX-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
-; X32-AVX-NEXT:    fstps {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    xorl %eax, %eax
-; X32-AVX-NEXT:    testl %edx, %edx
-; X32-AVX-NEXT:    setns %al
-; X32-AVX-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
-; X32-AVX-NEXT:    fstps {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    xorl %eax, %eax
-; X32-AVX-NEXT:    testl %esi, %esi
-; X32-AVX-NEXT:    setns %al
-; X32-AVX-NEXT:    fildll {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
-; X32-AVX-NEXT:    fstps {{[0-9]+}}(%esp)
-; X32-AVX-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
-; X32-AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
-; X32-AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
-; X32-AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
-; X32-AVX-NEXT:    leal -8(%ebp), %esp
-; X32-AVX-NEXT:    popl %esi
-; X32-AVX-NEXT:    popl %ebx
-; X32-AVX-NEXT:    popl %ebp
+; X32-AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; X32-AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
+; X32-AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X32-AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; X32-AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X32-AVX-NEXT:    vzeroupper
 ; X32-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: mask_uitofp_4i64_4f32:
 ; X64-SSE:       # BB#0:
 ; X64-SSE-NEXT:    pand {{.*}}(%rip), %xmm0
 ; X64-SSE-NEXT:    pand {{.*}}(%rip), %xmm1
-; X64-SSE-NEXT:    movd %xmm1, %rax
-; X64-SSE-NEXT:    testq %rax, %rax
-; X64-SSE-NEXT:    js .LBB3_1
-; X64-SSE-NEXT:  # BB#2:
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm3
-; X64-SSE-NEXT:    jmp .LBB3_3
-; X64-SSE-NEXT:  .LBB3_1:
-; X64-SSE-NEXT:    movq %rax, %rcx
-; X64-SSE-NEXT:    shrq %rcx
-; X64-SSE-NEXT:    andl $1, %eax
-; X64-SSE-NEXT:    orq %rcx, %rax
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm3
-; X64-SSE-NEXT:    addss %xmm3, %xmm3
-; X64-SSE-NEXT:  .LBB3_3:
-; X64-SSE-NEXT:    movd %xmm0, %rax
-; X64-SSE-NEXT:    testq %rax, %rax
-; X64-SSE-NEXT:    js .LBB3_4
-; X64-SSE-NEXT:  # BB#5:
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm2
-; X64-SSE-NEXT:    jmp .LBB3_6
-; X64-SSE-NEXT:  .LBB3_4:
-; X64-SSE-NEXT:    movq %rax, %rcx
-; X64-SSE-NEXT:    shrq %rcx
-; X64-SSE-NEXT:    andl $1, %eax
-; X64-SSE-NEXT:    orq %rcx, %rax
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm2
-; X64-SSE-NEXT:    addss %xmm2, %xmm2
-; X64-SSE-NEXT:  .LBB3_6:
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
-; X64-SSE-NEXT:    movd %xmm1, %rax
-; X64-SSE-NEXT:    testq %rax, %rax
-; X64-SSE-NEXT:    js .LBB3_7
-; X64-SSE-NEXT:  # BB#8:
-; X64-SSE-NEXT:    xorps %xmm1, %xmm1
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm1
-; X64-SSE-NEXT:    jmp .LBB3_9
-; X64-SSE-NEXT:  .LBB3_7:
-; X64-SSE-NEXT:    movq %rax, %rcx
-; X64-SSE-NEXT:    shrq %rcx
-; X64-SSE-NEXT:    andl $1, %eax
-; X64-SSE-NEXT:    orq %rcx, %rax
-; X64-SSE-NEXT:    xorps %xmm1, %xmm1
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm1
-; X64-SSE-NEXT:    addss %xmm1, %xmm1
-; X64-SSE-NEXT:  .LBB3_9:
-; X64-SSE-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
-; X64-SSE-NEXT:    movd %xmm0, %rax
-; X64-SSE-NEXT:    testq %rax, %rax
-; X64-SSE-NEXT:    js .LBB3_10
-; X64-SSE-NEXT:  # BB#11:
-; X64-SSE-NEXT:    xorps %xmm0, %xmm0
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm0
-; X64-SSE-NEXT:    jmp .LBB3_12
-; X64-SSE-NEXT:  .LBB3_10:
-; X64-SSE-NEXT:    movq %rax, %rcx
-; X64-SSE-NEXT:    shrq %rcx
-; X64-SSE-NEXT:    andl $1, %eax
-; X64-SSE-NEXT:    orq %rcx, %rax
-; X64-SSE-NEXT:    xorps %xmm0, %xmm0
-; X64-SSE-NEXT:    cvtsi2ssq %rax, %xmm0
-; X64-SSE-NEXT:    addss %xmm0, %xmm0
-; X64-SSE-NEXT:  .LBB3_12:
-; X64-SSE-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-SSE-NEXT:    unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
-; X64-SSE-NEXT:    movaps %xmm2, %xmm0
+; X64-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
+; X64-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X64-SSE-NEXT:    punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; X64-SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX-LABEL: mask_uitofp_4i64_4f32:
 ; X64-AVX:       # BB#0:
 ; X64-AVX-NEXT:    vandps {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX-NEXT:    vpextrq $1, %xmm0, %rax
-; X64-AVX-NEXT:    testq %rax, %rax
-; X64-AVX-NEXT:    js .LBB3_1
-; X64-AVX-NEXT:  # BB#2:
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
-; X64-AVX-NEXT:    jmp .LBB3_3
-; X64-AVX-NEXT:  .LBB3_1:
-; X64-AVX-NEXT:    movq %rax, %rcx
-; X64-AVX-NEXT:    shrq %rcx
-; X64-AVX-NEXT:    andl $1, %eax
-; X64-AVX-NEXT:    orq %rcx, %rax
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm1, %xmm1
-; X64-AVX-NEXT:    vaddss %xmm1, %xmm1, %xmm1
-; X64-AVX-NEXT:  .LBB3_3:
-; X64-AVX-NEXT:    vmovq %xmm0, %rax
-; X64-AVX-NEXT:    testq %rax, %rax
-; X64-AVX-NEXT:    js .LBB3_4
-; X64-AVX-NEXT:  # BB#5:
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm2
-; X64-AVX-NEXT:    jmp .LBB3_6
-; X64-AVX-NEXT:  .LBB3_4:
-; X64-AVX-NEXT:    movq %rax, %rcx
-; X64-AVX-NEXT:    shrq %rcx
-; X64-AVX-NEXT:    andl $1, %eax
-; X64-AVX-NEXT:    orq %rcx, %rax
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm2, %xmm2
-; X64-AVX-NEXT:    vaddss %xmm2, %xmm2, %xmm2
-; X64-AVX-NEXT:  .LBB3_6:
-; X64-AVX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm2[0],xmm1[0],xmm2[2,3]
-; X64-AVX-NEXT:    vextractf128 $1, %ymm0, %xmm0
-; X64-AVX-NEXT:    vmovq %xmm0, %rax
-; X64-AVX-NEXT:    testq %rax, %rax
-; X64-AVX-NEXT:    js .LBB3_7
-; X64-AVX-NEXT:  # BB#8:
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm2
-; X64-AVX-NEXT:    jmp .LBB3_9
-; X64-AVX-NEXT:  .LBB3_7:
-; X64-AVX-NEXT:    movq %rax, %rcx
-; X64-AVX-NEXT:    shrq %rcx
-; X64-AVX-NEXT:    andl $1, %eax
-; X64-AVX-NEXT:    orq %rcx, %rax
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm2
-; X64-AVX-NEXT:    vaddss %xmm2, %xmm2, %xmm2
-; X64-AVX-NEXT:  .LBB3_9:
-; X64-AVX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0],xmm1[3]
-; X64-AVX-NEXT:    vpextrq $1, %xmm0, %rax
-; X64-AVX-NEXT:    testq %rax, %rax
-; X64-AVX-NEXT:    js .LBB3_10
-; X64-AVX-NEXT:  # BB#11:
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
-; X64-AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
-; X64-AVX-NEXT:    vzeroupper
-; X64-AVX-NEXT:    retq
-; X64-AVX-NEXT:  .LBB3_10:
-; X64-AVX-NEXT:    movq %rax, %rcx
-; X64-AVX-NEXT:    shrq %rcx
-; X64-AVX-NEXT:    andl $1, %eax
-; X64-AVX-NEXT:    orq %rcx, %rax
-; X64-AVX-NEXT:    vcvtsi2ssq %rax, %xmm3, %xmm0
-; X64-AVX-NEXT:    vaddss %xmm0, %xmm0, %xmm0
-; X64-AVX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; X64-AVX-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; X64-AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,2]
+; X64-AVX-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; X64-AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
+; X64-AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X64-AVX-NEXT:    vzeroupper
 ; X64-AVX-NEXT:    retq
   %and = and <4 x i64> %a, <i64 127, i64 255, i64 4095, i64 65535>
   %cvt = uitofp <4 x i64> %and to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <2 x double> @clamp_sitofp_2i64_2f64(<2 x i64> %a) nounwind {

test/CodeGen/X86/uint_to_fp-3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE
 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
 
 ;PR29079
 
 define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {
 ; X32-SSE-LABEL: mask_ucvt_4i32_4f32:
 ; X32-SSE:       # BB#0:
-; X32-SSE-NEXT:    pand {{\.LCPI.*}}, %xmm0
-; X32-SSE-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; X32-SSE-NEXT:    pand %xmm0, %xmm1
-; X32-SSE-NEXT:    por {{\.LCPI.*}}, %xmm1
-; X32-SSE-NEXT:    psrld $16, %xmm0
-; X32-SSE-NEXT:    por {{\.LCPI.*}}, %xmm0
-; X32-SSE-NEXT:    addps {{\.LCPI.*}}, %xmm0
-; X32-SSE-NEXT:    addps %xmm1, %xmm0
+; X32-SSE-NEXT:    andps {{\.LCPI.*}}, %xmm0
+; X32-SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; X32-SSE-NEXT:    retl
 ;
 ; X32-AVX-LABEL: mask_ucvt_4i32_4f32:
 ; X32-AVX:       # BB#0:
-; X32-AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
-; X32-AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X32-AVX-NEXT:    vaddps {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-AVX-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; X32-AVX-NEXT:    vandps {{\.LCPI.*}}, %xmm0, %xmm0
+; X32-AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X32-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: mask_ucvt_4i32_4f32:
 ; X64-SSE:       # BB#0:
-; X64-SSE-NEXT:    pand {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT:    movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; X64-SSE-NEXT:    pand %xmm0, %xmm1
-; X64-SSE-NEXT:    por {{.*}}(%rip), %xmm1
-; X64-SSE-NEXT:    psrld $16, %xmm0
-; X64-SSE-NEXT:    por {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT:    addps {{.*}}(%rip), %xmm0
-; X64-SSE-NEXT:    addps %xmm1, %xmm0
+; X64-SSE-NEXT:    andps {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX-LABEL: mask_ucvt_4i32_4f32:
 ; X64-AVX:       # BB#0:
-; X64-AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X64-AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
-; X64-AVX-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
-; X64-AVX-NEXT:    vaddps {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT:    vaddps %xmm0, %xmm1, %xmm0
+; X64-AVX-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
+; X64-AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
 ; X64-AVX-NEXT:    retq
   %and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
   %cvt = uitofp <4 x i32> %and to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
 ; X32-SSE-LABEL: mask_ucvt_4i32_4f64:
 ; X32-SSE:       # BB#0:
-; X32-SSE-NEXT:    movdqa %xmm0, %xmm2
-; X32-SSE-NEXT:    pand {{\.LCPI.*}}, %xmm2
-; X32-SSE-NEXT:    pxor %xmm3, %xmm3
-; X32-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
-; X32-SSE-NEXT:    movdqa {{.*#+}} xmm4 = [1127219200,1160773632,0,0]
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
-; X32-SSE-NEXT:    movapd {{.*#+}} xmm5 = [4.503600e+15,1.934281e+25]
-; X32-SSE-NEXT:    subpd %xmm5, %xmm0
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm0[2,3,0,1]
-; X32-SSE-NEXT:    addpd %xmm6, %xmm0
-; X32-SSE-NEXT:    xorpd %xmm6, %xmm6
-; X32-SSE-NEXT:    movss {{.*#+}} xmm6 = xmm1[0],xmm6[1,2,3]
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm6 = xmm6[0],xmm4[0],xmm6[1],xmm4[1]
-; X32-SSE-NEXT:    subpd %xmm5, %xmm6
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm6[2,3,0,1]
-; X32-SSE-NEXT:    addpd %xmm6, %xmm1
-; X32-SSE-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; X32-SSE-NEXT:    punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm3[2],xmm2[3],xmm3[3]
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm2[2,3,0,1]
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
-; X32-SSE-NEXT:    subpd %xmm5, %xmm2
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
-; X32-SSE-NEXT:    addpd %xmm2, %xmm1
-; X32-SSE-NEXT:    movss {{.*#+}} xmm3 = xmm6[0],xmm3[1,2,3]
-; X32-SSE-NEXT:    punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
-; X32-SSE-NEXT:    subpd %xmm5, %xmm3
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm3[2,3,0,1]
-; X32-SSE-NEXT:    addpd %xmm3, %xmm2
-; X32-SSE-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; X32-SSE-NEXT:    pand {{\.LCPI.*}}, %xmm0
+; X32-SSE-NEXT:    cvtdq2pd %xmm0, %xmm2
+; X32-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; X32-SSE-NEXT:    cvtdq2pd %xmm0, %xmm1
+; X32-SSE-NEXT:    movaps %xmm2, %xmm0
 ; X32-SSE-NEXT:    retl
 ;
 ; X32-AVX-LABEL: mask_ucvt_4i32_4f64:
 ; X32-AVX:       # BB#0:
-; X32-AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm0
-; X32-AVX-NEXT:    vpand {{\.LCPI.*}}, %xmm0, %xmm1
-; X32-AVX-NEXT:    vcvtdq2pd %xmm1, %ymm1
-; X32-AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X32-AVX-NEXT:    vandps {{\.LCPI.*}}, %xmm0, %xmm0
 ; X32-AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
-; X32-AVX-NEXT:    vmulpd {{\.LCPI.*}}, %ymm0, %ymm0
-; X32-AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; X32-AVX-NEXT:    retl
 ;
 ; X64-SSE-LABEL: mask_ucvt_4i32_4f64:
 ; X64-SSE:       # BB#0:
-; X64-SSE-NEXT:    movdqa %xmm0, %xmm2
-; X64-SSE-NEXT:    pand {{.*}}(%rip), %xmm2
-; X64-SSE-NEXT:    pxor %xmm1, %xmm1
-; X64-SSE-NEXT:    movdqa %xmm2, %xmm0
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
-; X64-SSE-NEXT:    movdqa {{.*#+}} xmm3 = [1127219200,1160773632,0,0]
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
-; X64-SSE-NEXT:    movapd {{.*#+}} xmm5 = [4.503600e+15,1.934281e+25]
-; X64-SSE-NEXT:    subpd %xmm5, %xmm0
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm0[2,3,0,1]
-; X64-SSE-NEXT:    addpd %xmm6, %xmm0
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
-; X64-SSE-NEXT:    subpd %xmm5, %xmm4
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm6 = xmm4[2,3,0,1]
-; X64-SSE-NEXT:    addpd %xmm4, %xmm6
-; X64-SSE-NEXT:    unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm6[0]
-; X64-SSE-NEXT:    punpckhdq {{.*#+}} xmm2 = xmm2[2],xmm1[2],xmm2[3],xmm1[3]
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm2[2,3,0,1]
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
-; X64-SSE-NEXT:    subpd %xmm5, %xmm2
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm2[2,3,0,1]
-; X64-SSE-NEXT:    addpd %xmm2, %xmm1
-; X64-SSE-NEXT:    punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
-; X64-SSE-NEXT:    subpd %xmm5, %xmm4
-; X64-SSE-NEXT:    pshufd {{.*#+}} xmm2 = xmm4[2,3,0,1]
-; X64-SSE-NEXT:    addpd %xmm4, %xmm2
-; X64-SSE-NEXT:    unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; X64-SSE-NEXT:    pand {{.*}}(%rip), %xmm0
+; X64-SSE-NEXT:    cvtdq2pd %xmm0, %xmm2
+; X64-SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
+; X64-SSE-NEXT:    cvtdq2pd %xmm0, %xmm1
+; X64-SSE-NEXT:    movaps %xmm2, %xmm0
 ; X64-SSE-NEXT:    retq
 ;
 ; X64-AVX-LABEL: mask_ucvt_4i32_4f64:
 ; X64-AVX:       # BB#0:
-; X64-AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
-; X64-AVX-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm1
-; X64-AVX-NEXT:    vcvtdq2pd %xmm1, %ymm1
-; X64-AVX-NEXT:    vpsrld $16, %xmm0, %xmm0
+; X64-AVX-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
 ; X64-AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
-; X64-AVX-NEXT:    vmulpd {{.*}}(%rip), %ymm0, %ymm0
-; X64-AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
 ; X64-AVX-NEXT:    retq
   %and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
   %cvt = uitofp <4 x i32> %and to <4 x double>
   ret <4 x double> %cvt
 }

test/CodeGen/X86/vec_int_to_fp.ll

 ; AVX2-NEXT:    vcvtdq2pd %xmm0, %ymm0
 ; AVX2-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_8i16_to_2f64:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512-NEXT:    vcvtudq2pd %ymm0, %zmm0
+; AVX512-NEXT:    vcvtdq2pd %ymm0, %zmm0
 ; AVX512-NEXT:    # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <8 x i16> %a to <8 x double>
   %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <2 x i32> <i32 0, i32 1>
   ret <2 x double> %shuf
 }
 
 define <2 x double> @uitofp_2i8_to_2f64(<16 x i8> %a) {

 ; AVX2-NEXT:    vcvtdq2pd %xmm0, %ymm0
 ; AVX2-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_16i8_to_2f64:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2pd %ymm0, %zmm0
+; AVX512-NEXT:    vcvtdq2pd %ymm0, %zmm0
 ; AVX512-NEXT:    # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <16 x i8> %a to <16 x double>
   %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <2 x i32> <i32 0, i32 1>
   ret <2 x double> %shuf
 }
 
 define <4 x double> @uitofp_4i64_to_4f64(<4 x i64> %a) {

 ; SSE-NEXT:    pxor %xmm1, %xmm1
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE-NEXT:    cvtdq2pd %xmm0, %xmm2
 ; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE-NEXT:    cvtdq2pd %xmm0, %xmm1
 ; SSE-NEXT:    movaps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_4i16_to_4f64:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; VEX-NEXT:    vcvtdq2pd %xmm0, %ymm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_4i16_to_4f64:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX512-NEXT:    vcvtudq2pd %xmm0, %ymm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_4i16_to_4f64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; AVX-NEXT:    retq
   %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %cvt = uitofp <4 x i16> %shuf to <4 x double>
   ret <4 x double> %cvt
 }
 
 define <4 x double> @uitofp_8i16_to_4f64(<8 x i16> %a) {
 ; SSE-LABEL: uitofp_8i16_to_4f64:
 ; SSE:       # BB#0:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX2-NEXT:    vcvtdq2pd %xmm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_8i16_to_4f64:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512-NEXT:    vcvtudq2pd %ymm0, %zmm0
+; AVX512-NEXT:    vcvtdq2pd %ymm0, %zmm0
 ; AVX512-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <8 x i16> %a to <8 x double>
   %shuf = shufflevector <8 x double> %cvt, <8 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %shuf
 }
 
 define <4 x double> @uitofp_4i8_to_4f64(<16 x i8> %a) {
 ; SSE-LABEL: uitofp_4i8_to_4f64:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pxor %xmm1, %xmm1
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE-NEXT:    cvtdq2pd %xmm0, %xmm2
 ; SSE-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
 ; SSE-NEXT:    cvtdq2pd %xmm0, %xmm1
 ; SSE-NEXT:    movaps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_4i8_to_4f64:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; VEX-NEXT:    vcvtdq2pd %xmm0, %ymm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_4i8_to_4f64:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2pd %xmm0, %ymm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_4i8_to_4f64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; AVX-NEXT:    retq
   %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %cvt = uitofp <4 x i8> %shuf to <4 x double>
   ret <4 x double> %cvt
 }
 
 define <4 x double> @uitofp_16i8_to_4f64(<16 x i8> %a) {
 ; SSE-LABEL: uitofp_16i8_to_4f64:
 ; SSE:       # BB#0:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
 ; AVX2-NEXT:    vcvtdq2pd %xmm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_16i8_to_4f64:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2pd %ymm0, %zmm0
+; AVX512-NEXT:    vcvtdq2pd %ymm0, %zmm0
 ; AVX512-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <16 x i8> %a to <16 x double>
   %shuf = shufflevector <16 x double> %cvt, <16 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x double> %shuf
 }
 
 ;

 define <4 x float> @uitofp_4i16_to_4f32(<8 x i16> %a) {
 ; SSE-LABEL: uitofp_4i16_to_4f32:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pxor %xmm1, %xmm1
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_4i16_to_4f32:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; VEX-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_4i16_to_4f32:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
-; AVX512-NEXT:    vcvtudq2ps %xmm0, %xmm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_4i16_to_4f32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    retq
   %shuf = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %cvt = uitofp <4 x i16> %shuf to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <4 x float> @uitofp_8i16_to_4f32(<8 x i16> %a) {
 ; SSE-LABEL: uitofp_8i16_to_4f32:
 ; SSE:       # BB#0:

 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_8i16_to_4f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512-NEXT:    vcvtudq2ps %ymm0, %ymm0
+; AVX512-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX512-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <8 x i16> %a to <8 x float>
   %shuf = shufflevector <8 x float> %cvt, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %shuf
 }
 
 define <4 x float> @uitofp_4i8_to_4f32(<16 x i8> %a) {
 ; SSE-LABEL: uitofp_4i8_to_4f32:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    pxor %xmm1, %xmm1
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_4i8_to_4f32:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; VEX-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_4i8_to_4f32:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2ps %xmm0, %xmm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_4i8_to_4f32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    retq
   %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   %cvt = uitofp <4 x i8> %shuf to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <4 x float> @uitofp_16i8_to_4f32(<16 x i8> %a) {
 ; SSE-LABEL: uitofp_16i8_to_4f32:
 ; SSE:       # BB#0:

 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    # kill: %XMM0<def> %XMM0<kill> %YMM0<kill>
 ; AVX2-NEXT:    vzeroupper
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_16i8_to_4f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2ps %zmm0, %zmm0
+; AVX512-NEXT:    vcvtdq2ps %zmm0, %zmm0
 ; AVX512-NEXT:    # kill: %XMM0<def> %XMM0<kill> %ZMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <16 x i8> %a to <16 x float>
   %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %shuf
 }
 
 define <4 x float> @uitofp_4i64_to_4f32(<4 x i64> %a) {

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_8i16_to_8f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
-; AVX512-NEXT:    vcvtudq2ps %ymm0, %ymm0
+; AVX512-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX512-NEXT:    retq
   %cvt = uitofp <8 x i16> %a to <8 x float>
   ret <8 x float> %cvt
 }
 
 define <8 x float> @uitofp_8i8_to_8f32(<16 x i8> %a) {
 ; SSE-LABEL: uitofp_8i8_to_8f32:
 ; SSE:       # BB#0:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_8i8_to_8f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2ps %ymm0, %ymm0
+; AVX512-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX512-NEXT:    retq
   %shuf = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   %cvt = uitofp <8 x i8> %shuf to <8 x float>
   ret <8 x float> %cvt
 }
 
 define <8 x float> @uitofp_16i8_to_8f32(<16 x i8> %a) {
 ; SSE-LABEL: uitofp_16i8_to_8f32:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_16i8_to_8f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2ps %zmm0, %zmm0
+; AVX512-NEXT:    vcvtdq2ps %zmm0, %zmm0
 ; AVX512-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<kill>
 ; AVX512-NEXT:    retq
   %cvt = uitofp <16 x i8> %a to <16 x float>
   %shuf = shufflevector <16 x float> %cvt, <16 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x float> %shuf
 }
 
 ;

 ; SSE-NEXT:    movq {{.*#+}} xmm1 = mem[0],zero
 ; SSE-NEXT:    pxor %xmm0, %xmm0
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
 ; SSE-NEXT:    cvtdq2pd %xmm1, %xmm0
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    cvtdq2pd %xmm1, %xmm1
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_load_4i16_to_4f64:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; VEX-NEXT:    vcvtdq2pd %xmm0, %ymm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_load_4i16_to_4f64:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; AVX512-NEXT:    vcvtudq2pd %xmm0, %ymm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_load_4i16_to_4f64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; AVX-NEXT:    retq
   %ld = load <4 x i16>, <4 x i16> *%a
   %cvt = uitofp <4 x i16> %ld to <4 x double>
   ret <4 x double> %cvt
 }
 
 define <4 x double> @uitofp_load_4i8_to_4f64(<4 x i8> *%a) {
 ; SSE-LABEL: uitofp_load_4i8_to_4f64:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
 ; SSE-NEXT:    pxor %xmm0, %xmm0
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
 ; SSE-NEXT:    cvtdq2pd %xmm1, %xmm0
 ; SSE-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
 ; SSE-NEXT:    cvtdq2pd %xmm1, %xmm1
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_load_4i8_to_4f64:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; VEX-NEXT:    vcvtdq2pd %xmm0, %ymm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_load_4i8_to_4f64:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2pd %xmm0, %ymm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_load_4i8_to_4f64:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX-NEXT:    vcvtdq2pd %xmm0, %ymm0
+; AVX-NEXT:    retq
   %ld = load <4 x i8>, <4 x i8> *%a
   %cvt = uitofp <4 x i8> %ld to <4 x double>
   ret <4 x double> %cvt
 }
 
 ;
 ; Load Signed Integer to Float
 ;

 ; SSE-LABEL: uitofp_load_4i16_to_4f32:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
 ; SSE-NEXT:    pxor %xmm1, %xmm1
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_load_4i16_to_4f32:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; VEX-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_load_4i16_to_4f32:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
-; AVX512-NEXT:    vcvtudq2ps %xmm0, %xmm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_load_4i16_to_4f32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    retq
   %ld = load <4 x i16>, <4 x i16> *%a
   %cvt = uitofp <4 x i16> %ld to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <4 x float> @uitofp_load_4i8_to_4f32(<4 x i8> *%a) {
 ; SSE-LABEL: uitofp_load_4i8_to_4f32:
 ; SSE:       # BB#0:
 ; SSE-NEXT:    movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; SSE-NEXT:    pxor %xmm1, %xmm1
 ; SSE-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
 ; SSE-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; SSE-NEXT:    cvtdq2ps %xmm0, %xmm0
 ; SSE-NEXT:    retq
 ;
-; VEX-LABEL: uitofp_load_4i8_to_4f32:
-; VEX:       # BB#0:
-; VEX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; VEX-NEXT:    vcvtdq2ps %xmm0, %xmm0
-; VEX-NEXT:    retq
-;
-; AVX512-LABEL: uitofp_load_4i8_to_4f32:
-; AVX512:       # BB#0:
-; AVX512-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2ps %xmm0, %xmm0
-; AVX512-NEXT:    retq
+; AVX-LABEL: uitofp_load_4i8_to_4f32:
+; AVX:       # BB#0:
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    retq
   %ld = load <4 x i8>, <4 x i8> *%a
   %cvt = uitofp <4 x i8> %ld to <4 x float>
   ret <4 x float> %cvt
 }
 
 define <8 x float> @uitofp_load_8i64_to_8f32(<8 x i64> *%a) {
 ; SSE-LABEL: uitofp_load_8i64_to_8f32:
 ; SSE:       # BB#0:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_load_8i16_to_8f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxwd {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero
-; AVX512-NEXT:    vcvtudq2ps %ymm0, %ymm0
+; AVX512-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX512-NEXT:    retq
   %ld = load <8 x i16>, <8 x i16> *%a
   %cvt = uitofp <8 x i16> %ld to <8 x float>
   ret <8 x float> %cvt
 }
 
 define <8 x float> @uitofp_load_8i8_to_8f32(<8 x i8> *%a) {
 ; SSE-LABEL: uitofp_load_8i8_to_8f32:

 ; AVX2:       # BB#0:
 ; AVX2-NEXT:    vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
 ; AVX2-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: uitofp_load_8i8_to_8f32:
 ; AVX512:       # BB#0:
 ; AVX512-NEXT:    vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
-; AVX512-NEXT:    vcvtudq2ps %ymm0, %ymm0
+; AVX512-NEXT:    vcvtdq2ps %ymm0, %ymm0
 ; AVX512-NEXT:    retq
   %ld = load <8 x i8>, <8 x i8> *%a
   %cvt = uitofp <8 x i8> %ld to <8 x float>
   ret <8 x float> %cvt
 }
 
 ;
 ; Aggregates