[AMDGPU] Assembler: match e32 VOP instruction before e64.

[SamWot]

Summary

Split assembler match table in 4 tables with assembler variants:

• Default - all instructions except VOP3, SDWA and DPP
• VOP3
• SDWA
• DPP

First match Default table then VOP3, SDWA and DPP.

Depends on D24249

[• tstellarAMD]

This is a very nice solution for this problem. LGTM.

[artem.tamazov]

Good.

[vpykhtin]

LGTM.

llvm/trunk/lib/Target/AMDGPU/AMDGPU.td

 }
 
 def AMDGPUAsmParser : AsmParser {
   // Some of the R600 registers have the same name, so this crashes.
   // For example T0_XYZW and T0_XY both have the asm name T0.
   let ShouldEmitMatchRegisterName = 0;
 }
 
+def AMDGPUAsmVariants {
+  string Default = "Default";
+  int Default_ID = 0;
+  string VOP3 = "VOP3";
+  int VOP3_ID = 1;
+  string SDWA = "SDWA";
+  int SDWA_ID = 2;
+  string DPP = "DPP";
+  int DPP_ID = 3;
+}
+
+def DefaultAMDGPUAsmParserVariant : AsmParserVariant {
+  let Variant = AMDGPUAsmVariants.Default_ID;
+  let Name = AMDGPUAsmVariants.Default;
+}
+
+def VOP3AsmParserVariant : AsmParserVariant {
+  let Variant = AMDGPUAsmVariants.VOP3_ID;
+  let Name = AMDGPUAsmVariants.VOP3;
+}
+
+def SDWAAsmParserVariant : AsmParserVariant {
+  let Variant = AMDGPUAsmVariants.SDWA_ID;
+  let Name = AMDGPUAsmVariants.SDWA;
+}
+
+def DPPAsmParserVariant : AsmParserVariant {
+  let Variant = AMDGPUAsmVariants.DPP_ID;
+  let Name = AMDGPUAsmVariants.DPP;
+}
+
 def AMDGPU : Target {
   // Pull in Instruction Info:
   let InstructionSet = AMDGPUInstrInfo;
   let AssemblyParsers = [AMDGPUAsmParser];
+  let AssemblyParserVariants = [DefaultAMDGPUAsmParserVariant,
+                                VOP3AsmParserVariant,
+                                SDWAAsmParserVariant,
+                                DPPAsmParserVariant];
 }
 
 // Dummy Instruction itineraries for pseudo instructions
 def ALU_NULL : FuncUnit;
 def NullALU : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Predicate helper class

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
   return Match_Success;
 }
 
 bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                               OperandVector &Operands,
                                               MCStreamer &Out,
                                               uint64_t &ErrorInfo,
                                               bool MatchingInlineAsm) {
+  // What asm variants we should check
+  std::vector<unsigned> MatchedVariants;
+  if (getForcedEncodingSize() == 32) {
+    MatchedVariants = {AMDGPUAsmVariants::DEFAULT};
+  } else if (isForcedVOP3()) {
+    MatchedVariants = {AMDGPUAsmVariants::VOP3};
+  } else if (isForcedSDWA()) {
+    MatchedVariants = {AMDGPUAsmVariants::SDWA};
+  } else if (isForcedDPP()) {
+    MatchedVariants = {AMDGPUAsmVariants::DPP};
+  } else {
+    MatchedVariants = {AMDGPUAsmVariants::DEFAULT,
+                       AMDGPUAsmVariants::VOP3,
+                       AMDGPUAsmVariants::SDWA,
+                       AMDGPUAsmVariants::DPP};
+  }
+
   MCInst Inst;
+  unsigned Result = Match_Success;
+  for (auto Variant : MatchedVariants) {
+    uint64_t EI;
+    auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
+                                  Variant);
+    // We order match statuses from least to most specific. We use most specific
+    // status as resulting
+    // Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32
+    if ((R == Match_Success) ||
+        (R == Match_PreferE32) ||
+        (R == Match_MissingFeature && Result != Match_PreferE32) ||
+        (R == Match_InvalidOperand && Result != Match_MissingFeature
+                                   && Result != Match_PreferE32) ||
+        (R == Match_MnemonicFail   && Result != Match_InvalidOperand
+                                   && Result != Match_MissingFeature
+                                   && Result != Match_PreferE32)) {
+      Result = R;
+      ErrorInfo = EI;
+    }
+    if (R == Match_Success)
+      break;
+  }
 
-  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
-    default: break;
-    case Match_Success:
-      Inst.setLoc(IDLoc);
-      Out.EmitInstruction(Inst, getSTI());
-      return false;
-    case Match_MissingFeature:
-      return Error(IDLoc, "instruction not supported on this GPU");
+  switch (Result) {
+
 
-    case Match_MnemonicFail:
-      return Error(IDLoc, "unrecognized instruction mnemonic");
 
-    case Match_InvalidOperand: {
-      SMLoc ErrorLoc = IDLoc;
-      if (ErrorInfo != ~0ULL) {
-        if (ErrorInfo >= Operands.size()) {
-          return Error(IDLoc, "too few operands for instruction");
-        }
-        ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
-        if (ErrorLoc == SMLoc())
-          ErrorLoc = IDLoc;
-      }
-      return Error(ErrorLoc, "invalid operand for instruction");
-    }
-    case Match_PreferE32:
-      return Error(IDLoc, "internal error: instruction without _e64 suffix "
-                          "should be encoded as e32");
+
   }
   llvm_unreachable("Implement any new match types added!");
 }
 
 bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
                                                uint32_t &Minor) {
   if (getLexer().isNot(AsmToken::Integer))
     return TokError("invalid major version");

llvm/trunk/lib/Target/AMDGPU/SIDefines.h

namespace SIOutMods {
   enum {
     NONE = 0,
     MUL2 = 1,
     MUL4 = 2,
     DIV2 = 3
   };
 }
 
+namespace AMDGPUAsmVariants {
+  enum {
+    DEFAULT = 0,
+    VOP3 = 1,
+    SDWA = 2,
+    DPP = 3
+  };
+}
+
 namespace llvm {
 namespace AMDGPU {
 namespace EncValues { // Encoding values of enum9/8/7 operands
 
 enum {
   SGPR_MIN = 0,
   SGPR_MAX = 101,
   TTMP_MIN = 112,

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm = "",
 
   let SchedRW = [Write32Bit];
 
   field bits<1> DisableSIDecoder = 0;
   field bits<1> DisableVIDecoder = 0;
   field bits<1> DisableDecoder = 0;
 
   let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
+  let AsmVariantName = AMDGPUAsmVariants.Default;
 }
 
 class PseudoInstSI<dag outs, dag ins, list<dag> pattern = []>
   : InstSI<outs, ins, "", pattern> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
class VOP3Common <dag outs, dag ins, string asm = "",
   let VOP3 = 1;
   let VALU = 1;
 
   let AsmMatchConverter =
     !if(!eq(VOP3Only,1),
         "cvtVOP3",
         !if(!eq(HasMods,1), "cvtVOP3_2_mod", ""));
 
+  let AsmVariantName = AMDGPUAsmVariants.VOP3;
+
   let isCodeGenOnly = 0;
 
   int Size = 8;
 
   // Because SGPRs may be allowed if there are multiple operands, we
   // need a post-isel hook to insert copies in order to avoid
   // violating constant bus requirements.
   let hasPostISelHook = 1;

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

 }
 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
 def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
 def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
 
 // This class is used only with VOPC instructions. Use $sdst for out operand
-class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
+class SIInstAlias <string asm, Instruction inst, VOPProfile p,
+                   string VariantName = ""> :
     InstAlias <asm, (inst)>, PredicateControl {
 
   field bit isCompare;
   field bit isCommutable;
 
   let ResultInst =
     !if (p.HasDst32,
       !if (!eq(p.NumSrcArgs, 0),
// else
         // 0 dst, 2 src
         (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
       !if (!eq(p.NumSrcArgs, 1),
         // 0 dst, 1 src
         (inst p.Src0RC32:$src1),
       // else
         // 0 dst, 0 src
         (inst))));
+
+    let AsmVariantName = VariantName;
 }
 
-class SIInstAliasSI <string asm, string op_name, VOPProfile p> :
-  SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_si"), p> {
+class SIInstAliasSI <string asm, string op_name, VOPProfile p, string VariantName = ""> :
+  SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_si"), p, VariantName> {
   let AssemblerPredicate = SIAssemblerPredicate;
 }
 
-class SIInstAliasVI <string asm, string op_name, VOPProfile p> :
-  SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_vi"), p> {
+class SIInstAliasVI <string asm, string op_name, VOPProfile p, string VariantName = ""> :
+  SIInstAlias <asm, !cast<Instruction>(op_name#"_e32_vi"), p, VariantName> {
   let AssemblerPredicates = [isVI];
 }
 
-multiclass SIInstAliasBuilder <string asm, VOPProfile p> {
+multiclass SIInstAliasBuilder <string asm, VOPProfile p, string VariantName = ""> {
 
-  def : SIInstAliasSI <asm, NAME, p>;
+  def : SIInstAliasSI <asm, NAME, p, VariantName>;
 
-  def : SIInstAliasVI <asm, NAME, p>;
+  def : SIInstAliasVI <asm, NAME, p, VariantName>;
 }
 
 class VOP <string opName> {
   string OpName = opName;
 }
 
 class VOP2_REV <string revOp, bit isOrig> {
   string RevOp = revOp;
def _vi : VOPC<op.VI, ins, asm, []>,
       let isConvergent = DefExec;
       let SchedRW = sched;
       let DecoderNamespace = "VI";
       let DisableDecoder = DisableVIDecoder;
     }
 
   } // End AssemblerPredicates = [isVI]
 
-  defm : SIInstAliasBuilder<alias_asm, p>;
+  defm : SIInstAliasBuilder<alias_asm, p, AMDGPUAsmVariants.Default>;
 }
 
 multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
                         list<dag> pat64, bit DefExec, string revOp,
                         VOPProfile p, list<SchedReadWrite> sched> {
   defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched,
                       revOp>;
 

llvm/trunk/lib/Target/AMDGPU/VIInstrFormats.td

 }
 
 class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
     VOPAnyCommon <outs, ins, asm, pattern> {
   let DPP = 1;
   let Size = 8;
 
   let AsmMatchConverter = !if(!eq(HasMods,1), "cvtDPP", "");
+  let AsmVariantName = AMDGPUAsmVariants.DPP;
 }
 
 class VOP_DPPe : Enc64 {
   bits<2> src0_modifiers;
   bits<8> src0;
   bits<2> src1_modifiers;
   bits<9> dpp_ctrl;
   bits<1> bound_ctrl;
class VOP2_DPPe <bits<6> op> : VOP_DPPe {
   let Inst{30-25} = op;
   let Inst{31} = 0x0; //encoding
 }
 
 class VOP_SDWA <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
     VOPAnyCommon <outs, ins, asm, pattern> {
   let SDWA = 1;
   let Size = 8;
+  let AsmVariantName = AMDGPUAsmVariants.SDWA;
 }
 
 class VOP_SDWAe : Enc64 {
   bits<8> src0;
   bits<3> src0_sel;
   bits<2> src0_fmodifiers; // {abs,neg}
   bits<1> src0_imodifiers; // sext
   bits<3> src1_sel;

llvm/trunk/lib/Target/AMDGPU/VIInstructions.td

 // Aliases to simplify matching of floating-point instructions that
 // are VOP2 on SI and VOP3 on VI.
 
 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
   name#" $dst, $src0, $src1",
   (inst VGPR_32:$dst, 0, VCSrc_32:$src0, 0, VCSrc_32:$src1, 0, 0)
 >, PredicateControl {
   let UseInstAsmMatchConverter = 0;
+  let AsmVariantName = AMDGPUAsmVariants.VOP3;
 }
 
 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;