[TableGen] AsmMatcher: Add AsmVariantName to Instruction class.

[SamWot]

Summary

This allows specifying instructions that are available only in specific assembler variant. If AsmVariantName is specified then instruction will be presented only in MatchTable for this variant. If not specified then assembler variants will be determined based on AsmString.
Also this allows splitting assembler match tables in same way as it is done in dissasembler.

[• tstellarAMD]

utils/TableGen/AsmMatcherEmitter.cpp

1487 ↗

(On Diff #70381)

I think this should be a StringRef.

1519 ↗

(On Diff #70381)

Same Here.

[SamWot]

utils/TableGen/AsmMatcherEmitter.cpp

1487 ↗

(On Diff #70381)

It's unsafe here. getValueAsString() method return std::string by value. StringRef will point to free memory.

[SamWot]

ping

[• tstellarAMD]

LGTM.

[vpykhtin]

LGTM, but add the test first.

[SamWot]

Added tests

[vpykhtin]

LGTM.

llvm/trunk/include/llvm/Target/Target.td

class Instruction {
 
   /// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
   /// two-operand matcher inst-alias for a three operand instruction.
   /// For example, the arm instruction "add r3, r3, r5" can be written
   /// as "add r3, r5". The constraint is of the same form as a tied-operand
   /// constraint. For example, "$Rn = $Rd".
   string TwoOperandAliasConstraint = "";
 
+  /// Assembler variant name to use for this instruction. If specified then
+  /// instruction will be presented only in MatchTable for this variant. If
+  /// not specified then assembler variants will be determined based on
+  /// AsmString
+  string AsmVariantName = "";
+
   ///@}
 
   /// UseNamedOperandTable - If set, the operand indices of this instruction
   /// can be queried via the getNamedOperandIdx() function which is generated
   /// by TableGen.
   bit UseNamedOperandTable = 0;
 }
 
class InstAlias<string Asm, dag Result, int Emit = 1> {
   // If the instruction specified in Result has defined an AsmMatchConverter
   // then setting this to 1 will cause the alias to use the AsmMatchConverter
   // function when converting the OperandVector into an MCInst instead of the
   // function that is generated by the dag Result.
   // Setting this to 0 will cause the alias to ignore the Result instruction's
   // defined AsmMatchConverter and instead use the function generated by the
   // dag Result.
   bit UseInstAsmMatchConverter = 1;
+
+  // Assembler variant name to use for this alias. If not specified then
+  // assembler variants will be determined based on AsmString
+  string AsmVariantName = "";
 }
 
 //===----------------------------------------------------------------------===//
 // AsmWriter - This class can be implemented by targets that need to customize
 // the format of the .s file writer.
 //
 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
 // on X86 for example).

llvm/trunk/test/TableGen/AsmVariant.td

+// RUN: llvm-tblgen -gen-asm-matcher -I %p/../../include %s | FileCheck %s
+
+// Check that cpecifying AsmVariant works correctly
+
+include "llvm/Target/Target.td"
+
+def ArchInstrInfo : InstrInfo { }
+
+def FooAsmParserVariant : AsmParserVariant {
+  let Variant = 0;
+  let Name = "Foo";
+}
+
+def BarAsmParserVariant : AsmParserVariant {
+  let Variant = 1;
+  let Name = "Bar";
+}
+
+def Arch : Target {
+  let InstructionSet = ArchInstrInfo;
+  let AssemblyParserVariants = [FooAsmParserVariant, BarAsmParserVariant];
+}
+
+def Reg : Register<"reg">;
+
+def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
+
+def foo : Instruction {
+  let Size = 2;
+  let OutOperandList = (outs);
+  let InOperandList = (ins);
+  let AsmString = "foo";
+  let AsmVariantName = "Foo";
+}
+
+def BarAlias : InstAlias<"bar", (foo)> {
+  string AsmVariantName = "Bar";
+}
+
+// CHECK: static const MatchEntry MatchTable0[] = {
+// CHECK-NEXT: /* foo */, Arch::foo
+// CHECK-NEXT: };
+
+// CHECK: static const MatchEntry MatchTable1[] = {
+// CHECK-NEXT: /* bar */, Arch::foo
+// CHECK-NEXT: };

llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp

 };
 
 class AsmVariantInfo {
 public:
   std::string RegisterPrefix;
   std::string TokenizingCharacters;
   std::string SeparatorCharacters;
   std::string BreakCharacters;
+  std::string Name;
   int AsmVariantNo;
 };
 
 /// MatchableInfo - Helper class for storing the necessary information for an
 /// instruction or alias which is capable of being matched.
 struct MatchableInfo {
   struct AsmOperand {
     /// Token - This is the token that the operand came from.
for (unsigned VC = 0; VC != VariantCount; ++VC) {
     AsmVariantInfo Variant;
     Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
     Variant.TokenizingCharacters =
         AsmVariant->getValueAsString("TokenizingCharacters");
     Variant.SeparatorCharacters =
         AsmVariant->getValueAsString("SeparatorCharacters");
     Variant.BreakCharacters =
         AsmVariant->getValueAsString("BreakCharacters");
+    Variant.Name = AsmVariant->getValueAsString("Name");
     Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
 
     for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
 
       // If the tblgen -match-prefix option is specified (for tblgen hackers),
       // filter the set of instructions we consider.
       if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
         continue;
 
       // Ignore "codegen only" instructions.
       if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
         continue;
 
+      // Ignore instructions for different instructions
+      const std::string V = CGI->TheDef->getValueAsString("AsmVariantName");
+      if (!V.empty() && V != Variant.Name)
+        continue;
+
       auto II = llvm::make_unique<MatchableInfo>(*CGI);
 
       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
 
       // Ignore instructions which shouldn't be matched and diagnose invalid
       // instruction definitions with an error.
       if (!II->validate(CommentDelimiter, true))
         continue;
for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
 
       // If the tblgen -match-prefix option is specified (for tblgen hackers),
       // filter the set of instruction aliases we consider, based on the target
       // instruction.
       if (!StringRef(Alias->ResultInst->TheDef->getName())
             .startswith( MatchPrefix))
         continue;
 
+      const std::string V = Alias->TheDef->getValueAsString("AsmVariantName");
+      if (!V.empty() && V != Variant.Name)
+        continue;
+
       auto II = llvm::make_unique<MatchableInfo>(std::move(Alias));
 
       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
 
       // Validate the alias definitions.
       II->validate(CommentDelimiter, false);
 
       Matchables.push_back(std::move(II));