This is an archive of the discontinued LLVM Phabricator instance.

Differential D23617

[AMDGPU ]Refactor SOP instruction definitions.
ClosedPublic

Authored by vpykhtin on Aug 17 2016, 11:33 AM.

Details

Reviewers
artem.tamazov
• tstellarAMD
arsenm
SamWot
Commits
rGa34fb49f8f9a: [AMDGPU] Refactor SOP instructions TD files.
rL280101: [AMDGPU] Refactor SOP instructions TD files.
Summary

This change factors out SOP instructions in the same way as previously DS instructions were done.

Diff Detail

Repository
rL LLVM

Event Timeline

vpykhtin updated this revision to Diff 68389.Aug 17 2016, 11:33 AM
vpykhtin retitled this revision from to [AMDGPU ]Refactor SOx instruction definitions..
vpykhtin updated this object.
vpykhtin added reviewers: • tstellarAMD, arsenm, SamWot, artem.tamazov.
vpykhtin set the repository for this revision to rL LLVM.
vpykhtin added a project: Restricted Project.
vpykhtin added a subscriber: nhaustov.
Herald added subscribers: kzhuravl, arsenm. · View Herald TranscriptAug 17 2016, 11:33 AM
arsenm added a subscriber: llvm-commits.Aug 17 2016, 11:36 AM
arsenm added inline comments.
lib/Target/AMDGPU/SOxInstructions.td
1 ↗(On Diff #68389)

s/SOx/SOP

SamWot accepted this revision.Aug 18 2016, 7:43 AM
SamWot edited edge metadata.
This revision is now accepted and ready to land.Aug 18 2016, 7:43 AM
vpykhtin updated this revision to Diff 69024.Aug 23 2016, 12:16 PM
vpykhtin retitled this revision from [AMDGPU ]Refactor SOx instruction definitions. to [AMDGPU ]Refactor SOP instruction definitions..
vpykhtin updated this object.
vpykhtin edited edge metadata.
vpykhtin removed rL LLVM as the repository for this revision.

s/SOx/SOP done.

Lit failures fixed.

Tom, can you please run additional testing on this?

vpykhtin added a comment.Aug 25 2016, 3:04 AM

ping

artem.tamazov accepted this revision.Aug 25 2016, 6:37 AM
artem.tamazov edited edge metadata.

LGTM

arsenm added inline comments.Aug 25 2016, 10:16 AM
lib/Target/AMDGPU/SOPInstructions.td
83 ↗(On Diff #69024)

{ on previous line, same everywhere else

97–98 ↗(On Diff #69024)

Can you remove the extra spaces between all the instructions and the :

• tstellarAMD accepted this revision.Aug 29 2016, 7:59 AM
• tstellarAMD edited edge metadata.

Tests pass. LGTM.

Closed by commit rL280101: [AMDGPU] Refactor SOP instructions TD files. (authored by vpykhtin). · Explain WhyAug 30 2016, 8:29 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
126 lines
287 lines
503 lines
1103 lines

Diff 69693

llvm/trunk/lib/Target/AMDGPU/SIInstrFormats.td

Show First 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
} }
} // End Uses = [EXEC] } // End Uses = [EXEC]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar operations // Scalar operations
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SOP1e <bits<8> op> : Enc32 {
bits<7> sdst;
bits<8> src0;
let Inst{7-0} = src0;
let Inst{15-8} = op;
let Inst{22-16} = sdst;
let Inst{31-23} = 0x17d; //encoding;
}
class SOP2e <bits<7> op> : Enc32 {
bits<7> sdst;
bits<8> src0;
bits<8> src1;
let Inst{7-0} = src0;
let Inst{15-8} = src1;
let Inst{22-16} = sdst;
let Inst{29-23} = op;
let Inst{31-30} = 0x2; // encoding
}
class SOPCe <bits<7> op> : Enc32 {
bits<8> src0;
bits<8> src1;
let Inst{7-0} = src0;
let Inst{15-8} = src1;
let Inst{22-16} = op;
let Inst{31-23} = 0x17e;
}
class SOPKe <bits<5> op> : Enc32 {
bits <7> sdst;
bits <16> simm16;
let Inst{15-0} = simm16;
let Inst{22-16} = sdst;
let Inst{27-23} = op;
let Inst{31-28} = 0xb; //encoding
}
class SOPK64e <bits<5> op> : Enc64 {
bits <7> sdst = 0;
bits <16> simm16;
bits <32> imm;
let Inst{15-0} = simm16;
let Inst{22-16} = sdst;
let Inst{27-23} = op;
let Inst{31-28} = 0xb;
let Inst{63-32} = imm;
}
class SOPPe <bits<7> op> : Enc32 {
bits <16> simm16;
let Inst{15-0} = simm16;
let Inst{22-16} = op;
let Inst{31-23} = 0x17f; // encoding
}
class SMRDe <bits<5> op, bits<1> imm> : Enc32 { class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
bits<7> sdst; bits<7> sdst;
bits<7> sbase; bits<7> sbase;
let Inst{8} = imm; let Inst{8} = imm;
let Inst{14-9} = sbase{6-1}; let Inst{14-9} = sbase{6-1};
let Inst{21-15} = sdst; let Inst{21-15} = sdst;
let Inst{26-22} = op; let Inst{26-22} = op;
Show All 21 Linesclass SMRD_IMMe_ci <bits<5> op> : Enc64 {
let Inst{8} = 0; let Inst{8} = 0;
let Inst{14-9} = sbase{6-1}; let Inst{14-9} = sbase{6-1};
let Inst{21-15} = sdst; let Inst{21-15} = sdst;
let Inst{26-22} = op; let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding let Inst{31-27} = 0x18; //encoding
let Inst{63-32} = offset; let Inst{63-32} = offset;
} }
let SchedRW = [WriteSALU] in {
class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let isCodeGenOnly = 0;
let SALU = 1;
let SOP1 = 1;
}
class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let isCodeGenOnly = 0;
let SALU = 1;
let SOP2 = 1;
let UseNamedOperandTable = 1;
}
class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern>, SOPCe <op> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPC = 1;
let isCodeGenOnly = 0;
let Defs = [SCC];
let UseNamedOperandTable = 1;
}
class SOPK <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins , asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPK = 1;
let UseNamedOperandTable = 1;
}
class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPP = 1;
let UseNamedOperandTable = 1;
}
} // let SchedRW = [WriteSALU]
class SMRD <dag outs, dag ins, string asm, list<dag> pattern> : class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern> { InstSI<outs, ins, asm, pattern> {
let LGKM_CNT = 1; let LGKM_CNT = 1;
let SMRD = 1; let SMRD = 1;
let mayStore = 0; let mayStore = 0;
let mayLoad = 1; let mayLoad = 1;
▲ Show 20 Lines • Show All 351 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesclass vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
let VI3 = vi; let VI3 = vi;
} }
class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop { class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
let SI3 = si; let SI3 = si;
let VI3 = vi; let VI3 = vi;
} }
class sop1 <bits<8> si, bits<8> vi = si> {
field bits<8> SI = si;
field bits<8> VI = vi;
}
class sop2 <bits<7> si, bits<7> vi = si> {
field bits<7> SI = si;
field bits<7> VI = vi;
}
class sopk <bits<5> si, bits<5> vi = si> {
field bits<5> SI = si;
field bits<5> VI = vi;
}
class dsop <bits<8> si, bits<8> vi = si> {
field bits<8> SI = si;
field bits<8> VI = vi;
}
// Specify an SMRD opcode for SI and SMEM opcode for VI // Specify an SMRD opcode for SI and SMEM opcode for VI
// FIXME: This should really be bits<5> si, Tablegen crashes if // FIXME: This should really be bits<5> si, Tablegen crashes if
// parameter default value is other parameter with different bit size // parameter default value is other parameter with different bit size
class smrd<bits<8> si, bits<8> vi = si> { class smrd<bits<8> si, bits<8> vi = si> {
field bits<5> SI = si{4-0}; field bits<5> SI = si{4-0};
field bits<8> VI = vi; field bits<8> VI = vi;
} }
▲ Show 20 Lines • Show All 574 Lines • ▼ Show 20 Lines def _vi : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.VI>, EXPe_vi {
let DisableDecoder = DisableVIDecoder; let DisableDecoder = DisableVIDecoder;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar classes // Scalar classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SOP1 <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
SOP1 <outs, ins, asm, []>,
SOP1e <op.SI>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let isCodeGenOnly = 0;
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
SOP1 <outs, ins, asm, []>,
SOP1e <op.VI>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let isCodeGenOnly = 0;
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
list<dag> pattern> {
def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
def _vi : SOP1_Real_vi <op, opName, outs, ins, asm>;
}
multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0),
opName#" $sdst, $src0", pattern
>;
multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0),
opName#" $sdst, $src0", pattern
>;
// no input, 64-bit output.
multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
def "" : SOP1_Pseudo <opName, (outs SReg_64:$sdst), (ins), pattern>;
def _si : SOP1_Real_si <op, opName, (outs SReg_64:$sdst), (ins),
opName#" $sdst"> {
let src0 = 0;
}
def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$sdst), (ins),
opName#" $sdst"> {
let src0 = 0;
}
}
// 64-bit input, no output
multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
opName#" $src0"> {
let sdst = 0;
}
def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
opName#" $src0"> {
let sdst = 0;
}
}
// 64-bit input, 32-bit output.
multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_32:$sdst), (ins SSrc_64:$src0),
opName#" $sdst, $src0", pattern
>;
// 32-bit input, 64-bit output.
multiclass SOP1_64_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0),
opName#" $sdst, $src0", pattern
>;
class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
SOP2<outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let Size = 4;
// Pseudo instructions have no encodings, but adding this field here allows
// us to do:
// let sdst = xxx in {
// for multiclasses that include both real and pseudo instructions.
field bits<7> sdst = 0;
}
class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
SOP2<outs, ins, asm, []>,
SOP2e<op.SI>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
SOP2<outs, ins, asm, []>,
SOP2e<op.VI>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
list<dag> pattern> {
def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
def _vi : SOP2_Real_vi <op, opName, outs, ins, asm>;
}
multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
opName#" $sdst, $src0, $src1", pattern
>;
multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_64:$src1),
opName#" $sdst, $src0, $src1", pattern
>;
multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_32:$src1),
opName#" $sdst, $src0, $src1", pattern
>;
multiclass SOP2_64_32_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
opName#" $sdst, $src0, $src1", pattern
>;
class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1,
string opName, list<dag> pattern = []> : SOPC <
op, (outs), (ins rc0:$src0, rc1:$src1),
opName#" $src0, $src1", pattern > {
let Defs = [SCC];
}
class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
string opName, PatLeaf cond> : SOPC_Base <
op, rc, rc, opName,
[(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > {
}
class SOPC_CMP_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
: SOPC_Helper<op, SSrc_32, i32, opName, cond>;
class SOPC_32<bits<7> op, string opName, list<dag> pattern = []>
: SOPC_Base<op, SSrc_32, SSrc_32, opName, pattern>;
class SOPC_64_32<bits<7> op, string opName, list<dag> pattern = []>
: SOPC_Base<op, SSrc_64, SSrc_32, opName, pattern>;
class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SOPK <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
SOPK <outs, ins, asm, []>,
SOPKe <op.SI>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
let isCodeGenOnly = 0;
}
class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
SOPK <outs, ins, asm, []>,
SOPKe <op.VI>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
let isCodeGenOnly = 0;
}
multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
string asm = opName#opAsm> {
def "" : SOPK_Pseudo <opName, outs, ins, []>;
def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
def _vi : SOPK_Real_vi <op, opName, outs, ins, asm>;
}
multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
def "" : SOPK_Pseudo <opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
pattern>;
def _si : SOPK_Real_si <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
opName#" $sdst, $simm16">;
def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
opName#" $sdst, $simm16">;
}
multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
def "" : SOPK_Pseudo <opName, (outs),
(ins SReg_32:$src0, u16imm:$src1), pattern> {
let Defs = [SCC];
}
def _si : SOPK_Real_si <op, opName, (outs),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
let Defs = [SCC];
}
def _vi : SOPK_Real_vi <op, opName, (outs),
(ins SReg_32:$sdst, u16imm:$simm16), opName#" $sdst, $simm16"> {
let Defs = [SCC];
}
}
multiclass SOPK_32TIE <sopk op, string opName, list<dag> pattern> : SOPK_m <
op, opName, (outs SReg_32:$sdst), (ins SReg_32:$src0, u16imm:$simm16),
" $sdst, $simm16"
>;
multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
string argAsm, string asm = opName#argAsm> {
def "" : SOPK_Pseudo <opName, outs, ins, []>;
def _si : SOPK <outs, ins, asm, []>,
SOPK64e <op.SI>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
let isCodeGenOnly = 0;
}
def _vi : SOPK <outs, ins, asm, []>,
SOPK64e <op.VI>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
let isCodeGenOnly = 0;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SMRD classes // SMRD classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SMRD <outs, ins, "", pattern>, SMRD <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> { SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1; let isPseudo = 1;
▲ Show 20 Lines • Show All 2,488 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SIInstructions.td

Show All 12 Lines
def isGCN : Predicate<"Subtarget->getGeneration() " def isGCN : Predicate<"Subtarget->getGeneration() "
">= SISubtarget::SOUTHERN_ISLANDS">, ">= SISubtarget::SOUTHERN_ISLANDS">,
AssemblerPredicate<"FeatureGCN">; AssemblerPredicate<"FeatureGCN">;
def isSI : Predicate<"Subtarget->getGeneration() " def isSI : Predicate<"Subtarget->getGeneration() "
"== SISubtarget::SOUTHERN_ISLANDS">, "== SISubtarget::SOUTHERN_ISLANDS">,
AssemblerPredicate<"FeatureSouthernIslands">; AssemblerPredicate<"FeatureSouthernIslands">;
def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
include "SOPInstructions.td"
let SubtargetPredicate = isGCN in { let SubtargetPredicate = isGCN in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// EXP Instructions // EXP Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm EXP : EXP_m; defm EXP : EXP_m;
Show All 39 Linesdefm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime",
(outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))] (outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
>; >;
} }
defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv", defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
int_amdgcn_s_dcache_inv>; int_amdgcn_s_dcache_inv>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SOP1 Instructions
//===----------------------------------------------------------------------===//
let isMoveImm = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>;
defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>;
} // End isRematerializeable = 1
let Uses = [SCC] in {
defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>;
defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>;
} // End Uses = [SCC]
} // End isMoveImm = 1
let Defs = [SCC] in {
defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32",
[(set i32:$sdst, (not i32:$src0))]
>;
defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64",
[(set i64:$sdst, (not i64:$src0))]
>;
defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>;
defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>;
} // End Defs = [SCC]
defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32",
[(set i32:$sdst, (bitreverse i32:$src0))]
>;
defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>;
let Defs = [SCC] in {
defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>;
defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>;
defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32",
[(set i32:$sdst, (ctpop i32:$src0))]
>;
defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>;
} // End Defs = [SCC]
defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>;
defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>;
defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32",
[(set i32:$sdst, (cttz_zero_undef i32:$src0))]
>;
defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>;
defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32",
[(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))]
>;
defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32",
[(set i32:$sdst, (AMDGPUffbh_i32 i32:$src0))]
>;
defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
[(set i32:$sdst, (sext_inreg i32:$src0, i8))]
>;
defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16",
[(set i32:$sdst, (sext_inreg i32:$src0, i16))]
>;
defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>;
defm S_BITSET0_B64 : SOP1_64_32 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>;
defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>;
defm S_BITSET1_B64 : SOP1_64_32 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>;
defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>;
let isTerminator = 1, isBarrier = 1,
isBranch = 1, isIndirectBranch = 1 in {
defm S_SETPC_B64 : SOP1_1 <sop1<0x20, 0x1d>, "s_setpc_b64", []>;
}
defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>;
defm S_RFE_B64 : SOP1_1 <sop1<0x22, 0x1f>, "s_rfe_b64", []>;
let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>;
defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>;
defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>;
defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>;
defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>;
defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>;
defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>;
defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>;
} // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]
defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>;
defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>;
let Uses = [M0] in {
defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>;
defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>;
defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>;
defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>;
} // End Uses = [M0]
defm S_CBRANCH_JOIN : SOP1_1 <sop1<0x32, 0x2e>, "s_cbranch_join", []>;
defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>;
let Defs = [SCC] in {
defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>;
} // End Defs = [SCC]
defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>;
//===----------------------------------------------------------------------===//
// SOP2 Instructions
//===----------------------------------------------------------------------===//
let Defs = [SCC] in { // Carry out goes to SCC
let isCommutable = 1 in {
defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>;
defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32",
[(set i32:$sdst, (add SSrc_32:$src0, SSrc_32:$src1))]
>;
} // End isCommutable = 1
defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>;
defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32",
[(set i32:$sdst, (sub SSrc_32:$src0, SSrc_32:$src1))]
>;
let Uses = [SCC] in { // Carry in comes from SCC
let isCommutable = 1 in {
defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32",
[(set i32:$sdst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
} // End isCommutable = 1
defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32",
[(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
} // End Uses = [SCC]
defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32",
[(set i32:$sdst, (smin i32:$src0, i32:$src1))]
>;
defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32",
[(set i32:$sdst, (umin i32:$src0, i32:$src1))]
>;
defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32",
[(set i32:$sdst, (smax i32:$src0, i32:$src1))]
>;
defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32",
[(set i32:$sdst, (umax i32:$src0, i32:$src1))]
>;
} // End Defs = [SCC]
let Uses = [SCC] in {
defm S_CSELECT_B32 : SOP2_32 <sop2<0x0a>, "s_cselect_b32", []>;
defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>;
} // End Uses = [SCC]
let Defs = [SCC] in {
defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32",
[(set i32:$sdst, (and i32:$src0, i32:$src1))]
>;
defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64",
[(set i64:$sdst, (and i64:$src0, i64:$src1))]
>;
defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32",
[(set i32:$sdst, (or i32:$src0, i32:$src1))]
>;
defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64",
[(set i64:$sdst, (or i64:$src0, i64:$src1))]
>;
defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32",
[(set i32:$sdst, (xor i32:$src0, i32:$src1))]
>;
defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64",
[(set i64:$sdst, (xor i64:$src0, i64:$src1))]
>;
defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>;
defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>;
defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>;
defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>;
defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>;
defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>;
defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>;
defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>;
defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>;
defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>;
} // End Defs = [SCC]
// Use added complexity so these patterns are preferred to the VALU patterns.
let AddedComplexity = 1 in {
let Defs = [SCC] in {
defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32",
[(set i32:$sdst, (shl i32:$src0, i32:$src1))]
>;
defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64",
[(set i64:$sdst, (shl i64:$src0, i32:$src1))]
>;
defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32",
[(set i32:$sdst, (srl i32:$src0, i32:$src1))]
>;
defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64",
[(set i64:$sdst, (srl i64:$src0, i32:$src1))]
>;
defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",
[(set i32:$sdst, (sra i32:$src0, i32:$src1))]
>;
defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64",
[(set i64:$sdst, (sra i64:$src0, i32:$src1))]
>;
} // End Defs = [SCC]
defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32",
[(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
defm S_BFM_B64 : SOP2_64_32_32 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
[(set i32:$sdst, (mul i32:$src0, i32:$src1))]
>;
} // End AddedComplexity = 1
let Defs = [SCC] in {
defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>;
defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>;
defm S_BFE_U64 : SOP2_64_32 <sop2<0x29, 0x27>, "s_bfe_u64", []>;
defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>;
} // End Defs = [SCC]
let sdst = 0 in {
defm S_CBRANCH_G_FORK : SOP2_m <
sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs),
(ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", []
>;
}
let Defs = [SCC] in {
defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>;
} // End Defs = [SCC]
//===----------------------------------------------------------------------===//
// SOPC Instructions
//===----------------------------------------------------------------------===//
def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00000000, "s_cmp_eq_i32", COND_EQ>;
def S_CMP_LG_I32 : SOPC_CMP_32 <0x00000001, "s_cmp_lg_i32", COND_NE>;
def S_CMP_GT_I32 : SOPC_CMP_32 <0x00000002, "s_cmp_gt_i32", COND_SGT>;
def S_CMP_GE_I32 : SOPC_CMP_32 <0x00000003, "s_cmp_ge_i32", COND_SGE>;
def S_CMP_LT_I32 : SOPC_CMP_32 <0x00000004, "s_cmp_lt_i32", COND_SLT>;
def S_CMP_LE_I32 : SOPC_CMP_32 <0x00000005, "s_cmp_le_i32", COND_SLE>;
def S_CMP_EQ_U32 : SOPC_CMP_32 <0x00000006, "s_cmp_eq_u32", COND_EQ>;
def S_CMP_LG_U32 : SOPC_CMP_32 <0x00000007, "s_cmp_lg_u32", COND_NE >;
def S_CMP_GT_U32 : SOPC_CMP_32 <0x00000008, "s_cmp_gt_u32", COND_UGT>;
def S_CMP_GE_U32 : SOPC_CMP_32 <0x00000009, "s_cmp_ge_u32", COND_UGE>;
def S_CMP_LT_U32 : SOPC_CMP_32 <0x0000000a, "s_cmp_lt_u32", COND_ULT>;
def S_CMP_LE_U32 : SOPC_CMP_32 <0x0000000b, "s_cmp_le_u32", COND_ULE>;
def S_BITCMP0_B32 : SOPC_32 <0x0000000c, "s_bitcmp0_b32">;
def S_BITCMP1_B32 : SOPC_32 <0x0000000d, "s_bitcmp1_b32">;
def S_BITCMP0_B64 : SOPC_64_32 <0x0000000e, "s_bitcmp0_b64">;
def S_BITCMP1_B64 : SOPC_64_32 <0x0000000f, "s_bitcmp1_b64">;
def S_SETVSKIP : SOPC_32 <0x00000010, "s_setvskip">;
//===----------------------------------------------------------------------===//
// SOPK Instructions
//===----------------------------------------------------------------------===//
let isReMaterializable = 1, isMoveImm = 1 in {
defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>;
} // End isReMaterializable = 1
let Uses = [SCC] in {
defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>;
}
let isCompare = 1 in {
/*
This instruction is disabled for now until we can figure out how to teach
the instruction selector to correctly use the S_CMP* vs V_CMP*
instructions.
When this instruction is enabled the code generator sometimes produces this
invalid sequence:
SCC = S_CMPK_EQ_I32 SGPR0, imm
VCC = COPY SCC
VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32",
[(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
>;
*/
defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>;
defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>;
defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>;
defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>;
defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>;
defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>;
defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>;
defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>;
defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>;
defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>;
defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>;
defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>;
} // End isCompare = 1
let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0",
Constraints = "$sdst = $src0" in {
defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>;
defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>;
}
defm S_CBRANCH_I_FORK : SOPK_m <
sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs),
(ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
>;
let mayLoad = 1 in {
defm S_GETREG_B32 : SOPK_m <
sopk<0x12, 0x11>, "s_getreg_b32", (outs SReg_32:$sdst),
(ins hwreg:$simm16), " $sdst, $simm16"
>;
}
defm S_SETREG_B32 : SOPK_m <
sopk<0x13, 0x12>, "s_setreg_b32", (outs),
(ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst"
>;
// FIXME: Not on SI?
//defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>;
defm S_SETREG_IMM32_B32 : SOPK_IMM32 <
sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs),
(ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
>;
//===----------------------------------------------------------------------===//
// SOPP Instructions
//===----------------------------------------------------------------------===//
def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
let isTerminator = 1 in {
def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
[(AMDGPUendpgm)]> {
let simm16 = 0;
let isBarrier = 1;
let hasCtrlDep = 1;
let hasSideEffects = 1;
}
let isBranch = 1, SchedRW = [WriteBranch] in {
def S_BRANCH : SOPP <
0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
[(br bb:$simm16)]> {
let isBarrier = 1;
}
let Uses = [SCC] in {
def S_CBRANCH_SCC0 : SOPP <
0x00000004, (ins sopp_brtarget:$simm16),
"s_cbranch_scc0 $simm16"
>;
def S_CBRANCH_SCC1 : SOPP <
0x00000005, (ins sopp_brtarget:$simm16),
"s_cbranch_scc1 $simm16",
[(si_uniform_br_scc SCC, bb:$simm16)]
>;
} // End Uses = [SCC]
let Uses = [VCC] in {
def S_CBRANCH_VCCZ : SOPP <
0x00000006, (ins sopp_brtarget:$simm16),
"s_cbranch_vccz $simm16"
>;
def S_CBRANCH_VCCNZ : SOPP <
0x00000007, (ins sopp_brtarget:$simm16),
"s_cbranch_vccnz $simm16"
>;
} // End Uses = [VCC]
let Uses = [EXEC] in {
def S_CBRANCH_EXECZ : SOPP <
0x00000008, (ins sopp_brtarget:$simm16),
"s_cbranch_execz $simm16"
>;
def S_CBRANCH_EXECNZ : SOPP <
0x00000009, (ins sopp_brtarget:$simm16),
"s_cbranch_execnz $simm16"
>;
} // End Uses = [EXEC]
} // End isBranch = 1
} // End isTerminator = 1
let hasSideEffects = 1 in {
def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
[(int_amdgcn_s_barrier)]
> {
let SchedRW = [WriteBarrier];
let simm16 = 0;
let mayLoad = 1;
let mayStore = 1;
let isConvergent = 1;
}
let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
// On SI the documentation says sleep for approximately 64 * low 2
// bits, consistent with the reported maximum of 448. On VI the
// maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the
// maximum really 15 on VI?
def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16),
"s_sleep $simm16", [(int_amdgcn_s_sleep SIMM16bit:$simm16)]> {
let hasSideEffects = 1;
let mayLoad = 1;
let mayStore = 1;
}
def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">;
let Uses = [EXEC, M0] in {
// FIXME: Should this be mayLoad+mayStore?
def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16",
[(AMDGPUsendmsg (i32 imm:$simm16))]
>;
} // End Uses = [EXEC, M0]
def S_SENDMSGHALT : SOPP <0x00000011, (ins SendMsgImm:$simm16), "s_sendmsghalt $simm16">;
def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
let simm16 = 0;
}
def S_INCPERFLEVEL : SOPP <0x00000014, (ins i32imm:$simm16), "s_incperflevel $simm16",
[(int_amdgcn_s_incperflevel SIMM16bit:$simm16)]> {
let hasSideEffects = 1;
let mayLoad = 1;
let mayStore = 1;
}
def S_DECPERFLEVEL : SOPP <0x00000015, (ins i32imm:$simm16), "s_decperflevel $simm16",
[(int_amdgcn_s_decperflevel SIMM16bit:$simm16)]> {
let hasSideEffects = 1;
let mayLoad = 1;
let mayStore = 1;
}
def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
let simm16 = 0;
}
} // End hasSideEffects
//===----------------------------------------------------------------------===//
// VOPC Instructions // VOPC Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isCompare = 1, isCommutable = 1 in { let isCompare = 1, isCommutable = 1 in {
defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">; defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>; defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
▲ Show 20 Lines • Show All 1,667 Lines • ▼ Show 20 Linesdef : Pat<
(EXTRACT_SUBREG (EXTRACT_SUBREG
(BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN (BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN
(REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1),
(REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1),
$rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)),
sub0) sub0)
>; >;
//===----------------------------------------------------------------------===//
// S_GETREG_B32 Intrinsic Pattern.
//===----------------------------------------------------------------------===//
def : Pat <
(int_amdgcn_s_getreg imm:$simm16),
(S_GETREG_B32 (as_i16imm $simm16))
>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// V_ICMPIntrinsic Pattern. // V_ICMPIntrinsic Pattern.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat < class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat <
(AMDGPUsetcc vt:$src0, vt:$src1, cond), (AMDGPUsetcc vt:$src0, vt:$src1, cond),
(inst $src0, $src1) (inst $src0, $src1)
>; >;
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Linesdef : Pat <
(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset) (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)
>; >;
} // End Predicates = [isCI] } // End Predicates = [isCI]
} // End let AddedComplexity = 10000 } // End let AddedComplexity = 10000
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SOP1 Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(i64 (ctpop i64:$src)),
(i64 (REG_SEQUENCE SReg_64,
(i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0,
(S_MOV_B32 0), sub1))
>;
def : Pat <
(i32 (smax i32:$x, (i32 (ineg i32:$x)))),
(S_ABS_I32 $x)
>;
//===----------------------------------------------------------------------===//
// SOP2 Patterns
//===----------------------------------------------------------------------===//
// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
// case, the sgpr-copies pass will fix this to use the vector version.
def : Pat <
(i32 (addc i32:$src0, i32:$src1)),
(S_ADD_U32 $src0, $src1)
>;
//===----------------------------------------------------------------------===//
// SOPP Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(int_amdgcn_s_waitcnt i32:$simm16),
(S_WAITCNT (as_i16imm $simm16))
>;
//===----------------------------------------------------------------------===//
// VOP1 Patterns // VOP1 Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [UnsafeFPMath] in { let Predicates = [UnsafeFPMath] in {
//def : RcpPat<V_RCP_F64_e32, f64>; //def : RcpPat<V_RCP_F64_e32, f64>;
//defm : RsqPat<V_RSQ_F64_e32, f64>; //defm : RsqPat<V_RSQ_F64_e32, f64>;
//defm : RsqPat<V_RSQ_F32_e32, f32>; //defm : RsqPat<V_RSQ_F32_e32, f32>;
▲ Show 20 Lines • Show All 1,157 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td

//===-- SOPInstructions.td - SOP Instruction Defintions -------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// SOP1 Instructions
//===----------------------------------------------------------------------===//
class SOP1_Pseudo <string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
InstSI <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let SubtargetPredicate = isGCN;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOP1 = 1;
let SchedRW = [WriteSALU];
string Mnemonic = opName;
string AsmOperands = asmOps;
bits<1> has_src0 = 1;
bits<1> has_sdst = 1;
}
class SOP1_Real<bits<8> op, SOP1_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList,
ps.Mnemonic # " " # ps.AsmOperands, []>,
Enc32 {
let isPseudo = 0;
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
// encoding
bits<7> sdst;
bits<8> src0;
let Inst{7-0} = !if(ps.has_src0, src0, ?);
let Inst{15-8} = op;
let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
let Inst{31-23} = 0x17d; //encoding;
}
class SOP1_32 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0),
"$sdst, $src0", pattern
>;
class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0),
"$sdst, $src0", pattern
>;
// 64-bit input, 32-bit output.
class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_32:$sdst), (ins SSrc_64:$src0),
"$sdst, $src0", pattern
>;
// 32-bit input, 64-bit output.
class SOP1_64_32 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0),
"$sdst, $src0", pattern
>;
// no input, 64-bit output.
class SOP1_64_0 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs SReg_64:$sdst), (ins), "$sdst", pattern> {
let has_src0 = 0;
}
// 64-bit input, no output
class SOP1_1 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
opName, (outs), (ins SReg_64:$src0), "$src0", pattern> {
let has_sdst = 0;
}
let isMoveImm = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
def S_MOV_B32 : SOP1_32 <"s_mov_b32">;
def S_MOV_B64 : SOP1_64 <"s_mov_b64">;
} // End isRematerializeable = 1
let Uses = [SCC] in {
def S_CMOV_B32 : SOP1_32 <"s_cmov_b32">;
def S_CMOV_B64 : SOP1_64 <"s_cmov_b64">;
} // End Uses = [SCC]
} // End isMoveImm = 1
let Defs = [SCC] in {
def S_NOT_B32 : SOP1_32 <"s_not_b32",
[(set i32:$sdst, (not i32:$src0))]
>;
def S_NOT_B64 : SOP1_64 <"s_not_b64",
[(set i64:$sdst, (not i64:$src0))]
>;
def S_WQM_B32 : SOP1_32 <"s_wqm_b32">;
def S_WQM_B64 : SOP1_64 <"s_wqm_b64">;
} // End Defs = [SCC]
def S_BREV_B32 : SOP1_32 <"s_brev_b32",
[(set i32:$sdst, (bitreverse i32:$src0))]
>;
def S_BREV_B64 : SOP1_64 <"s_brev_b64">;
let Defs = [SCC] in {
def S_BCNT0_I32_B32 : SOP1_32 <"s_bcnt0_i32_b32">;
def S_BCNT0_I32_B64 : SOP1_32_64 <"s_bcnt0_i32_b64">;
def S_BCNT1_I32_B32 : SOP1_32 <"s_bcnt1_i32_b32",
[(set i32:$sdst, (ctpop i32:$src0))]
>;
def S_BCNT1_I32_B64 : SOP1_32_64 <"s_bcnt1_i32_b64">;
} // End Defs = [SCC]
def S_FF0_I32_B32 : SOP1_32 <"s_ff0_i32_b32">;
def S_FF0_I32_B64 : SOP1_32_64 <"s_ff0_i32_b64">;
def S_FF1_I32_B32 : SOP1_32 <"s_ff1_i32_b32",
[(set i32:$sdst, (cttz_zero_undef i32:$src0))]
>;
def S_FF1_I32_B64 : SOP1_32_64 <"s_ff1_i32_b64">;
def S_FLBIT_I32_B32 : SOP1_32 <"s_flbit_i32_b32",
[(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))]
>;
def S_FLBIT_I32_B64 : SOP1_32_64 <"s_flbit_i32_b64">;
def S_FLBIT_I32 : SOP1_32 <"s_flbit_i32",
[(set i32:$sdst, (AMDGPUffbh_i32 i32:$src0))]
>;
def S_FLBIT_I32_I64 : SOP1_32_64 <"s_flbit_i32_i64">;
def S_SEXT_I32_I8 : SOP1_32 <"s_sext_i32_i8",
[(set i32:$sdst, (sext_inreg i32:$src0, i8))]
>;
def S_SEXT_I32_I16 : SOP1_32 <"s_sext_i32_i16",
[(set i32:$sdst, (sext_inreg i32:$src0, i16))]
>;
def S_BITSET0_B32 : SOP1_32 <"s_bitset0_b32">;
def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64">;
def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32">;
def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64">;
def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64">;
let isTerminator = 1, isBarrier = 1,
isBranch = 1, isIndirectBranch = 1 in {
def S_SETPC_B64 : SOP1_1 <"s_setpc_b64">;
}
def S_SWAPPC_B64 : SOP1_64 <"s_swappc_b64">;
def S_RFE_B64 : SOP1_1 <"s_rfe_b64">;
let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
def S_AND_SAVEEXEC_B64 : SOP1_64 <"s_and_saveexec_b64">;
def S_OR_SAVEEXEC_B64 : SOP1_64 <"s_or_saveexec_b64">;
def S_XOR_SAVEEXEC_B64 : SOP1_64 <"s_xor_saveexec_b64">;
def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <"s_andn2_saveexec_b64">;
def S_ORN2_SAVEEXEC_B64 : SOP1_64 <"s_orn2_saveexec_b64">;
def S_NAND_SAVEEXEC_B64 : SOP1_64 <"s_nand_saveexec_b64">;
def S_NOR_SAVEEXEC_B64 : SOP1_64 <"s_nor_saveexec_b64">;
def S_XNOR_SAVEEXEC_B64 : SOP1_64 <"s_xnor_saveexec_b64">;
} // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]
def S_QUADMASK_B32 : SOP1_32 <"s_quadmask_b32">;
def S_QUADMASK_B64 : SOP1_64 <"s_quadmask_b64">;
let Uses = [M0] in {
def S_MOVRELS_B32 : SOP1_32 <"s_movrels_b32">;
def S_MOVRELS_B64 : SOP1_64 <"s_movrels_b64">;
def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">;
def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">;
} // End Uses = [M0]
def S_CBRANCH_JOIN : SOP1_1 <"s_cbranch_join">;
def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">;
let Defs = [SCC] in {
def S_ABS_I32 : SOP1_32 <"s_abs_i32">;
} // End Defs = [SCC]
def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">;
//===----------------------------------------------------------------------===//
// SOP2 Instructions
//===----------------------------------------------------------------------===//
class SOP2_Pseudo<string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
InstSI<outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let SubtargetPredicate = isGCN;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOP2 = 1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
string Mnemonic = opName;
string AsmOperands = asmOps;
bits<1> has_sdst = 1;
// Pseudo instructions have no encodings, but adding this field here allows
// us to do:
// let sdst = xxx in {
// for multiclasses that include both real and pseudo instructions.
// field bits<7> sdst = 0;
// let Size = 4; // Do we need size here?
}
class SOP2_Real<bits<7> op, SOP2_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList,
ps.Mnemonic # " " # ps.AsmOperands, []>,
Enc32 {
let isPseudo = 0;
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
// encoding
bits<7> sdst;
bits<8> src0;
bits<8> src1;
let Inst{7-0} = src0;
let Inst{15-8} = src1;
let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
let Inst{29-23} = op;
let Inst{31-30} = 0x2; // encoding
}
class SOP2_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
"$sdst, $src0, $src1", pattern
>;
class SOP2_64 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_64:$src1),
"$sdst, $src0, $src1", pattern
>;
class SOP2_64_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_32:$src1),
"$sdst, $src0, $src1", pattern
>;
class SOP2_64_32_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
"$sdst, $src0, $src1", pattern
>;
let Defs = [SCC] in { // Carry out goes to SCC
let isCommutable = 1 in {
def S_ADD_U32 : SOP2_32 <"s_add_u32">;
def S_ADD_I32 : SOP2_32 <"s_add_i32",
[(set i32:$sdst, (add SSrc_32:$src0, SSrc_32:$src1))]
>;
} // End isCommutable = 1
def S_SUB_U32 : SOP2_32 <"s_sub_u32">;
def S_SUB_I32 : SOP2_32 <"s_sub_i32",
[(set i32:$sdst, (sub SSrc_32:$src0, SSrc_32:$src1))]
>;
let Uses = [SCC] in { // Carry in comes from SCC
let isCommutable = 1 in {
def S_ADDC_U32 : SOP2_32 <"s_addc_u32",
[(set i32:$sdst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
} // End isCommutable = 1
def S_SUBB_U32 : SOP2_32 <"s_subb_u32",
[(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
} // End Uses = [SCC]
def S_MIN_I32 : SOP2_32 <"s_min_i32",
[(set i32:$sdst, (smin i32:$src0, i32:$src1))]
>;
def S_MIN_U32 : SOP2_32 <"s_min_u32",
[(set i32:$sdst, (umin i32:$src0, i32:$src1))]
>;
def S_MAX_I32 : SOP2_32 <"s_max_i32",
[(set i32:$sdst, (smax i32:$src0, i32:$src1))]
>;
def S_MAX_U32 : SOP2_32 <"s_max_u32",
[(set i32:$sdst, (umax i32:$src0, i32:$src1))]
>;
} // End Defs = [SCC]
let Uses = [SCC] in {
def S_CSELECT_B32 : SOP2_32 <"s_cselect_b32">;
def S_CSELECT_B64 : SOP2_64 <"s_cselect_b64">;
} // End Uses = [SCC]
let Defs = [SCC] in {
def S_AND_B32 : SOP2_32 <"s_and_b32",
[(set i32:$sdst, (and i32:$src0, i32:$src1))]
>;
def S_AND_B64 : SOP2_64 <"s_and_b64",
[(set i64:$sdst, (and i64:$src0, i64:$src1))]
>;
def S_OR_B32 : SOP2_32 <"s_or_b32",
[(set i32:$sdst, (or i32:$src0, i32:$src1))]
>;
def S_OR_B64 : SOP2_64 <"s_or_b64",
[(set i64:$sdst, (or i64:$src0, i64:$src1))]
>;
def S_XOR_B32 : SOP2_32 <"s_xor_b32",
[(set i32:$sdst, (xor i32:$src0, i32:$src1))]
>;
def S_XOR_B64 : SOP2_64 <"s_xor_b64",
[(set i64:$sdst, (xor i64:$src0, i64:$src1))]
>;
def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32">;
def S_ANDN2_B64 : SOP2_64 <"s_andn2_b64">;
def S_ORN2_B32 : SOP2_32 <"s_orn2_b32">;
def S_ORN2_B64 : SOP2_64 <"s_orn2_b64">;
def S_NAND_B32 : SOP2_32 <"s_nand_b32">;
def S_NAND_B64 : SOP2_64 <"s_nand_b64">;
def S_NOR_B32 : SOP2_32 <"s_nor_b32">;
def S_NOR_B64 : SOP2_64 <"s_nor_b64">;
def S_XNOR_B32 : SOP2_32 <"s_xnor_b32">;
def S_XNOR_B64 : SOP2_64 <"s_xnor_b64">;
} // End Defs = [SCC]
// Use added complexity so these patterns are preferred to the VALU patterns.
let AddedComplexity = 1 in {
let Defs = [SCC] in {
def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
[(set i32:$sdst, (shl i32:$src0, i32:$src1))]
>;
def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
[(set i64:$sdst, (shl i64:$src0, i32:$src1))]
>;
def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
[(set i32:$sdst, (srl i32:$src0, i32:$src1))]
>;
def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",
[(set i64:$sdst, (srl i64:$src0, i32:$src1))]
>;
def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
[(set i32:$sdst, (sra i32:$src0, i32:$src1))]
>;
def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
[(set i64:$sdst, (sra i64:$src0, i32:$src1))]
>;
} // End Defs = [SCC]
def S_BFM_B32 : SOP2_32 <"s_bfm_b32",
[(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;
def S_MUL_I32 : SOP2_32 <"s_mul_i32",
[(set i32:$sdst, (mul i32:$src0, i32:$src1))]
>;
} // End AddedComplexity = 1
let Defs = [SCC] in {
def S_BFE_U32 : SOP2_32 <"s_bfe_u32">;
def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;
def S_BFE_U64 : SOP2_64_32 <"s_bfe_u64">;
def S_BFE_I64 : SOP2_64_32 <"s_bfe_i64">;
} // End Defs = [SCC]
def S_CBRANCH_G_FORK : SOP2_Pseudo <
"s_cbranch_g_fork", (outs),
(ins SReg_64:$src0, SReg_64:$src1),
"$src0, $src1"
> {
let has_sdst = 0;
}
let Defs = [SCC] in {
def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">;
} // End Defs = [SCC]
//===----------------------------------------------------------------------===//
// SOPK Instructions
//===----------------------------------------------------------------------===//
class SOPK_Pseudo <string opName, dag outs, dag ins,
string asmOps, list<dag> pattern=[]> :
InstSI <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let SubtargetPredicate = isGCN;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPK = 1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
string Mnemonic = opName;
string AsmOperands = asmOps;
bits<1> has_sdst = 1;
}
class SOPK_Real<bits<5> op, SOPK_Pseudo ps> :
InstSI <ps.OutOperandList, ps.InOperandList,
ps.Mnemonic # " " # ps.AsmOperands, []> {
let isPseudo = 0;
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let DisableEncoding = ps.DisableEncoding;
let Constraints = ps.Constraints;
// encoding
bits<7> sdst;
bits<16> simm16;
bits<32> imm;
}
class SOPK_Real32<bits<5> op, SOPK_Pseudo ps> :
SOPK_Real <op, ps>,
Enc32 {
let Inst{15-0} = simm16;
let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
let Inst{27-23} = op;
let Inst{31-28} = 0xb; //encoding
}
class SOPK_Real64<bits<5> op, SOPK_Pseudo ps> :
SOPK_Real<op, ps>,
Enc64 {
let Inst{15-0} = simm16;
let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
let Inst{27-23} = op;
let Inst{31-28} = 0xb; //encoding
let Inst{63-32} = imm;
}
class SOPK_32 <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
opName,
(outs SReg_32:$sdst),
(ins u16imm:$simm16),
"$sdst, $simm16",
pattern>;
class SOPK_SCC <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
opName,
(outs),
(ins SReg_32:$sdst, u16imm:$simm16),
"$sdst, $simm16",
pattern> {
let Defs = [SCC];
}
class SOPK_32TIE <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
opName,
(outs SReg_32:$sdst),
(ins SReg_32:$src0, u16imm:$simm16),
"$sdst, $simm16",
pattern
>;
let isReMaterializable = 1, isMoveImm = 1 in {
def S_MOVK_I32 : SOPK_32 <"s_movk_i32">;
} // End isReMaterializable = 1
let Uses = [SCC] in {
def S_CMOVK_I32 : SOPK_32 <"s_cmovk_i32">;
}
let isCompare = 1 in {
// This instruction is disabled for now until we can figure out how to teach
// the instruction selector to correctly use the S_CMP* vs V_CMP*
// instructions.
//
// When this instruction is enabled the code generator sometimes produces this
// invalid sequence:
//
// SCC = S_CMPK_EQ_I32 SGPR0, imm
// VCC = COPY SCC
// VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
//
// def S_CMPK_EQ_I32 : SOPK_SCC <"s_cmpk_eq_i32",
// [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
// >;
def S_CMPK_EQ_I32 : SOPK_SCC <"s_cmpk_eq_i32">;
def S_CMPK_LG_I32 : SOPK_SCC <"s_cmpk_lg_i32">;
def S_CMPK_GT_I32 : SOPK_SCC <"s_cmpk_gt_i32">;
def S_CMPK_GE_I32 : SOPK_SCC <"s_cmpk_ge_i32">;
def S_CMPK_LT_I32 : SOPK_SCC <"s_cmpk_lt_i32">;
def S_CMPK_LE_I32 : SOPK_SCC <"s_cmpk_le_i32">;
def S_CMPK_EQ_U32 : SOPK_SCC <"s_cmpk_eq_u32">;
def S_CMPK_LG_U32 : SOPK_SCC <"s_cmpk_lg_u32">;
def S_CMPK_GT_U32 : SOPK_SCC <"s_cmpk_gt_u32">;
def S_CMPK_GE_U32 : SOPK_SCC <"s_cmpk_ge_u32">;
def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32">;
def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32">;
} // End isCompare = 1
let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0",
Constraints = "$sdst = $src0" in {
def S_ADDK_I32 : SOPK_32TIE <"s_addk_i32">;
def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;
}
def S_CBRANCH_I_FORK : SOPK_Pseudo <
"s_cbranch_i_fork",
(outs), (ins SReg_64:$sdst, u16imm:$simm16),
"$sdst, $simm16"
>;
let mayLoad = 1 in {
def S_GETREG_B32 : SOPK_Pseudo <
"s_getreg_b32",
(outs SReg_32:$sdst), (ins hwreg:$simm16),
"$sdst, $simm16"
>;
}
def S_SETREG_B32 : SOPK_Pseudo <
"s_setreg_b32",
(outs), (ins SReg_32:$sdst, hwreg:$simm16),
"$simm16, $sdst"
>;
// FIXME: Not on SI?
//def S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32">;
def S_SETREG_IMM32_B32 : SOPK_Pseudo <
"s_setreg_imm32_b32",
(outs), (ins i32imm:$imm, hwreg:$simm16),
"$simm16, $imm"
> {
let has_sdst = 0;
}
//===----------------------------------------------------------------------===//
// SOPC Instructions
//===----------------------------------------------------------------------===//
class SOPCe <bits<7> op> : Enc32 {
bits<8> src0;
bits<8> src1;
let Inst{7-0} = src0;
let Inst{15-8} = src1;
let Inst{22-16} = op;
let Inst{31-23} = 0x17e;
}
class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern>, SOPCe <op> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPC = 1;
let isCodeGenOnly = 0;
let Defs = [SCC];
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
let SubtargetPredicate = isGCN;
}
class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1,
string opName, list<dag> pattern = []> : SOPC <
op, (outs), (ins rc0:$src0, rc1:$src1),
opName#" $src0, $src1", pattern > {
let Defs = [SCC];
}
class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
string opName, PatLeaf cond> : SOPC_Base <
op, rc, rc, opName,
[(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > {
}
class SOPC_CMP_32<bits<7> op, string opName, PatLeaf cond = COND_NULL>
: SOPC_Helper<op, SSrc_32, i32, opName, cond>;
class SOPC_32<bits<7> op, string opName, list<dag> pattern = []>
: SOPC_Base<op, SSrc_32, SSrc_32, opName, pattern>;
class SOPC_64_32<bits<7> op, string opName, list<dag> pattern = []>
: SOPC_Base<op, SSrc_64, SSrc_32, opName, pattern>;
def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00, "s_cmp_eq_i32", COND_EQ>;
def S_CMP_LG_I32 : SOPC_CMP_32 <0x01, "s_cmp_lg_i32", COND_NE>;
def S_CMP_GT_I32 : SOPC_CMP_32 <0x02, "s_cmp_gt_i32", COND_SGT>;
def S_CMP_GE_I32 : SOPC_CMP_32 <0x03, "s_cmp_ge_i32", COND_SGE>;
def S_CMP_LT_I32 : SOPC_CMP_32 <0x04, "s_cmp_lt_i32", COND_SLT>;
def S_CMP_LE_I32 : SOPC_CMP_32 <0x05, "s_cmp_le_i32", COND_SLE>;
def S_CMP_EQ_U32 : SOPC_CMP_32 <0x06, "s_cmp_eq_u32", COND_EQ>;
def S_CMP_LG_U32 : SOPC_CMP_32 <0x07, "s_cmp_lg_u32", COND_NE >;
def S_CMP_GT_U32 : SOPC_CMP_32 <0x08, "s_cmp_gt_u32", COND_UGT>;
def S_CMP_GE_U32 : SOPC_CMP_32 <0x09, "s_cmp_ge_u32", COND_UGE>;
def S_CMP_LT_U32 : SOPC_CMP_32 <0x0a, "s_cmp_lt_u32", COND_ULT>;
def S_CMP_LE_U32 : SOPC_CMP_32 <0x0b, "s_cmp_le_u32", COND_ULE>;
def S_BITCMP0_B32 : SOPC_32 <0x0c, "s_bitcmp0_b32">;
def S_BITCMP1_B32 : SOPC_32 <0x0d, "s_bitcmp1_b32">;
def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">;
def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">;
def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
//===----------------------------------------------------------------------===//
// SOPP Instructions
//===----------------------------------------------------------------------===//
class SOPPe <bits<7> op> : Enc32 {
bits <16> simm16;
let Inst{15-0} = simm16;
let Inst{22-16} = op;
let Inst{31-23} = 0x17f; // encoding
}
class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let SOPP = 1;
let SchedRW = [WriteSALU];
let UseNamedOperandTable = 1;
let SubtargetPredicate = isGCN;
}
def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
let isTerminator = 1 in {
def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
[(AMDGPUendpgm)]> {
let simm16 = 0;
let isBarrier = 1;
let hasCtrlDep = 1;
let hasSideEffects = 1;
}
let isBranch = 1, SchedRW = [WriteBranch] in {
def S_BRANCH : SOPP <
0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
[(br bb:$simm16)]> {
let isBarrier = 1;
}
let Uses = [SCC] in {
def S_CBRANCH_SCC0 : SOPP <
0x00000004, (ins sopp_brtarget:$simm16),
"s_cbranch_scc0 $simm16"
>;
def S_CBRANCH_SCC1 : SOPP <
0x00000005, (ins sopp_brtarget:$simm16),
"s_cbranch_scc1 $simm16",
[(si_uniform_br_scc SCC, bb:$simm16)]
>;
} // End Uses = [SCC]
let Uses = [VCC] in {
def S_CBRANCH_VCCZ : SOPP <
0x00000006, (ins sopp_brtarget:$simm16),
"s_cbranch_vccz $simm16"
>;
def S_CBRANCH_VCCNZ : SOPP <
0x00000007, (ins sopp_brtarget:$simm16),
"s_cbranch_vccnz $simm16"
>;
} // End Uses = [VCC]
let Uses = [EXEC] in {
def S_CBRANCH_EXECZ : SOPP <
0x00000008, (ins sopp_brtarget:$simm16),
"s_cbranch_execz $simm16"
>;
def S_CBRANCH_EXECNZ : SOPP <
0x00000009, (ins sopp_brtarget:$simm16),
"s_cbranch_execnz $simm16"
>;
} // End Uses = [EXEC]
} // End isBranch = 1
} // End isTerminator = 1
let hasSideEffects = 1 in {
def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
[(int_amdgcn_s_barrier)]> {
let SchedRW = [WriteBarrier];
let simm16 = 0;
let mayLoad = 1;
let mayStore = 1;
let isConvergent = 1;
}
let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
// On SI the documentation says sleep for approximately 64 * low 2
// bits, consistent with the reported maximum of 448. On VI the
// maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the
// maximum really 15 on VI?
def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16),
"s_sleep $simm16", [(int_amdgcn_s_sleep SIMM16bit:$simm16)]> {
let hasSideEffects = 1;
let mayLoad = 1;
let mayStore = 1;
}
def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">;
let Uses = [EXEC, M0] in {
// FIXME: Should this be mayLoad+mayStore?
def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16",
[(AMDGPUsendmsg (i32 imm:$simm16))]
>;
} // End Uses = [EXEC, M0]
def S_SENDMSGHALT : SOPP <0x00000011, (ins SendMsgImm:$simm16), "s_sendmsghalt $simm16">;
def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
let simm16 = 0;
}
def S_INCPERFLEVEL : SOPP <0x00000014, (ins i32imm:$simm16), "s_incperflevel $simm16",
[(int_amdgcn_s_incperflevel SIMM16bit:$simm16)]> {
let hasSideEffects = 1;
let mayLoad = 1;
let mayStore = 1;
}
def S_DECPERFLEVEL : SOPP <0x00000015, (ins i32imm:$simm16), "s_decperflevel $simm16",
[(int_amdgcn_s_decperflevel SIMM16bit:$simm16)]> {
let hasSideEffects = 1;
let mayLoad = 1;
let mayStore = 1;
}
def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
let simm16 = 0;
}
} // End hasSideEffects
let Predicates = [isGCN] in {
//===----------------------------------------------------------------------===//
// S_GETREG_B32 Intrinsic Pattern.
//===----------------------------------------------------------------------===//
def : Pat <
(int_amdgcn_s_getreg imm:$simm16),
(S_GETREG_B32 (as_i16imm $simm16))
>;
//===----------------------------------------------------------------------===//
// SOP1 Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(i64 (ctpop i64:$src)),
(i64 (REG_SEQUENCE SReg_64,
(i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0,
(S_MOV_B32 0), sub1))
>;
def : Pat <
(i32 (smax i32:$x, (i32 (ineg i32:$x)))),
(S_ABS_I32 $x)
>;
//===----------------------------------------------------------------------===//
// SOP2 Patterns
//===----------------------------------------------------------------------===//
// V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
// case, the sgpr-copies pass will fix this to use the vector version.
def : Pat <
(i32 (addc i32:$src0, i32:$src1)),
(S_ADD_U32 $src0, $src1)
>;
//===----------------------------------------------------------------------===//
// SOPP Patterns
//===----------------------------------------------------------------------===//
def : Pat <
(int_amdgcn_s_waitcnt i32:$simm16),
(S_WAITCNT (as_i16imm $simm16))
>;
} // End isGCN predicate
//===----------------------------------------------------------------------===//
// Real target instructions, move this to the appropriate subtarget TD file
//===----------------------------------------------------------------------===//
class Select_si<string opName> :
SIMCInstr<opName, SIEncodingFamily.SI> {
list<Predicate> AssemblerPredicates = [isSICI];
string DecoderNamespace = "SICI";
}
class SOP1_Real_si<bits<8> op, SOP1_Pseudo ps> :
SOP1_Real<op, ps>,
Select_si<ps.Mnemonic>;
class SOP2_Real_si<bits<7> op, SOP2_Pseudo ps> :
SOP2_Real<op, ps>,
Select_si<ps.Mnemonic>;
class SOPK_Real_si<bits<5> op, SOPK_Pseudo ps> :
SOPK_Real32<op, ps>,
Select_si<ps.Mnemonic>;
def S_MOV_B32_si : SOP1_Real_si <0x03, S_MOV_B32>;
def S_MOV_B64_si : SOP1_Real_si <0x04, S_MOV_B64>;
def S_CMOV_B32_si : SOP1_Real_si <0x05, S_CMOV_B32>;
def S_CMOV_B64_si : SOP1_Real_si <0x06, S_CMOV_B64>;
def S_NOT_B32_si : SOP1_Real_si <0x07, S_NOT_B32>;
def S_NOT_B64_si : SOP1_Real_si <0x08, S_NOT_B64>;
def S_WQM_B32_si : SOP1_Real_si <0x09, S_WQM_B32>;
def S_WQM_B64_si : SOP1_Real_si <0x0a, S_WQM_B64>;
def S_BREV_B32_si : SOP1_Real_si <0x0b, S_BREV_B32>;
def S_BREV_B64_si : SOP1_Real_si <0x0c, S_BREV_B64>;
def S_BCNT0_I32_B32_si : SOP1_Real_si <0x0d, S_BCNT0_I32_B32>;
def S_BCNT0_I32_B64_si : SOP1_Real_si <0x0e, S_BCNT0_I32_B64>;
def S_BCNT1_I32_B32_si : SOP1_Real_si <0x0f, S_BCNT1_I32_B32>;
def S_BCNT1_I32_B64_si : SOP1_Real_si <0x10, S_BCNT1_I32_B64>;
def S_FF0_I32_B32_si : SOP1_Real_si <0x11, S_FF0_I32_B32>;
def S_FF0_I32_B64_si : SOP1_Real_si <0x12, S_FF0_I32_B64>;
def S_FF1_I32_B32_si : SOP1_Real_si <0x13, S_FF1_I32_B32>;
def S_FF1_I32_B64_si : SOP1_Real_si <0x14, S_FF1_I32_B64>;
def S_FLBIT_I32_B32_si : SOP1_Real_si <0x15, S_FLBIT_I32_B32>;
def S_FLBIT_I32_B64_si : SOP1_Real_si <0x16, S_FLBIT_I32_B64>;
def S_FLBIT_I32_si : SOP1_Real_si <0x17, S_FLBIT_I32>;
def S_FLBIT_I32_I64_si : SOP1_Real_si <0x18, S_FLBIT_I32_I64>;
def S_SEXT_I32_I8_si : SOP1_Real_si <0x19, S_SEXT_I32_I8>;
def S_SEXT_I32_I16_si : SOP1_Real_si <0x1a, S_SEXT_I32_I16>;
def S_BITSET0_B32_si : SOP1_Real_si <0x1b, S_BITSET0_B32>;
def S_BITSET0_B64_si : SOP1_Real_si <0x1c, S_BITSET0_B64>;
def S_BITSET1_B32_si : SOP1_Real_si <0x1d, S_BITSET1_B32>;
def S_BITSET1_B64_si : SOP1_Real_si <0x1e, S_BITSET1_B64>;
def S_GETPC_B64_si : SOP1_Real_si <0x1f, S_GETPC_B64>;
def S_SETPC_B64_si : SOP1_Real_si <0x20, S_SETPC_B64>;
def S_SWAPPC_B64_si : SOP1_Real_si <0x21, S_SWAPPC_B64>;
def S_RFE_B64_si : SOP1_Real_si <0x22, S_RFE_B64>;
def S_AND_SAVEEXEC_B64_si : SOP1_Real_si <0x24, S_AND_SAVEEXEC_B64>;
def S_OR_SAVEEXEC_B64_si : SOP1_Real_si <0x25, S_OR_SAVEEXEC_B64>;
def S_XOR_SAVEEXEC_B64_si : SOP1_Real_si <0x26, S_XOR_SAVEEXEC_B64>;
def S_ANDN2_SAVEEXEC_B64_si: SOP1_Real_si <0x27, S_ANDN2_SAVEEXEC_B64>;
def S_ORN2_SAVEEXEC_B64_si : SOP1_Real_si <0x28, S_ORN2_SAVEEXEC_B64>;
def S_NAND_SAVEEXEC_B64_si : SOP1_Real_si <0x29, S_NAND_SAVEEXEC_B64>;
def S_NOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2a, S_NOR_SAVEEXEC_B64>;
def S_XNOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2b, S_XNOR_SAVEEXEC_B64>;
def S_QUADMASK_B32_si : SOP1_Real_si <0x2c, S_QUADMASK_B32>;
def S_QUADMASK_B64_si : SOP1_Real_si <0x2d, S_QUADMASK_B64>;
def S_MOVRELS_B32_si : SOP1_Real_si <0x2e, S_MOVRELS_B32>;
def S_MOVRELS_B64_si : SOP1_Real_si <0x2f, S_MOVRELS_B64>;
def S_MOVRELD_B32_si : SOP1_Real_si <0x30, S_MOVRELD_B32>;
def S_MOVRELD_B64_si : SOP1_Real_si <0x31, S_MOVRELD_B64>;
def S_CBRANCH_JOIN_si : SOP1_Real_si <0x32, S_CBRANCH_JOIN>;
def S_MOV_REGRD_B32_si : SOP1_Real_si <0x33, S_MOV_REGRD_B32>;
def S_ABS_I32_si : SOP1_Real_si <0x34, S_ABS_I32>;
def S_MOV_FED_B32_si : SOP1_Real_si <0x35, S_MOV_FED_B32>;
def S_ADD_U32_si : SOP2_Real_si <0x00, S_ADD_U32>;
def S_ADD_I32_si : SOP2_Real_si <0x02, S_ADD_I32>;
def S_SUB_U32_si : SOP2_Real_si <0x01, S_SUB_U32>;
def S_SUB_I32_si : SOP2_Real_si <0x03, S_SUB_I32>;
def S_ADDC_U32_si : SOP2_Real_si <0x04, S_ADDC_U32>;
def S_SUBB_U32_si : SOP2_Real_si <0x05, S_SUBB_U32>;
def S_MIN_I32_si : SOP2_Real_si <0x06, S_MIN_I32>;
def S_MIN_U32_si : SOP2_Real_si <0x07, S_MIN_U32>;
def S_MAX_I32_si : SOP2_Real_si <0x08, S_MAX_I32>;
def S_MAX_U32_si : SOP2_Real_si <0x09, S_MAX_U32>;
def S_CSELECT_B32_si : SOP2_Real_si <0x0a, S_CSELECT_B32>;
def S_CSELECT_B64_si : SOP2_Real_si <0x0b, S_CSELECT_B64>;
def S_AND_B32_si : SOP2_Real_si <0x0e, S_AND_B32>;
def S_AND_B64_si : SOP2_Real_si <0x0f, S_AND_B64>;
def S_OR_B32_si : SOP2_Real_si <0x10, S_OR_B32>;
def S_OR_B64_si : SOP2_Real_si <0x11, S_OR_B64>;
def S_XOR_B32_si : SOP2_Real_si <0x12, S_XOR_B32>;
def S_XOR_B64_si : SOP2_Real_si <0x13, S_XOR_B64>;
def S_ANDN2_B32_si : SOP2_Real_si <0x14, S_ANDN2_B32>;
def S_ANDN2_B64_si : SOP2_Real_si <0x15, S_ANDN2_B64>;
def S_ORN2_B32_si : SOP2_Real_si <0x16, S_ORN2_B32>;
def S_ORN2_B64_si : SOP2_Real_si <0x17, S_ORN2_B64>;
def S_NAND_B32_si : SOP2_Real_si <0x18, S_NAND_B32>;
def S_NAND_B64_si : SOP2_Real_si <0x19, S_NAND_B64>;
def S_NOR_B32_si : SOP2_Real_si <0x1a, S_NOR_B32>;
def S_NOR_B64_si : SOP2_Real_si <0x1b, S_NOR_B64>;
def S_XNOR_B32_si : SOP2_Real_si <0x1c, S_XNOR_B32>;
def S_XNOR_B64_si : SOP2_Real_si <0x1d, S_XNOR_B64>;
def S_LSHL_B32_si : SOP2_Real_si <0x1e, S_LSHL_B32>;
def S_LSHL_B64_si : SOP2_Real_si <0x1f, S_LSHL_B64>;
def S_LSHR_B32_si : SOP2_Real_si <0x20, S_LSHR_B32>;
def S_LSHR_B64_si : SOP2_Real_si <0x21, S_LSHR_B64>;
def S_ASHR_I32_si : SOP2_Real_si <0x22, S_ASHR_I32>;
def S_ASHR_I64_si : SOP2_Real_si <0x23, S_ASHR_I64>;
def S_BFM_B32_si : SOP2_Real_si <0x24, S_BFM_B32>;
def S_BFM_B64_si : SOP2_Real_si <0x25, S_BFM_B64>;
def S_MUL_I32_si : SOP2_Real_si <0x26, S_MUL_I32>;
def S_BFE_U32_si : SOP2_Real_si <0x27, S_BFE_U32>;
def S_BFE_I32_si : SOP2_Real_si <0x28, S_BFE_I32>;
def S_BFE_U64_si : SOP2_Real_si <0x29, S_BFE_U64>;
def S_BFE_I64_si : SOP2_Real_si <0x2a, S_BFE_I64>;
def S_CBRANCH_G_FORK_si : SOP2_Real_si <0x2b, S_CBRANCH_G_FORK>;
def S_ABSDIFF_I32_si : SOP2_Real_si <0x2c, S_ABSDIFF_I32>;
def S_MOVK_I32_si : SOPK_Real_si <0x00, S_MOVK_I32>;
def S_CMOVK_I32_si : SOPK_Real_si <0x02, S_CMOVK_I32>;
def S_CMPK_EQ_I32_si : SOPK_Real_si <0x03, S_CMPK_EQ_I32>;
def S_CMPK_LG_I32_si : SOPK_Real_si <0x04, S_CMPK_LG_I32>;
def S_CMPK_GT_I32_si : SOPK_Real_si <0x05, S_CMPK_GT_I32>;
def S_CMPK_GE_I32_si : SOPK_Real_si <0x06, S_CMPK_GE_I32>;
def S_CMPK_LT_I32_si : SOPK_Real_si <0x07, S_CMPK_LT_I32>;
def S_CMPK_LE_I32_si : SOPK_Real_si <0x08, S_CMPK_LE_I32>;
def S_CMPK_EQ_U32_si : SOPK_Real_si <0x09, S_CMPK_EQ_U32>;
def S_CMPK_LG_U32_si : SOPK_Real_si <0x0a, S_CMPK_LG_U32>;
def S_CMPK_GT_U32_si : SOPK_Real_si <0x0b, S_CMPK_GT_U32>;
def S_CMPK_GE_U32_si : SOPK_Real_si <0x0c, S_CMPK_GE_U32>;
def S_CMPK_LT_U32_si : SOPK_Real_si <0x0d, S_CMPK_LT_U32>;
def S_CMPK_LE_U32_si : SOPK_Real_si <0x0e, S_CMPK_LE_U32>;
def S_ADDK_I32_si : SOPK_Real_si <0x0f, S_ADDK_I32>;
def S_MULK_I32_si : SOPK_Real_si <0x10, S_MULK_I32>;
def S_CBRANCH_I_FORK_si : SOPK_Real_si <0x11, S_CBRANCH_I_FORK>;
def S_GETREG_B32_si : SOPK_Real_si <0x12, S_GETREG_B32>;
def S_SETREG_B32_si : SOPK_Real_si <0x13, S_SETREG_B32>;
//def S_GETREG_REGRD_B32_si : SOPK_Real_si <0x14, S_GETREG_REGRD_B32>; // see pseudo for comments
def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>,
Select_si<S_SETREG_IMM32_B32.Mnemonic>;
class Select_vi<string opName> :
SIMCInstr<opName, SIEncodingFamily.VI> {
list<Predicate> AssemblerPredicates = [isVI];
string DecoderNamespace = "VI";
}
class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> :
SOP1_Real<op, ps>,
Select_vi<ps.Mnemonic>;
class SOP2_Real_vi<bits<7> op, SOP2_Pseudo ps> :
SOP2_Real<op, ps>,
Select_vi<ps.Mnemonic>;
class SOPK_Real_vi<bits<5> op, SOPK_Pseudo ps> :
SOPK_Real32<op, ps>,
Select_vi<ps.Mnemonic>;
def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>;
def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>;
def S_CMOV_B32_vi : SOP1_Real_vi <0x02, S_CMOV_B32>;
def S_CMOV_B64_vi : SOP1_Real_vi <0x03, S_CMOV_B64>;
def S_NOT_B32_vi : SOP1_Real_vi <0x04, S_NOT_B32>;
def S_NOT_B64_vi : SOP1_Real_vi <0x05, S_NOT_B64>;
def S_WQM_B32_vi : SOP1_Real_vi <0x06, S_WQM_B32>;
def S_WQM_B64_vi : SOP1_Real_vi <0x07, S_WQM_B64>;
def S_BREV_B32_vi : SOP1_Real_vi <0x08, S_BREV_B32>;
def S_BREV_B64_vi : SOP1_Real_vi <0x09, S_BREV_B64>;
def S_BCNT0_I32_B32_vi : SOP1_Real_vi <0x0a, S_BCNT0_I32_B32>;
def S_BCNT0_I32_B64_vi : SOP1_Real_vi <0x0b, S_BCNT0_I32_B64>;
def S_BCNT1_I32_B32_vi : SOP1_Real_vi <0x0c, S_BCNT1_I32_B32>;
def S_BCNT1_I32_B64_vi : SOP1_Real_vi <0x0d, S_BCNT1_I32_B64>;
def S_FF0_I32_B32_vi : SOP1_Real_vi <0x0e, S_FF0_I32_B32>;
def S_FF0_I32_B64_vi : SOP1_Real_vi <0x0f, S_FF0_I32_B64>;
def S_FF1_I32_B32_vi : SOP1_Real_vi <0x10, S_FF1_I32_B32>;
def S_FF1_I32_B64_vi : SOP1_Real_vi <0x11, S_FF1_I32_B64>;
def S_FLBIT_I32_B32_vi : SOP1_Real_vi <0x12, S_FLBIT_I32_B32>;
def S_FLBIT_I32_B64_vi : SOP1_Real_vi <0x13, S_FLBIT_I32_B64>;
def S_FLBIT_I32_vi : SOP1_Real_vi <0x14, S_FLBIT_I32>;
def S_FLBIT_I32_I64_vi : SOP1_Real_vi <0x15, S_FLBIT_I32_I64>;
def S_SEXT_I32_I8_vi : SOP1_Real_vi <0x16, S_SEXT_I32_I8>;
def S_SEXT_I32_I16_vi : SOP1_Real_vi <0x17, S_SEXT_I32_I16>;
def S_BITSET0_B32_vi : SOP1_Real_vi <0x18, S_BITSET0_B32>;
def S_BITSET0_B64_vi : SOP1_Real_vi <0x19, S_BITSET0_B64>;
def S_BITSET1_B32_vi : SOP1_Real_vi <0x1a, S_BITSET1_B32>;
def S_BITSET1_B64_vi : SOP1_Real_vi <0x1b, S_BITSET1_B64>;
def S_GETPC_B64_vi : SOP1_Real_vi <0x1c, S_GETPC_B64>;
def S_SETPC_B64_vi : SOP1_Real_vi <0x1d, S_SETPC_B64>;
def S_SWAPPC_B64_vi : SOP1_Real_vi <0x1e, S_SWAPPC_B64>;
def S_RFE_B64_vi : SOP1_Real_vi <0x1f, S_RFE_B64>;
def S_AND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x20, S_AND_SAVEEXEC_B64>;
def S_OR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x21, S_OR_SAVEEXEC_B64>;
def S_XOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x22, S_XOR_SAVEEXEC_B64>;
def S_ANDN2_SAVEEXEC_B64_vi: SOP1_Real_vi <0x23, S_ANDN2_SAVEEXEC_B64>;
def S_ORN2_SAVEEXEC_B64_vi : SOP1_Real_vi <0x24, S_ORN2_SAVEEXEC_B64>;
def S_NAND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x25, S_NAND_SAVEEXEC_B64>;
def S_NOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x26, S_NOR_SAVEEXEC_B64>;
def S_XNOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x27, S_XNOR_SAVEEXEC_B64>;
def S_QUADMASK_B32_vi : SOP1_Real_vi <0x28, S_QUADMASK_B32>;
def S_QUADMASK_B64_vi : SOP1_Real_vi <0x29, S_QUADMASK_B64>;
def S_MOVRELS_B32_vi : SOP1_Real_vi <0x2a, S_MOVRELS_B32>;
def S_MOVRELS_B64_vi : SOP1_Real_vi <0x2b, S_MOVRELS_B64>;
def S_MOVRELD_B32_vi : SOP1_Real_vi <0x2c, S_MOVRELD_B32>;
def S_MOVRELD_B64_vi : SOP1_Real_vi <0x2d, S_MOVRELD_B64>;
def S_CBRANCH_JOIN_vi : SOP1_Real_vi <0x2e, S_CBRANCH_JOIN>;
def S_MOV_REGRD_B32_vi : SOP1_Real_vi <0x2f, S_MOV_REGRD_B32>;
def S_ABS_I32_vi : SOP1_Real_vi <0x30, S_ABS_I32>;
def S_MOV_FED_B32_vi : SOP1_Real_vi <0x31, S_MOV_FED_B32>;
def S_ADD_U32_vi : SOP2_Real_vi <0x00, S_ADD_U32>;
def S_ADD_I32_vi : SOP2_Real_vi <0x02, S_ADD_I32>;
def S_SUB_U32_vi : SOP2_Real_vi <0x01, S_SUB_U32>;
def S_SUB_I32_vi : SOP2_Real_vi <0x03, S_SUB_I32>;
def S_ADDC_U32_vi : SOP2_Real_vi <0x04, S_ADDC_U32>;
def S_SUBB_U32_vi : SOP2_Real_vi <0x05, S_SUBB_U32>;
def S_MIN_I32_vi : SOP2_Real_vi <0x06, S_MIN_I32>;
def S_MIN_U32_vi : SOP2_Real_vi <0x07, S_MIN_U32>;
def S_MAX_I32_vi : SOP2_Real_vi <0x08, S_MAX_I32>;
def S_MAX_U32_vi : SOP2_Real_vi <0x09, S_MAX_U32>;
def S_CSELECT_B32_vi : SOP2_Real_vi <0x0a, S_CSELECT_B32>;
def S_CSELECT_B64_vi : SOP2_Real_vi <0x0b, S_CSELECT_B64>;
def S_AND_B32_vi : SOP2_Real_vi <0x0c, S_AND_B32>;
def S_AND_B64_vi : SOP2_Real_vi <0x0d, S_AND_B64>;
def S_OR_B32_vi : SOP2_Real_vi <0x0e, S_OR_B32>;
def S_OR_B64_vi : SOP2_Real_vi <0x0f, S_OR_B64>;
def S_XOR_B32_vi : SOP2_Real_vi <0x10, S_XOR_B32>;
def S_XOR_B64_vi : SOP2_Real_vi <0x11, S_XOR_B64>;
def S_ANDN2_B32_vi : SOP2_Real_vi <0x12, S_ANDN2_B32>;
def S_ANDN2_B64_vi : SOP2_Real_vi <0x13, S_ANDN2_B64>;
def S_ORN2_B32_vi : SOP2_Real_vi <0x14, S_ORN2_B32>;
def S_ORN2_B64_vi : SOP2_Real_vi <0x15, S_ORN2_B64>;
def S_NAND_B32_vi : SOP2_Real_vi <0x16, S_NAND_B32>;
def S_NAND_B64_vi : SOP2_Real_vi <0x17, S_NAND_B64>;
def S_NOR_B32_vi : SOP2_Real_vi <0x18, S_NOR_B32>;
def S_NOR_B64_vi : SOP2_Real_vi <0x19, S_NOR_B64>;
def S_XNOR_B32_vi : SOP2_Real_vi <0x1a, S_XNOR_B32>;
def S_XNOR_B64_vi : SOP2_Real_vi <0x1b, S_XNOR_B64>;
def S_LSHL_B32_vi : SOP2_Real_vi <0x1c, S_LSHL_B32>;
def S_LSHL_B64_vi : SOP2_Real_vi <0x1d, S_LSHL_B64>;
def S_LSHR_B32_vi : SOP2_Real_vi <0x1e, S_LSHR_B32>;
def S_LSHR_B64_vi : SOP2_Real_vi <0x1f, S_LSHR_B64>;
def S_ASHR_I32_vi : SOP2_Real_vi <0x20, S_ASHR_I32>;
def S_ASHR_I64_vi : SOP2_Real_vi <0x21, S_ASHR_I64>;
def S_BFM_B32_vi : SOP2_Real_vi <0x22, S_BFM_B32>;
def S_BFM_B64_vi : SOP2_Real_vi <0x23, S_BFM_B64>;
def S_MUL_I32_vi : SOP2_Real_vi <0x24, S_MUL_I32>;
def S_BFE_U32_vi : SOP2_Real_vi <0x25, S_BFE_U32>;
def S_BFE_I32_vi : SOP2_Real_vi <0x26, S_BFE_I32>;
def S_BFE_U64_vi : SOP2_Real_vi <0x27, S_BFE_U64>;
def S_BFE_I64_vi : SOP2_Real_vi <0x28, S_BFE_I64>;
def S_CBRANCH_G_FORK_vi : SOP2_Real_vi <0x29, S_CBRANCH_G_FORK>;
def S_ABSDIFF_I32_vi : SOP2_Real_vi <0x2a, S_ABSDIFF_I32>;
def S_MOVK_I32_vi : SOPK_Real_vi <0x00, S_MOVK_I32>;
def S_CMOVK_I32_vi : SOPK_Real_vi <0x01, S_CMOVK_I32>;
def S_CMPK_EQ_I32_vi : SOPK_Real_vi <0x02, S_CMPK_EQ_I32>;
def S_CMPK_LG_I32_vi : SOPK_Real_vi <0x03, S_CMPK_LG_I32>;
def S_CMPK_GT_I32_vi : SOPK_Real_vi <0x04, S_CMPK_GT_I32>;
def S_CMPK_GE_I32_vi : SOPK_Real_vi <0x05, S_CMPK_GE_I32>;
def S_CMPK_LT_I32_vi : SOPK_Real_vi <0x06, S_CMPK_LT_I32>;
def S_CMPK_LE_I32_vi : SOPK_Real_vi <0x07, S_CMPK_LE_I32>;
def S_CMPK_EQ_U32_vi : SOPK_Real_vi <0x08, S_CMPK_EQ_U32>;
def S_CMPK_LG_U32_vi : SOPK_Real_vi <0x09, S_CMPK_LG_U32>;
def S_CMPK_GT_U32_vi : SOPK_Real_vi <0x0A, S_CMPK_GT_U32>;
def S_CMPK_GE_U32_vi : SOPK_Real_vi <0x0B, S_CMPK_GE_U32>;
def S_CMPK_LT_U32_vi : SOPK_Real_vi <0x0C, S_CMPK_LT_U32>;
def S_CMPK_LE_U32_vi : SOPK_Real_vi <0x0D, S_CMPK_LE_U32>;
def S_ADDK_I32_vi : SOPK_Real_vi <0x0E, S_ADDK_I32>;
def S_MULK_I32_vi : SOPK_Real_vi <0x0F, S_MULK_I32>;
def S_CBRANCH_I_FORK_vi : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;
def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;
//def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
No newline at end of file