GlobalISel: implement low-level type suitable for MachineInstr selection

[t.p.northover]

Summary

In my first attempt at a legalization framework for GlobalISel (http://reviews.llvm.org/D21534), Quentin said he intended to move towards a lower-level type representation (essentially just size & lanes). Since the legalization description makes heavy use of types, it's probably best to do that earlier rather than later, hence this patch.

I've added a new LLT class, with 3 variants, designed to look similar to IR-level types:

• unsized for labels etc
• sN for scalars & aggregates.
• <N x sM> for vectors.

At the moment, vectors must contain more than 1 element (so no <1 x double>). I know there are doubts about this being adequate, but I'd like to press on as far as possible under the assumption that RegBankSelect can handle things and it's easier to relax that requirement than impose it later if we're wrong.

There should be no functional change here (we still don't have that much functionality to change!). Test changes are just updating to the new syntax.

Cheers.

Tim.

[qcolombet]

Hi Tim,

Looks pretty good to me.
I'd like to keep (at least for now), the type recording capabilities in register bank info though. I believe making a second constructor for LLT that takes SVT is going to be useful anyway.

Cheers,
-Quentin

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

107

We should be able to keep this functionality by providing a conversion from SVT to LLT, like we do for Type, right?

lib/CodeGen/LowLevelType.cpp

25

Don't you say we should allow <1 x Ty> kind of vector?
I do not see that here.

31

One thing to keep in mind is that, at some point, when we will want to do optimizations, we should have a way to know that the padding bits are garbage.
I do not expect this to be handle here, but I should think a way of rebuilding that information like computeKnownBits.

That will probably affect the legalization (expansion) of loads and stores when optimizations are set.

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

193

I guess we do not need that if we keep the types recording in RegisterBankInfo.

test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

72

Thanks for fixing the typo as well, I meant to do it at some point :P.

[t.p.northover]

I'd like to keep (at least for now), the type recording capabilities in register bank info though. I believe making a second constructor for LLT that takes SVT is going to be useful anyway.

I removed that reasonably late in development. Going from an SVT to an LLT is fine, the problem was that the only query of the information was based on a MachineInstr's (LLT) type which no longer has the information needed to choose a sane SVT. I suppose we could add some concept of a generic MachineInstr's "realm" (int/float) to provide the dropped info?

Tim.

lib/CodeGen/LowLevelType.cpp

25

Yep, discovered that myself while integrating this patch with my legalize things. I'll fix it in the updated version.

test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

72

Not entirely altruistic: it caused aborts with the new code.

[t.p.northover]

Only change in the end was enforcing no single-lane vectors in LLT::LLT (I think).

[eli.friedman]

include/llvm/CodeGen/LowLevelType.h

136

Should this work on a scalar type? (s32 -> <2 x s32>).

[qcolombet]

include/llvm/CodeGen/LowLevelType.h

56

Add a comment saying that NumElements must be > 1.

62

brif => brief

66

unsigned instead of int for NumElements and ScalarSizeInBits.

75

const &.
I assume we do not support nullptr.

83

Add a comment saying this should be call only for vector type.
/// \pre isVector() == true.

83

unsigned instead of int.

88

/// \pre isSized() == true.

98

/// \pre isVector() == true.

include/llvm/CodeGen/MachineInstr.h

28

The ifdef is probably useless.

[t.p.northover]

include/llvm/CodeGen/LowLevelType.h

83

I'll use a normal comment because "\pre" seems to be ignored by our documentation generator (and I prefer it).

136

For symmetry with halfElements, probably. It would make MoreElements also act as "Vectorize" in the same way FewerElements doubles as Scalarize which doesn't seem like a bad thing.

include/llvm/CodeGen/MachineInstr.h

28

Why? It seems rather weird to #ifdef the use of LLT but not its definition.

[t.p.northover]

Fix patch after Quentin & Matt's comments.

[t.p.northover]

Uploaded completely the wrong diff last time. This should fix it to what I intended.

[t.p.northover]

Ping?

[t.p.northover]

Updating diff. Very minor changes.

[qcolombet]

Hi Tim,

LGTM.

Thanks,
-Quentin

[t.p.northover]

Thanks Quentin, it's r276158.

include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
 #define LLVM_CODEGEN_GLOBALISEL_MACHINEIRBUILDER_H
 
 #include "llvm/CodeGen/GlobalISel/Types.h"
 
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/IR/DebugLoc.h"
 
 namespace llvm {
 
 // Forward declarations.
 class MachineFunction;
 class MachineInstr;
 class TargetInstrInfo;
public:
   /// does not describe a generic instruction.
   /// The insertion point is the one set by the last call of either
   /// setBasicBlock or setMI.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre Ty == nullptr or isPreISelGenericOpcode(Opcode)
   ///
   /// \return The newly created instruction.
-  MachineInstr *buildInstr(unsigned Opcode, Type *Ty);
+  MachineInstr *buildInstr(unsigned Opcode, LLT Ty);
 
   /// Build and insert <empty> = \p Opcode [\p Ty] \p BB.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre Ty == nullptr or isPreISelGenericOpcode(Opcode)
   ///
   /// \return The newly created instruction.
-  MachineInstr *buildInstr(unsigned Opcode, Type *Ty, MachineBasicBlock &BB);
+  MachineInstr *buildInstr(unsigned Opcode, LLT Ty, MachineBasicBlock &BB);
 
   /// Build and insert \p Res<def> = \p Opcode [\p Ty] \p Op0, \p Op1.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre Ty == nullptr or isPreISelGenericOpcode(Opcode)
   ///
   /// \return The newly created instruction.
-  MachineInstr *buildInstr(unsigned Opcode, Type *Ty, unsigned Res,
+  MachineInstr *buildInstr(unsigned Opcode, LLT Ty, unsigned Res,
                            unsigned Op0, unsigned Op1);
 
   /// Build and insert \p Res<def> = \p Opcode \p Op0, \p Op1.
   /// I.e., instruction with a non-generic opcode.
   ///
   /// \pre setBasicBlock or setMI must have been called.
   /// \pre not isPreISelGenericOpcode(\p Opcode)
   ///

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

public:
   };
 
 protected:
   /// Hold the set of supported register banks.
   std::unique_ptr<RegisterBank[]> RegBanks;
   /// Total number of register banks.
   unsigned NumRegBanks;
 
-  /// Mapping from MVT::SimpleValueType to register banks.
-  std::unique_ptr<const RegisterBank *[]> VTToRegBank;
-
   /// Create a RegisterBankInfo that can accomodate up to \p NumRegBanks
   /// RegisterBank instances.
   ///
   /// \note For the verify method to succeed all the \p NumRegBanks
   /// must be initialized by createRegisterBank and updated with
   /// addRegBankCoverage RegisterBank.
   RegisterBankInfo(unsigned NumRegBanks);
 
protected:
 
   /// Add \p RCId to the set of register class that the register bank,
   /// identified \p ID, covers.
   /// This method transitively adds all the sub classes and the subreg-classes
   /// of \p RCId to the set of covered register classes.
   /// It also adjusts the size of the register bank to reflect the maximal
   /// size of a value that can be hold into that register bank.
   ///
-  /// If \p AddTypeMapping is true, this method also records what types can
-  /// be mapped to \p ID. Although this done by default, targets may want to
-  /// disable it, espicially if a given type may be mapped on different
-  /// register bank. Indeed, in such case, this method only records the
-  /// first register bank where the type matches.
-  /// This information is only used to provide default mapping
-  /// (see getInstrMappingImpl).
-  ///
   /// \note This method does *not* add the super classes of \p RCId.
   /// The rationale is if \p ID covers the registers of \p RCId, that
   /// does not necessarily mean that \p ID covers the set of registers
   /// of RCId's superclasses.
   /// This method does *not* add the superreg classes as well for consistents.
   /// The expected use is to add the coverage top-down with respect to the
   /// register hierarchy.
   ///
   /// \todo TableGen should just generate the BitSet vector for us.
   void addRegBankCoverage(unsigned ID, unsigned RCId,
-                          const TargetRegisterInfo &TRI,
-                          bool AddTypeMapping = true);
+                          const TargetRegisterInfo &TRI);
 
   /// Get the register bank identified by \p ID.
   RegisterBank &getRegBank(unsigned ID) {
     assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
     return RegBanks[ID];
   }
 
-  /// Get the register bank that has been recorded to cover \p SVT.
-  const RegisterBank *getRegBankForType(MVT::SimpleValueType SVT) const {
-    if (!VTToRegBank)
-      return nullptr;
-    assert(SVT < MVT::SimpleValueType::LAST_VALUETYPE && "Out-of-bound access");
-    return VTToRegBank.get()[SVT];
-  }
-
-  /// Record \p RegBank as the register bank that covers \p SVT.
-  /// If a record was already set for \p SVT, the mapping is not
-  /// updated, unless \p Force == true
-  ///
-  /// \post if getRegBankForType(SVT)\@pre == nullptr then
-  ///                       getRegBankForType(SVT) == &RegBank
-  /// \post if Force == true then getRegBankForType(SVT) == &RegBank
-  void recordRegBankForType(const RegisterBank &RegBank,
-                            MVT::SimpleValueType SVT, bool Force = false) {
-    if (!VTToRegBank) {
-      VTToRegBank.reset(
-          new const RegisterBank *[MVT::SimpleValueType::LAST_VALUETYPE]);
-      std::fill(&VTToRegBank[0],
-                &VTToRegBank[MVT::SimpleValueType::LAST_VALUETYPE], nullptr);
-    }
-    assert(SVT < MVT::SimpleValueType::LAST_VALUETYPE && "Out-of-bound access");
-    // If we want to override the mapping or the mapping does not exits yet,
-    // set the register bank for SVT.
-    if (Force || !getRegBankForType(SVT))
-      VTToRegBank.get()[SVT] = &RegBank;
-  }
-
   /// Try to get the mapping of \p MI.
   /// See getInstrMapping for more details on what a mapping represents.
   ///
   /// Unlike getInstrMapping the returned InstructionMapping may be invalid
   /// (isValid() == false).
   /// This means that the target independent code is not smart enough
   /// to get the mapping of \p MI and thus, the target has to provide the
   /// information for \p MI.

include/llvm/CodeGen/LowLevelType.h

+//== llvm/CodeGen/GlobalISel/LowLevelType.h -------------------- -*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// Implement a low-level type suitable for MachineInstr level instruction
+/// selection.
+///
+/// For a type attached to a MachineInstr, we only care about 2 details: total
+/// size and the number of vector lanes (if any). Accordingly, there are 3
+/// possible valid type-kinds:
+///
+///    * `unsized` for labels etc
+///    * `sN` for scalars and aggregates
+///    * `<N x sM>` for vectors, which must have at least 2 elements.
+///
+/// Other information required for correct selection is expected to be carried
+/// by the opcode, or non-type flags. For example the distinction between G_ADD
+/// and G_FADD for int/float or fast-math flags.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_GLOBALISEL_LOWLEVELTYPE_H
+#define LLVM_CODEGEN_GLOBALISEL_LOWLEVELTYPE_H
+
+#include <cassert>
+#include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/CodeGen/ValueTypes.h"
+
+namespace llvm {
+
+class LLVMContext;
+class Type;
+class raw_ostream;
+
+class LLT {
+public:
+  enum TypeKind : uint16_t {
+    Invalid,
+    Scalar,
+    Vector,
+    Unsized,
+  };
+
+  /// \brief get a low-level scalar or aggregate "bag of bits".
+  static LLT scalar(int SizeInBits) {
+    return LLT{Scalar, 1, SizeInBits};
+  }
+
+  /// \brief get a low-level vector of some number of elements and element
+  /// width.
+  static LLT vector(int NumElements, int ScalarSizeInBits) {
+    assert(NumElements > 1 && "invalid number of vector elements");
+    return LLT{Vector, NumElements, ScalarSizeInBits};
+  }
+
+  /// \brif get an unsized but valid low-level type (e.g. for a label).
+  static LLT unsized() {
+    return LLT{Unsized, 1, 0};
+  }
+
+  explicit LLT(TypeKind Kind, int NumElements, int ScalarSizeInBits)
+    : ScalarSize(ScalarSizeInBits), NumElements(NumElements), Kind(Kind) {
+    assert((Kind != Vector || NumElements > 1) &&
+           "invalid number of vector elements");
+  }
+
+  explicit LLT() : ScalarSize(0), NumElements(0), Kind(Invalid) {}
+
+  /// \brief construct a low-level type based on an LLVM type.
+  explicit LLT(Type *Ty);
+
+  bool isValid() const { return Kind != Invalid; }
+
+  bool isVector() const { return Kind == Vector; }
+
+  bool isSized() const { return Kind == Scalar || Kind == Vector; }
+
+  int getNumElements() const {
+    assert(isVector() && "cannot get number of elements on scalar/aggregate");
+    return NumElements;
+  }
+
+  int getSizeInBits() const {
+    assert(isSized() && "attempt to get size of unsized type");
+    return ScalarSize * NumElements;
+  }
+
+  int getScalarSizeInBits() const {
+    assert(isSized() && "cannot get size of this type");
+    return ScalarSize;
+  }
+
+  LLT getElementType() const {
+    assert(isVector() && "cannot get element type of scalar/aggregate");
+    return scalar(ScalarSize);
+  }
+
+  /// \brief get a low-level type with half the size of the original, by halving
+  /// the size of the scalar type involved. For example `s32` will become
+  /// `s16`, `<2 x s32>` will become `<2 x s16>`.
+  LLT halfScalarSize() const {
+    assert(isSized() && "cannot change size of this type");
+    return LLT{Kind, NumElements, ScalarSize / 2};
+  }
+
+  /// \brief get a low-level type with twice the size of the original, by
+  /// doubling the size of the scalar type involved. For example `s32` will
+  /// become `s64`, `<2 x s32>` will become `<2 x s64>`.
+  LLT doubleScalarSize() const {
+    assert(isSized() && "cannot change size of this type");
+    return LLT{Kind, NumElements, ScalarSize * 2};
+  }
+
+  /// \brief get a low-level type with half the size of the original, by halving
+  /// the number of vector elements of the scalar type involved. The source must
+  /// be a vector type with an even number of elements. For example `<4 x
+  /// s32>` will become `<2 x s32>`, `<2 x s32>` will become `s32`.
+  LLT halfElements() const {
+    assert(isVector() && NumElements % 2 == 0 && "cannot half odd vector");
+    if (NumElements == 2)
+      return scalar(ScalarSize);
+
+    return LLT{Vector, NumElements / 2, ScalarSize};
+  }
+
+  /// \brief get a low-level type with twice the size of the original, by
+  /// doubling the number of vector elements of the scalar type involved. The
+  /// source must be a vector type. For example `<2 x s32>` will become `<4 x
+  /// s32>`.
+  LLT doubleElements() const {
+    assert(isVector());
+    return LLT{Kind, NumElements * 2, ScalarSize};
+  }
+
+  void print(raw_ostream &OS) const;
+
+  bool operator ==(const LLT &RHS) const {
+    return Kind == RHS.Kind && ScalarSize == RHS.ScalarSize &&
+           NumElements == RHS.NumElements;
+  }
+
+  friend struct DenseMapInfo<LLT>;
+private:
+  int ScalarSize;
+  int16_t NumElements;
+  TypeKind Kind;
+};
+
+template<> struct DenseMapInfo<LLT> {
+  static inline LLT getEmptyKey() {
+    return LLT{LLT::Invalid, 0, -1};
+  }
+  static inline LLT getTombstoneKey() {
+    return LLT{LLT::Invalid, 0, -2};
+  }
+  static inline unsigned getHashValue(const LLT &Ty) {
+    uint64_t Val = ((uint64_t)Ty.ScalarSize << 32) |
+                   ((uint64_t)Ty.NumElements << 16) | (uint64_t)Ty.Kind;
+    return DenseMapInfo<uint64_t>::getHashValue(Val);
+  }
+  static bool isEqual(const LLT &LHS, const LLT &RHS) {
+    return LHS == RHS;
+  }
+};
+
+}
+
+#endif

include/llvm/CodeGen/MachineInstr.h

 
 #include "llvm/ADT/DenseMapInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/ilist.h"
 #include "llvm/ADT/ilist_node.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#ifdef LLVM_BUILD_GLOBAL_ISEL
+#include "llvm/CodeGen/LowLevelType.h"
+#endif
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/InlineAsm.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/ArrayRecycler.h"
 #include "llvm/Target/TargetOpcodes.h"
 
 namespace llvm {
 
 class StringRef;
 template <typename T> class ArrayRef;
 template <typename T> class SmallVectorImpl;
 class DILocalVariable;
 class DIExpression;
 class TargetInstrInfo;
 class TargetRegisterClass;
 class TargetRegisterInfo;
-#ifdef LLVM_BUILD_GLOBAL_ISEL
-class Type;
-#endif
 class MachineFunction;
 class MachineMemOperand;
 
 //===----------------------------------------------------------------------===//
 /// Representation of each machine instruction.
 ///
 /// This class isn't a POD type, but it must have a trivial destructor. When a
 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
private:
   // that this is a non-owning reference to a shared copy on write buffer owned
   // by the MachineFunction and created via MF.allocateMemRefsArray.
   mmo_iterator MemRefs;
 
   DebugLoc debugLoc;                    // Source line information.
 
 #ifdef LLVM_BUILD_GLOBAL_ISEL
   /// Type of the instruction in case of a generic opcode.
-  /// \invariant This must be nullptr is getOpcode() is not
+  /// \invariant This must be LLT{} if getOpcode() is not
   /// in the range of generic opcodes.
-  Type *Ty;
+  LLT Ty;
 #endif
 
   MachineInstr(const MachineInstr&) = delete;
   void operator=(const MachineInstr&) = delete;
   // Use MachineFunction::DeleteMachineInstr() instead.
   ~MachineInstr() = delete;
 
   // Intrusive list support
public:
 
   /// clearFlag - Clear a MI flag.
   void clearFlag(MIFlag Flag) {
     Flags &= ~((uint8_t)Flag);
   }
 
   /// Set the type of the instruction.
   /// \pre getOpcode() is in the range of the generic opcodes.
-  void setType(Type *Ty);
-  Type *getType() const;
+  void setType(LLT Ty);
+  LLT getType() const;
 
   /// Return true if MI is in a bundle (but not the first MI in a bundle).
   ///
   /// A bundle looks like this before it's finalized:
   ///   ----------------
   ///   |      MI      |
   ///   ----------------
   ///          |

lib/CodeGen/CMakeLists.txt

add_llvm_library(LLVMCodeGen
   LivePhysRegs.cpp
   LiveRangeCalc.cpp
   LiveRangeEdit.cpp
   LiveRegMatrix.cpp
   LiveStackAnalysis.cpp
   LiveVariables.cpp
   LLVMTargetMachine.cpp
   LocalStackSlotAllocation.cpp
+  LowLevelType.cpp
   LowerEmuTLS.cpp
   MachineBasicBlock.cpp
   MachineBlockFrequencyInfo.cpp
   MachineBlockPlacement.cpp
   MachineBranchProbabilityInfo.cpp
   MachineCombiner.cpp
   MachineCopyPropagation.cpp
   MachineCSE.cpp

lib/CodeGen/GlobalISel/IRTranslator.cpp

 bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
   // Get or create a virtual register for each value.
   // Unless the value is a Constant => loadimm cst?
   // or inline constant each time?
   // Creation of a virtual register needs to have a size.
   unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
   unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
   unsigned Res = getOrCreateVReg(Inst);
-  MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1);
+  MIRBuilder.buildInstr(Opcode, LLT{Inst.getType()}, Res, Op0, Op1);
   return true;
 }
 
 bool IRTranslator::translateReturn(const Instruction &Inst) {
   assert(isa<ReturnInst>(Inst) && "Return expected");
   const Value *Ret = cast<ReturnInst>(Inst).getReturnValue();
   // The target may mess up with the insertion point, but
   // this is not important as a return is the last instruction
   // of the block anyway.
   return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
 }
 
 bool IRTranslator::translateBr(const Instruction &Inst) {
   assert(isa<BranchInst>(Inst) && "Branch expected");
   const BranchInst &BrInst = *cast<BranchInst>(&Inst);
   if (BrInst.isUnconditional()) {
     const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getOperand(0));
     MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
-    MIRBuilder.buildInstr(TargetOpcode::G_BR, BrTgt.getType(), TgtBB);
+    MIRBuilder.buildInstr(TargetOpcode::G_BR, LLT{BrTgt.getType()}, TgtBB);
   } else {
     assert(0 && "Not yet implemented");
   }
   // Link successors.
   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
   for (const BasicBlock *Succ : BrInst.successors())
     CurBB.addSuccessor(&getOrCreateBB(*Succ));
   return true;

lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

if (MI) {
     return MI->getNextNode();
   }
   return Before ? getMBB().begin() : getMBB().end();
 }
 
 //------------------------------------------------------------------------------
 // Build instruction variants.
 //------------------------------------------------------------------------------
-MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty) {
+MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty) {
   MachineInstr *NewMI = BuildMI(getMF(), DL, getTII().get(Opcode));
-  if (Ty) {
+  if (Ty.isValid()) {
     assert(isPreISelGenericOpcode(Opcode) &&
            "Only generic instruction can have a type");
     NewMI->setType(Ty);
   } else
     assert(!isPreISelGenericOpcode(Opcode) &&
            "Generic instruction must have a type");
   getMBB().insert(getInsertPt(), NewMI);
   return NewMI;
 }
 
 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res,
                                            unsigned Op0, unsigned Op1) {
-  return buildInstr(Opcode, nullptr, Res, Op0, Op1);
+  return buildInstr(Opcode, LLT{}, Res, Op0, Op1);
 }
 
-MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty,
+MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty,
                                            unsigned Res, unsigned Op0,
                                            unsigned Op1) {
   MachineInstr *NewMI = buildInstr(Opcode, Ty);
   MachineInstrBuilder(getMF(), NewMI)
       .addReg(Res, RegState::Define)
       .addReg(Op0)
       .addReg(Op1);
   return NewMI;
 }
 
 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res,
                                            unsigned Op0) {
-  MachineInstr *NewMI = buildInstr(Opcode, nullptr);
+  MachineInstr *NewMI = buildInstr(Opcode, LLT{});
   MachineInstrBuilder(getMF(), NewMI).addReg(Res, RegState::Define).addReg(Op0);
   return NewMI;
 }
 
 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) {
-  return buildInstr(Opcode, nullptr);
+  return buildInstr(Opcode, LLT{});
 }
 
-MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty,
+MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty,
                                            MachineBasicBlock &BB) {
   MachineInstr *NewMI = buildInstr(Opcode, Ty);
   MachineInstrBuilder(getMF(), NewMI).addMBB(&BB);
   return NewMI;
 }

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

void RegisterBankInfo::createRegisterBank(unsigned ID, const char *Name) {
   RegisterBank &RegBank = getRegBank(ID);
   assert(RegBank.getID() == RegisterBank::InvalidID &&
          "A register bank should be created only once");
   RegBank.ID = ID;
   RegBank.Name = Name;
 }
 
 void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
-                                          const TargetRegisterInfo &TRI,
-                                          bool AddTypeMapping) {
+                                          const TargetRegisterInfo &TRI) {
   RegisterBank &RB = getRegBank(ID);
   unsigned NbOfRegClasses = TRI.getNumRegClasses();
 
   DEBUG(dbgs() << "Add coverage for: " << RB << '\n');
 
   // Check if RB is underconstruction.
   if (!RB.isValid())
     RB.ContainedRegClasses.resize(NbOfRegClasses);
do {
     const TargetRegisterClass &CurRC = *TRI.getRegClass(RCId);
 
     DEBUG(dbgs() << "Examine: " << TRI.getRegClassName(&CurRC)
                  << "(Size*8: " << (CurRC.getSize() * 8) << ")\n");
 
     // Remember the biggest size in bits.
     MaxSize = std::max(MaxSize, CurRC.getSize() * 8);
 
-    // If we have been asked to record the type supported by this
-    // register bank, do it now.
-    if (AddTypeMapping)
-      for (MVT::SimpleValueType SVT :
-           make_range(CurRC.vt_begin(), CurRC.vt_end()))
-        recordRegBankForType(getRegBank(ID), SVT);
-
     // Walk through all sub register classes and push them into the worklist.
     bool First = true;
     for (BitMaskClassIterator It(CurRC.getSubClassMask(), TRI); It.isValid();
          ++It) {
       unsigned SubRCId = It.getID();
       if (!Covered.test(SubRCId)) {
         if (First)
           DEBUG(dbgs() << "  Enqueue sub-class: ");
for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) {
     // that is already set on Reg, if any, since those instructions do
     // not have any constraints.
     const RegisterBank *CurRegBank = isCopyLike ? AltRegBank : nullptr;
     if (!CurRegBank) {
       // If this is a target specific instruction, we can deduce
       // the register bank from the encoding constraints.
       CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI);
       if (!CurRegBank) {
-        // Check if we can deduce the register bank from the type of
-        // the instruction.
-        Type *MITy = MI.getType();
-        if (MITy)
-          CurRegBank = getRegBankForType(
-              MVT::getVT(MITy, /*HandleUnknown*/ true).SimpleTy);
-        if (!CurRegBank)
-          // Use the current assigned register bank.
-          // That may not make much sense though.
-          CurRegBank = AltRegBank;
-        if (!CurRegBank) {
-          // All our attempts failed, give up.
-          CompleteMapping = false;
 
-          if (!isCopyLike)
-            // MI does not carry enough information to guess the mapping.
-            return InstructionMapping();
 
-          // For copies, we want to keep interating to find a register
-          // bank for the other operands if we did not find one yet.
-          if (RegBank)
-            break;
-          continue;
-        }
-      }
-    }
     RegBank = CurRegBank;
     RegSize = getSizeInBits(Reg, MRI, TRI);
     Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank);
   }
 
   if (CompleteMapping)
     return Mapping;
 

lib/CodeGen/LowLevelType.cpp

+//===-- llvm/CodeGen/GlobalISel/LowLevelType.cpp --------------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file This file implements the more header-heavy bits of the LLT class to
+/// avoid polluting users' namespaces.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/LowLevelType.h"
+#include "llvm/IR/DerivedTypes.h"
+#include "llvm/Support/raw_ostream.h"
+using namespace llvm;
+
+LLT::LLT(Type *Ty) {
+  if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
+    ScalarSize = VTy->getElementType()->getPrimitiveSizeInBits();
+    NumElements = VTy->getNumElements();
+    Kind = NumElements == 1 ? Scalar : Vector;
+  } else if (Ty->isSized()) {
+    // Aggregates are no different from real scalars as far as GlobalISel is
+    // concerned.
+    Kind = Scalar;
+    ScalarSize = Ty->getPrimitiveSizeInBits();
+    NumElements = 1;
+  } else {
+    Kind = Unsized;
+    ScalarSize = NumElements = 0;
+  }
+}
+
+void LLT::print(raw_ostream &OS) const {
+  if (isVector())
+    OS << "<" << NumElements << " x s" << ScalarSize << ">";
+  else if (isSized())
+    OS << "s" << ScalarSize;
+  else if (isValid())
+    OS << "unsized";
+  else
+    llvm_unreachable("trying to print an invalid type");
+}

lib/CodeGen/MIRParser/MILexer.h

enum TokenKind {
     md_range,
 
     // Identifier tokens
     Identifier,
     IntegerType,
     NamedRegister,
     MachineBasicBlockLabel,
     MachineBasicBlock,
+    ScalarType,
     StackObject,
     FixedStackObject,
     NamedGlobalValue,
     GlobalValue,
     ExternalSymbol,
 
     // Other tokens
     IntegerLiteral,

lib/CodeGen/MIRParser/MILexer.cpp

static Cursor lexName(Cursor C, MIToken &Token, MIToken::TokenKind Type,
   }
   while (isIdentifierChar(C.peek()))
     C.advance();
   Token.reset(Type, Range.upto(C))
       .setStringValue(Range.upto(C).drop_front(PrefixLength));
   return C;
 }
 
-static Cursor maybeLexIntegerType(Cursor C, MIToken &Token) {
-  if (C.peek() != 'i' || !isdigit(C.peek(1)))
+static Cursor maybeLexIntegerOrScalarType(Cursor C, MIToken &Token) {
+  if ((C.peek() != 'i' && C.peek() != 's') || !isdigit(C.peek(1)))
     return None;
+  char Kind = C.peek();
   auto Range = C;
   C.advance(); // Skip 'i'
   while (isdigit(C.peek()))
     C.advance();
-  Token.reset(MIToken::IntegerType, Range.upto(C));
+  Token.reset(Kind == 'i' ? MIToken::IntegerType : MIToken::ScalarType,
+              Range.upto(C));
   return C;
 }
 
 static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
   return StringSwitch<MIToken::TokenKind>(Identifier)
       .Case("_", MIToken::underscore)
       .Case("implicit", MIToken::kw_implicit)
       .Case("implicit-def", MIToken::kw_implicit_define)

 StringRef llvm::lexMIToken(StringRef Source, MIToken &Token,
                            ErrorCallbackType ErrorCallback) {
   auto C = skipComment(skipWhitespace(Cursor(Source)));
   if (C.isEOF()) {
     Token.reset(MIToken::Eof, C.remaining());
     return C.remaining();
   }
 
-  if (Cursor R = maybeLexIntegerType(C, Token))
+  if (Cursor R = maybeLexIntegerOrScalarType(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback))
     return R.remaining();
   if (Cursor R = maybeLexIdentifier(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexJumpTableIndex(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexStackObject(C, Token))

lib/CodeGen/MIRParser/MIParser.cpp

public:
   bool parseRegisterTiedDefIndex(unsigned &TiedDefIdx);
   bool parseSize(unsigned &Size);
   bool parseRegisterOperand(MachineOperand &Dest,
                             Optional<unsigned> &TiedDefIdx, bool IsDef = false);
   bool parseImmediateOperand(MachineOperand &Dest);
   bool parseIRConstant(StringRef::iterator Loc, StringRef Source,
                        const Constant *&C);
   bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
-  bool parseIRType(StringRef::iterator Loc, StringRef Source, unsigned &Read,
-                   Type *&Ty);
-  // \p MustBeSized defines whether or not \p Ty must be sized.
-  bool parseIRType(StringRef::iterator Loc, Type *&Ty, bool MustBeSized = true);
+  bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty, bool MustBeSized);
   bool parseTypedImmediateOperand(MachineOperand &Dest);
   bool parseFPImmediateOperand(MachineOperand &Dest);
   bool parseMBBReference(MachineBasicBlock *&MBB);
   bool parseMBBOperand(MachineOperand &Dest);
   bool parseStackFrameIndex(int &FI);
   bool parseStackObjectOperand(MachineOperand &Dest);
   bool parseFixedStackFrameIndex(int &FI);
   bool parseFixedStackObjectOperand(MachineOperand &Dest);
bool MIParser::parse(MachineInstr *&MI) {
   }
   if (!Operands.empty() && expectAndConsume(MIToken::equal))
     return true;
 
   unsigned OpCode, Flags = 0;
   if (Token.isError() || parseInstruction(OpCode, Flags))
     return true;
 
-  Type *Ty = nullptr;
+  LLT Ty{};
   if (isPreISelGenericOpcode(OpCode)) {
     // For generic opcode, a type is mandatory.
     auto Loc = Token.location();
-    if (parseIRType(Loc, Ty))
+    if (parseLowLevelType(Loc, Ty, true))
       return true;
   }
 
   // Parse the remaining machine operands.
   while (!Token.isNewlineOrEOF() && Token.isNot(MIToken::kw_debug_location) &&
          Token.isNot(MIToken::coloncolon) && Token.isNot(MIToken::lbrace)) {
     auto Loc = Token.location();
     Optional<unsigned> TiedDefIdx;
if (!MCID.isVariadic()) {
     // FIXME: Move the implicit operand verification to the machine verifier.
     if (verifyImplicitOperands(Operands, MCID))
       return true;
   }
 
   // TODO: Check for extraneous machine operands.
   MI = MF.CreateMachineInstr(MCID, DebugLocation, /*NoImplicit=*/true);
   MI->setFlags(Flags);
-  if (Ty)
+  if (Ty.isValid())
     MI->setType(Ty);
   for (const auto &Operand : Operands)
     MI->addOperand(MF, Operand.Operand);
   if (assignRegisterTies(*MI, Operands))
     return true;
   if (MemOperands.empty())
     return false;
   MachineInstr::mmo_iterator MemRefs =

 
 bool MIParser::parseIRConstant(StringRef::iterator Loc, const Constant *&C) {
   if (parseIRConstant(Loc, StringRef(Loc, Token.range().end() - Loc), C))
     return true;
   lex();
   return false;
 }
 
-bool MIParser::parseIRType(StringRef::iterator Loc, StringRef StringValue,
-                           unsigned &Read, Type *&Ty) {
-  auto Source = StringValue.str(); // The source has to be null terminated.
-  SMDiagnostic Err;
-  Ty = parseTypeAtBeginning(Source.c_str(), Read, Err,
-                            *MF.getFunction()->getParent(), &IRSlots);
-  if (!Ty)
-    return error(Loc + Err.getColumnNo(), Err.getMessage());
+bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty,
+                                 bool MustBeSized) {
+  if (Token.is(MIToken::Identifier) && Token.stringValue() == "unsized") {
+    if (MustBeSized)
+      return error("expected sN or <N x sM> for sized GlobalISel type");
+    lex();
+    Ty = LLT::unsized();
+    return false;
+  } else if (Token.is(MIToken::ScalarType)) {
+    Ty = LLT::scalar(APSInt(Token.range().drop_front()).getZExtValue());
+    lex();
     return false;
   }
 
-bool MIParser::parseIRType(StringRef::iterator Loc, Type *&Ty,
-                           bool MustBeSized) {
-  // At this point we enter in the IR world, i.e., to get the correct type,
-  // we need to hand off the whole string, not just the current token.
-  // E.g., <4 x i64> would give '<' as a token and there is not much
-  // the IR parser can do with that.
-  unsigned Read = 0;
-  if (parseIRType(Loc, StringRef(Loc), Read, Ty))
-    return true;
-  // The type must be sized, otherwise there is not much the backend
-  // can do with it.
-  if (MustBeSized && !Ty->isSized())
-    return error("expected a sized type");
-  // The next token is Read characters from the Loc.
-  // However, the current location is not Loc, but Loc + the length of Token.
-  // Therefore, subtract the length of Token (range().end() - Loc) to the
-  // number of characters to skip before the next token.
-  lex(Read - (Token.range().end() - Loc));
+  // Now we're looking for a vector.
+  if (Token.isNot(MIToken::less))
+    return error(Loc, "expected unsized, sN or <N x sM> for GlobalISel type");
+  lex();
+
+  if (Token.isNot(MIToken::IntegerLiteral))
+    return error(Loc, "expected <N x sM> for vctor type");
+  uint64_t NumElements = Token.integerValue().getZExtValue();
+  lex();
+
+  if (Token.isNot(MIToken::Identifier) || Token.stringValue() != "x")
+    return error(Loc, "expected '<N x sM>' for vector type");
+  lex();
+
+  if (Token.isNot(MIToken::ScalarType))
+    return error(Loc, "expected '<N x sM>' for vector type");
+  uint64_t ScalarSize = APSInt(Token.range().drop_front()).getZExtValue();
+  lex();
+
+  if (Token.isNot(MIToken::greater))
+    return error(Loc, "expected '<N x sM>' for vector type");
+  lex();
+
+  Ty = LLT::vector(NumElements, ScalarSize);
   return false;
 }
 
 bool MIParser::parseTypedImmediateOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::IntegerType));
   auto Loc = Token.location();
   lex();
   if (Token.isNot(MIToken::IntegerLiteral))

lib/CodeGen/MIRPrinter.cpp

void MIPrinter::print(const MachineInstr &MI) {
   }
 
   if (I)
     OS << " = ";
   if (MI.getFlag(MachineInstr::FrameSetup))
     OS << "frame-setup ";
   OS << TII->getName(MI.getOpcode());
   if (isPreISelGenericOpcode(MI.getOpcode())) {
-    assert(MI.getType() && "Generic instructions must have a type");
+    assert(MI.getType().isValid() && "Generic instructions must have a type");
     OS << ' ';
-    MI.getType()->print(OS, /*IsForDebug*/ false, /*NoDetails*/ true);
+    MI.getType().print(OS);
   }
   if (I < E)
     OS << ' ';
 
   bool NeedComma = false;
   for (; I < E; ++I) {
     if (NeedComma)
       OS << ", ";

lib/CodeGen/MachineInstr.cpp

 /// the MCInstrDesc.
 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
                            DebugLoc dl, bool NoImp)
     : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
       AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
       debugLoc(std::move(dl))
 #ifdef LLVM_BUILD_GLOBAL_ISEL
       ,
-      Ty(nullptr)
+      Ty(LLT{})
 #endif
 {
   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
 
   // Reserve space for the expected number of operands.
   if (unsigned NumOps = MCID->getNumOperands() +
     MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
     CapOperands = OperandCapacity::get(NumOps);
     Operands = MF.allocateOperandArray(CapOperands);
   }
 
   if (!NoImp)
     addImplicitDefUseOperands(MF);
 }
 
 /// MachineInstr ctor - Copies MachineInstr arg exactly
 ///
 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
     : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
       Flags(0), AsmPrinterFlags(0), NumMemRefs(MI.NumMemRefs),
       MemRefs(MI.MemRefs), debugLoc(MI.getDebugLoc())
 #ifdef LLVM_BUILD_GLOBAL_ISEL
       ,
-      Ty(nullptr)
+      Ty(LLT{})
 #endif
 {
   assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
 
   CapOperands = OperandCapacity::get(MI.getNumOperands());
   Operands = MF.allocateOperandArray(CapOperands);
 
   // Copy operands.
MachineRegisterInfo *MachineInstr::getRegInfo() {
   return nullptr;
 }
 
 // Implement dummy setter and getter for type when
 // global-isel is not built.
 // The proper implementation is WIP and is tracked here:
 // PR26576.
 #ifndef LLVM_BUILD_GLOBAL_ISEL
-void MachineInstr::setType(Type *Ty) {}
+void MachineInstr::setType(LLT Ty) {}
 
-Type *MachineInstr::getType() const { return nullptr; }
+LLT MachineInstr::getType() const { return LLT{}; }
 
 #else
-void MachineInstr::setType(Type *Ty) {
-  assert((!Ty || isPreISelGenericOpcode(getOpcode())) &&
+void MachineInstr::setType(LLT Ty) {
+  assert((!Ty.isValid() || isPreISelGenericOpcode(getOpcode())) &&
          "Non generic instructions are not supposed to be typed");
   this->Ty = Ty;
 }
 
-Type *MachineInstr::getType() const { return Ty; }
+LLT MachineInstr::getType() const { return Ty; }
 #endif // LLVM_BUILD_GLOBAL_ISEL
 
 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
 /// this instruction from their respective use lists.  This requires that the
 /// operands already be on their use lists.
 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
   for (MachineOperand &MO : operands())
     if (MO.isReg())
if (StartOp != 0)
     OS << " = ";
 
   // Print the opcode name.
   if (TII)
     OS << TII->getName(getOpcode());
   else
     OS << "UNKNOWN";
 
-  if (getType()) {
+  if (getType().isValid()) {
     OS << ' ';
-    getType()->print(OS, /*IsForDebug*/ false, /*NoDetails*/ true);
+    getType().print(OS);
     OS << ' ';
   }
 
   if (SkipOpers)
     return;
 
   // Print the rest of the operands.
   bool OmittedAnyCallClobbers = false;

lib/Target/AArch64/AArch64RegisterBankInfo.h

public:
   /// \todo This should be TableGen'ed.
   const RegisterBank &
   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 
   /// Get the alternative mappings for \p MI.
   /// Alternative in the sense different from getInstrMapping.
   InstructionMappings
   getInstrAlternativeMappings(const MachineInstr &MI) const override;
+
+  InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
 };
 } // End llvm namespace.
 #endif

lib/Target/AArch64/AArch64RegisterBankInfo.cpp

default:
     break;
   }
   return RegisterBankInfo::getInstrAlternativeMappings(MI);
 }
 
 void AArch64RegisterBankInfo::applyMappingImpl(
     const OperandsMapper &OpdMapper) const {
   switch (OpdMapper.getMI().getOpcode()) {
+  case TargetOpcode::G_ADD:
   case TargetOpcode::G_OR: {
     // Those ID must match getInstrAlternativeMappings.
     assert((OpdMapper.getInstrMapping().getID() == 1 ||
             OpdMapper.getInstrMapping().getID() == 2) &&
            "Don't know how to handle that ID");
     return applyDefaultMapping(OpdMapper);
   }
   default:
     llvm_unreachable("Don't know how to handle that operation");
   }
 }
+
+RegisterBankInfo::InstructionMapping
+AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
+  if (Mapping.isValid())
+    return Mapping;
+
+  // As a top-level guess, vectors go in FPRs, scalars in GPRs. Obviously this
+  // won't work for normal floating-point types (or NZCV). When such
+  // instructions exist we'll need to look at the MI's opcode.
+  LLT Ty = MI.getType();
+  unsigned BankID;
+  if (Ty.isVector())
+    BankID = AArch64::FPRRegBankID;
+  else
+    BankID = AArch64::GPRRegBankID;
+
+  Mapping = InstructionMapping{1, 1, MI.getNumOperands()};
+  int Size = Ty.isSized() ? Ty.getSizeInBits() : 0;
+  for (unsigned Idx = 0; Idx < MI.getNumOperands(); ++Idx)
+    Mapping.setOperandMapping(Idx, Size, getRegBank(BankID));
+
+  return Mapping;
+}

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 ; RUN: llc -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
 ; REQUIRES: global-isel
 ; This file checks that the translation from llvm IR to generic MachineInstr
 ; is correct.
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-apple-ios"
 
 ; Tests for add.
 ; CHECK: name: addi64
 ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD i64 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD s64 [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0 
 define i64 @addi64(i64 %arg1, i64 %arg2) {
   %res = add i64 %arg1, %arg2
   ret i64 %res
 }
 
 ; Tests for br.
 ; CHECK: name: uncondbr
 ; CHECK: body:
 ;
 ; Entry basic block.
 ; CHECK: {{[0-9a-zA-Z._-]+}}:
 ;
 ; Make sure we have one successor and only one.
 ; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]]({{0x[a-f0-9]+ / 0x[a-f0-9]+}} = 100.00%)
 ;
 ; Check that we emit the correct branch.
-; CHECK: G_BR label %[[END]]
+; CHECK: G_BR unsized %[[END]]
 ;
 ; Check that end contains the return instruction.
 ; CHECK: [[END]]:
 ; CHECK-NEXT: RET_ReallyLR
 define void @uncondbr() {
   br label %end
 end:
   ret void
 }
 
 ; Tests for or.
 ; CHECK: name: ori64
 ; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1
-; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR i64 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR s64 [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %x0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %x0
 define i64 @ori64(i64 %arg1, i64 %arg2) {
   %res = or i64 %arg1, %arg2
   ret i64 %res
 }
 
 ; CHECK: name: ori32
 ; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0
 ; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1
-; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR i32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR s32 [[ARG1]], [[ARG2]]
 ; CHECK-NEXT: %w0 = COPY [[RES]]
 ; CHECK-NEXT: RET_ReallyLR implicit %w0
 define i32 @ori32(i32 %arg1, i32 %arg2) {
   %res = or i32 %arg1, %arg2
   ret i32 %res
 }

test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     liveins: %x0
-    ; CHECK:      %0(32) = G_ADD i32 %x0
-    %0(32) = G_ADD i32 %x0, %x0
+    ; CHECK:      %0(32) = G_ADD s32 %w0
+    %0(32) = G_ADD s32 %w0, %w0
 ...
 
 ---
 # Check that we assign a relevant register bank for %0.
 # Based on the type <2 x i32>, this should be fpr.
 # FPR is used for both floating point and vector registers.
 name:            defaultMappingVector
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: fpr }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     liveins: %d0
-    ; CHECK:      %0(32) = G_ADD <2 x i32> %d0
-    %0(32) = G_ADD <2 x i32> %d0, %d0
+    ; CHECK:      %0(64) = G_ADD <2 x s32> %d0
+    %0(64) = G_ADD <2 x s32> %d0, %d0
 ...
 
 ---
 # Check that we repair the assignment for %0.
 # Indeed based on the source of the copy it should live
 # in FPR, but at the use, it should be GPR.
 name:            defaultMapping1Repair
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: fpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
     ; CHECK:           %0(32) = COPY %s0
     ; CHECK-NEXT:      %2(32) = COPY %0
-    ; CHECK-NEXT:      %1(32) = G_ADD i32 %2, %x0
+    ; CHECK-NEXT:      %1(32) = G_ADD s32 %2, %w0
     %0(32) = COPY %s0
-    %1(32) = G_ADD i32 %0, %x0
+    %1(32) = G_ADD s32 %0, %w0
 ...
 
 # Check that we repair the assignment for %0 differently for both uses.
 name:            defaultMapping2Repairs
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: fpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 # CHECK-NEXT:   - { id: 3, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %s0, %x0
     ; CHECK:           %0(32) = COPY %s0
     ; CHECK-NEXT:      %2(32) = COPY %0
     ; CHECK-NEXT:      %3(32) = COPY %0
-    ; CHECK-NEXT:      %1(32) = G_ADD i32 %2, %3
+    ; CHECK-NEXT:      %1(32) = G_ADD s32 %2, %3
     %0(32) = COPY %s0
-    %1(32) = G_ADD i32 %0, %0
+    %1(32) = G_ADD s32 %0, %0
 ...
 
 ---
 # Check that we repair the definition of %1.
 # %1 is forced to be into FPR, but its definition actually
 # requires that it lives in GPR. Make sure regbankselect
 # fixes that.
 name:            defaultMappingDefRepair
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 # CHECK-NEXT:   - { id: 1, class: fpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: fpr }
 body: |
   bb.0.entry:
     liveins: %w0
     ; CHECK:           %0(32) = COPY %w0
-    ; CHECK-NEXT:      %2(32) = G_ADD i32 %0, %w0
+    ; CHECK-NEXT:      %2(32) = G_ADD s32 %0, %w0
     ; CHECK-NEXT:      %1(32) = COPY %2
     %0(32) = COPY %w0
-    %1(32) = G_ADD i32 %0, %w0
+    %1(32) = G_ADD s32 %0, %w0
 ...
 
 ---
 # Check that we are able to propagate register banks from phis.
 name:            phiPropagation
 isSSA:           true
 tracksRegLiveness:   true
 # CHECK:      registers:
bb.0.entry:
   
     %0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src)
     %1 = COPY %x1
     %2 = COPY %w2
     TBNZW killed %2, 0, %bb.2.end
   
   bb.1.then:
     successors: %bb.2.end
-    %3(32) = G_ADD i32 %0, %0
+    %3(32) = G_ADD s32 %0, %0
   
   bb.2.end:
     %4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then
     STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst)
     RET_ReallyLR
 ...
 
 ---
 # Make sure we can repair physical register uses as well.
 name:            defaultMappingUseRepairPhysReg
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 # CHECK-NEXT:   - { id: 2, class: gpr }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0, %s0
     ; CHECK:           %0(32) = COPY %w0
     ; CHECK-NEXT:      %2(32) = COPY %s0
-    ; CHECK-NEXT:      %1(32) = G_ADD i32 %0, %2
+    ; CHECK-NEXT:      %1(32) = G_ADD s32 %0, %2
     %0(32) = COPY %w0
-    %1(32) = G_ADD i32 %0, %s0
+    %1(32) = G_ADD s32 %0, %s0
 ...
 
 ---
 # Make sure we can repair physical register defs.
 name:            defaultMappingDefRepairPhysReg
 isSSA:           true
 # CHECK:      registers:
 # CHECK-NEXT:   - { id: 0, class: gpr }
 # CHECK-NEXT:   - { id: 1, class: gpr }
 registers:
   - { id: 0, class: _ }
 body: |
   bb.0.entry:
     liveins: %w0
     ; CHECK:           %0(32) = COPY %w0
-    ; CHECK-NEXT:      %1(32) = G_ADD i32 %0, %0
+    ; CHECK-NEXT:      %1(32) = G_ADD s32 %0, %0
     ; CHECK-NEXT:      %s0 = COPY %1
     %0(32) = COPY %w0
-    %s0 = G_ADD i32 %0, %0
+    %s0 = G_ADD s32 %0, %0
 ...
 
 ---
 # Check that the greedy mode is able to switch the
 # G_OR instruction from fpr to gpr.
 name:            greedyMappingOr
 isSSA:           true
 # CHECK:      registers:
bb.0.entry:
 
 
     ; Fast mode tries to reuse the source of the copy for the destination.
     ; Now, the default mapping says that %0 and %1 need to be in FPR.
     ; The repairing code insert two copies to materialize that.
     ; FAST-NEXT: %3(64) = COPY %0
     ; FAST-NEXT: %4(64) = COPY %1
     ; The mapping of G_OR is on FPR.
-    ; FAST-NEXT: %2(64) = G_OR <2 x i32> %3, %4
+    ; FAST-NEXT: %2(64) = G_OR <2 x s32> %3, %4
 
     ; Greedy mode remapped the instruction on the GPR bank.
-    ; GREEDY-NEXT: %2(64) = G_OR <2 x i32> %0, %1
+    ; GREEDY-NEXT: %2(64) = G_OR <2 x s32> %0, %1
     %0(64) = COPY %x0
     %1(64) = COPY %x1
-    %2(64) = G_OR <2 x i32> %0, %1
+    %2(64) = G_OR <2 x s32> %0, %1
 ...
 
 ---
 # Check that the greedy mode is able to switch the
 # G_OR instruction from fpr to gpr, while still honoring
 # %2 constraint.
 name:            greedyMappingOrWithConstraints
 isSSA:           true
bb.0.entry:
 
 
     ; Fast mode tries to reuse the source of the copy for the destination.
     ; Now, the default mapping says that %0 and %1 need to be in FPR.
     ; The repairing code insert two copies to materialize that.
     ; FAST-NEXT: %3(64) = COPY %0
     ; FAST-NEXT: %4(64) = COPY %1
     ; The mapping of G_OR is on FPR.
-    ; FAST-NEXT: %2(64) = G_OR <2 x i32> %3, %4
+    ; FAST-NEXT: %2(64) = G_OR <2 x s32> %3, %4
 
     ; Greedy mode remapped the instruction on the GPR bank.
-    ; GREEDY-NEXT: %3(64) = G_OR <2 x i32> %0, %1
+    ; GREEDY-NEXT: %3(64) = G_OR <2 x s32> %0, %1
     ; We need to keep %2 into FPR because we do not know anything about it.
     ; GREEDY-NEXT: %2(64) = COPY %3
     %0(64) = COPY %x0
     %1(64) = COPY %x1
-    %2(64) = G_OR <2 x i32> %0, %1
+    %2(64) = G_OR <2 x s32> %0, %1
 ...

test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll

 ; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
 ; REQUIRES: global-isel
 ; This file checks that the translation from llvm IR to generic MachineInstr
 ; is correct.
 
 ; Tests for add.
 ; CHECK: name: addi32
-; CHECK: G_ADD i32
+; CHECK: G_ADD s32
 define i32 @addi32(i32 %arg1, i32 %arg2) {
   %res = add i32 %arg1, %arg2
   ret i32 %res
 }

test/CodeGen/MIR/X86/generic-instr-type-error.mir

 # RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
 # This test ensures that the MIR parser report an error for
 # opaque types used on generic instruction.
 
 ---
 name:            bar
 isSSA:           true
 registers:
   - { id: 0, class: gr32 }
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK: [[@LINE+1]]:20: expected a sized type
-    %0(32) = G_ADD %opaque %edi, %edi
+    ; CHECK: [[@LINE+1]]:20: expected sN or <N x sM> for sized GlobalISel type
+    %0(32) = G_ADD unsized %edi, %edi
 ...

test/CodeGen/MIR/X86/generic-virtual-registers.mir

registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body: |
   bb.0.entry:
     liveins: %edi
-    ; CHECK:      %0(32) = G_ADD i32 %edi
-    %0(32) = G_ADD i32 %edi, %edi
-    ; CHECK:      %1(64) = G_ADD <2 x i32> %edi
-    %1(64) = G_ADD <2 x i32> %edi, %edi
-    ; CHECK:      %2(64) = G_ADD <2 x i32> %edi
-    %2(64) = G_ADD %type_alias %edi, %edi
+    ; CHECK:      %0(32) = G_ADD s32 %edi
+    %0(32) = G_ADD s32 %edi, %edi
+    ; CHECK:      %1(64) = G_ADD <2 x s32> %edi
+    %1(64) = G_ADD <2 x s32> %edi, %edi
+    ; CHECK:      %2(64) = G_ADD s64 %edi
+    %2(64) = G_ADD s64 %edi, %edi
     ; G_ADD is actually not a valid operand for structure type,
     ; but that is the only one we have for now for testing.
-    ; CHECK:      %3(64) = G_ADD { i32, i32 } %edi
-    %3(64) = G_ADD {i32, i32} %edi, %edi
-    ; CHECK:      %4(48) = G_ADD %structure_alias %edi
-    %4(48) = G_ADD %structure_alias %edi, %edi
+    ; CHECK:      %3(64) = G_ADD s64 %edi
+    %3(64) = G_ADD s64 %edi, %edi
+    ; CHECK:      %4(48) = G_ADD s48 %edi
+    %4(48) = G_ADD s48 %edi, %edi
 ...