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Differential D20797

[test/AMDGPU] Square-braced-syntax for registers: add macro test/example.
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Authored by artem.tamazov on May 30 2016, 11:44 AM.

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• tstellarAMD
arsenm

Commits

rGf88397c84cf5: [test/AMDGPU] Square-braced-syntax for registers: add macro test/example.
rL271675: [test/AMDGPU] Square-braced-syntax for registers: add macro test/example.

Summary

Test added as per discussion in http://reviews.llvm.org/D20588.
The macro is just a demonstration, useless in practice.
Coding style fixes.

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Repository: rL LLVM

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artem.tamazov updated this revision to Diff 58981.May 30 2016, 11:44 AM

artem.tamazov retitled this revision from to [test/AMDGPU] Square-braced-syntax for registers: add macro test/example..

artem.tamazov updated this object.

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artem.tamazov set the repository for this revision to rL LLVM.

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artem.tamazov added a parent revision: D20588: [AMDGPU][llvm-mc] Square-braced-syntax for registers: make ":expr2" optional..May 30 2016, 11:46 AM

Coding style fixes as per late comments in http://reviews.llvm.org/D20588.

Herald added a subscriber: arsenm. · View Herald TranscriptJun 2 2016, 6:47 AM

LGTM

This revision is now accepted and ready to land.Jun 2 2016, 11:41 AM

Closed by commit rL271675: [test/AMDGPU] Square-braced-syntax for registers: add macro test/example. (authored by artem.tamazov). · Explain WhyJun 3 2016, 7:47 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

test/

MC/

AMDGPU/

macro-examples.s

35 lines

Diff 58981

test/MC/AMDGPU/macro-examples.s

This file was added.

				// RUN: llvm-mc -arch=amdgcn -mcpu=fiji %s \| FileCheck %s --check-prefix=VI

				//===----------------------------------------------------------------------===//
				// Example of reg[expr] and reg[epxr1:expr2] syntax in macros.
				//===----------------------------------------------------------------------===//

				.macro REG_NUM_EXPR_EXAMPLE width iter iter_end
				.if \width == 4
				flat_load_dwordx4 v[8 + (\iter * 4):8 + (\iter * 4) + 3], v[2:3]
				.else
				flat_load_dword v[8 + \iter], v[2:3]
				.endif

				.if (\iter_end - \iter)
				REG_NUM_EXPR_EXAMPLE \width, (\iter + 1), \iter_end
				.endif
				.endm

				REG_NUM_EXPR_EXAMPLE 4, 0, 0
				// VI: flat_load_dwordx4 v[8:11], v[2:3]

				REG_NUM_EXPR_EXAMPLE 1, 0, 0
				// VI: flat_load_dword v8, v[2:3]

				REG_NUM_EXPR_EXAMPLE 4, 1, 4
				// VI: flat_load_dwordx4 v[12:15], v[2:3]
				// VI: flat_load_dwordx4 v[16:19], v[2:3]
				// VI: flat_load_dwordx4 v[20:23], v[2:3]
				// VI: flat_load_dwordx4 v[24:27], v[2:3]

				REG_NUM_EXPR_EXAMPLE 1, 1, 4
				// VI: flat_load_dword v9, v[2:3]
				// VI: flat_load_dword v10, v[2:3]
				// VI: flat_load_dword v11, v[2:3]
				// VI: flat_load_dword v12, v[2:3]