[AMDGPU][llvm-mc] Square-braced-syntax for registers: make ":expr2" optional.

[artem.tamazov]

Summary

Register numbers may be specified as assembly-time expressions. This feature can be useful in macros and alike. However, expressions are supported within sqare braces only.

Sqare braces were initially intended to support specifying of multiple (pairs/quads...) registers. Syntax like v[8:8] which specifies single register is also supported. That allows expressions but looks a bit unnatural.

This change supports syntax REG[EXPR].
Tests added.

[artem.tamazov]

Ping. That ball will be in flight for a day))

[arsenm]

Can you add a test that's an example of the macro use you are talking about? I'm not sure I see the point. Does sp3 support this?

[artem.tamazov]

In D20588#441260, @arsenm wrote:

Can you add a test that's an example of the macro use you are talking about? I'm not sure I see the point.

This change just supports expressions in register numbers, so it looks to me test with macro out of the scope.
As far as I understand, support for macros is a part of core llvm-mc, and there are tests.
An example from Jay C.:

.set kCopyAlignedVecWidth, 4
.set kCopyAlignedUnroll, 1
...
.macro mCopyAlignedPhase2Load iter iter_end
    .if kCopyAlignedVecWidth == 4
      flat_load_dwordx4    v[8 + (\iter * 4):8 + (\iter * 4) + 3], v[2:3]
    .else
      flat_load_dword      v[8 + \iter], v[2:3]
    .endif

    v_add_u32              v2, vcc, v2, s25
    v_addc_u32             v3, vcc, v3, 0x0, vcc

    .if (\iter_end - \iter)
      mCopyAlignedPhase2Load (\iter + 1), \iter_end
    .endif
  .endm

  mCopyAlignedPhase2Load 0, (kCopyAlignedUnroll - 1)

[artem.tamazov]

In D20588#441260, @arsenm wrote:

Does sp3 support this?

I do not know if it supports expressions as register numbers.

[arsenm]

In D20588#441276, @artem.tamazov wrote:

In D20588#441260, @arsenm wrote:

Can you add a test that's an example of the macro use you are talking about? I'm not sure I see the point.

This change just supports expressions in register numbers, so it looks to me test with macro out of the scope.
As far as I understand, support for macros is a part of core llvm-mc, and there are tests.
An example from Jay C.:

.set kCopyAlignedVecWidth, 4
.set kCopyAlignedUnroll, 1
...
.macro mCopyAlignedPhase2Load iter iter_end
    .if kCopyAlignedVecWidth == 4
      flat_load_dwordx4    v[8 + (\iter * 4):8 + (\iter * 4) + 3], v[2:3]
    .else
      flat_load_dword      v[8 + \iter], v[2:3]
    .endif

    v_add_u32              v2, vcc, v2, s25
    v_addc_u32             v3, vcc, v3, 0x0, vcc

    .if (\iter_end - \iter)
      mCopyAlignedPhase2Load (\iter + 1), \iter_end
    .endif
  .endm

  mCopyAlignedPhase2Load 0, (kCopyAlignedUnroll - 1)

It's still a good idea to add tests to make sure this feature actually works here, and with this feature in particular even if nothing was done here to implement that specifically

[artem.tamazov]

In D20588#442468, @arsenm wrote:

In D20588#441276, @artem.tamazov wrote:

In D20588#441260, @arsenm wrote:

Can you add a test that's an example of the macro use you are talking about? I'm not sure I see the point.

This change just supports expressions in register numbers, so it looks to me test with macro out of the scope.
As far as I understand, support for macros is a part of core llvm-mc, and there are tests.

It's still a good idea to add tests to make sure this feature actually works here, and with this feature in particular even if nothing was done here to implement that specifically

Okay, I will add a test with macro soon. In a new "test/MC/AMDGPU/macro-examples.s", I think.

[arsenm]

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

774

return on next line

[artem.tamazov]

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

774

I just followed existing style)) Anyway, this patch is already committed, so I will put the fix into http://reviews.llvm.org/D20797. Would you like me to fix all the stuff like this (scattered here and there)?

[arsenm]

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

774

Sure

llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

if ((Reg = getSpecialRegForName(RegName))) {
       else if (RegName.startswith("ttmp")) { RegNumIndex = strlen("ttmp"); RegKind = IS_TTMP; }
       else { return false; }
       if (RegName.size() > RegNumIndex) {
         // Single 32-bit register: vXX.
         if (RegName.substr(RegNumIndex).getAsInteger(10, RegNum)) { return false; }
         Parser.Lex();
         RegWidth = 1;
       } else {
-        // Range of registers: v[XX:YY].
+        // Range of registers: v[XX:YY]. ":YY" is optional.
         Parser.Lex();
         int64_t RegLo, RegHi;
         if (getLexer().isNot(AsmToken::LBrac)) { return false; }
         Parser.Lex();
 
         if (getParser().parseAbsoluteExpression(RegLo)) { return false; }
 
-        if (getLexer().isNot(AsmToken::Colon)) { return false; }
+        const bool isRBrace = getLexer().is(AsmToken::RBrac);
+        if (!isRBrace && getLexer().isNot(AsmToken::Colon)) { return false; }
         Parser.Lex();
 
+        if (isRBrace) {
+          RegHi = RegLo;
+        } else {
           if (getParser().parseAbsoluteExpression(RegHi)) { return false; }
 
           if (getLexer().isNot(AsmToken::RBrac)) { return false; }
           Parser.Lex();
-
+        }
         RegNum = (unsigned) RegLo;
         RegWidth = (RegHi - RegLo) + 1;
       }
     }
   } else if (getLexer().is(AsmToken::LBrac)) {
     // List of consecutive registers: [s0,s1,s2,s3]
     Parser.Lex();
     if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) { return false; }

llvm/trunk/test/MC/AMDGPU/reg-syntax-extra.s

 
 s_buffer_load_dword ttmp1, [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
 // SICI: s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x74,0xf4,0x38,0xc2]
 // VI:   s_buffer_load_dword ttmp1, ttmp[4:7], ttmp4 ; encoding: [0x7a,0x1c,0x20,0xc0,0x74,0x00,0x00,0x00]
 
 s_buffer_load_dwordx4 [ttmp8,ttmp9,ttmp10,ttmp11], [ttmp4,ttmp5,ttmp6,ttmp7], ttmp4
 // SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
 // VI:   s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 [ttmp[8],ttmp[8+1],ttmp[5*2],ttmp[(3+2)*2+1]], ttmp[45/11:(33+45)/11], ttmp4
+// SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
+// VI:   s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 ttmp[7+1:(3+2)*2+1], [ttmp[45/11],ttmp[5],ttmp6,ttmp[(33+45)/11]], ttmp4
+// SICI: s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x74,0x74,0xbc,0xc2]
+// VI:   s_buffer_load_dwordx4 ttmp[8:11], ttmp[4:7], ttmp4 ; encoding: [0x3a,0x1e,0x28,0xc0,0x74,0x00,0x00,0x00]
+
+flat_load_dword v[8:8], v[2:3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dword v[63/8+1:65/8], v[2:3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dword v8, v[2*2-2:(3+7)/3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dword v[63/8+1], v[2:3]
+// VI:   flat_load_dword v8, v[2:3]      ; encoding: [0x00,0x00,0x50,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dwordx4 v[8:11], v[2*2-2:(3*3-6)]
+// VI:   flat_load_dwordx4 v[8:11], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dwordx4 v[8/2+4:11/2+6], v[2:3]
+// VI:   flat_load_dwordx4 v[8:11], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x00,0x08]
+
+flat_load_dwordx4   [v[8/2+4],v9,v[10],v[11/2+6]], v[2:3]
+// VI:   flat_load_dwordx4 v[8:11], v[2:3] ; encoding: [0x00,0x00,0x5c,0xdc,0x02,0x00,0x00,0x08]