[AArch64] Improve getUsefulBitsForUse for narrow stores.

[mcrosier]

Summary

For narrow stores (e.g., strb, srth) we know the upper bits of the register are unused/not useful. In some cases we can use this information to eliminate unnecessary instructions.

For example, without this patch we generate (from the 2nd test case):

ldr w8, [x0]
and w8, w8, #0xfff0
bfxil w8, w2, #16, #4
strh w8, [x1]

and after the patch the 'and' is removed:

ldr w8, [x0]
bfxil w8, w2, #16, #4
strh w8, [x1]
ret

During the lowering of the bitfield insert instruction the 'and' is eliminated because we know the upper 16-bits that are masked off are unused and the lower 4-bits that are masked off are overwritten by the insert itself. Therefore, the 'and' is unnecessary.

Please take a look,
Chad

[t.p.northover]

Looks good to me. Thanks!

Tim.

[gberry]

You might want to fix the typo in the first line of the description: (i.e., ldrb, ldrh) should be (i.e. strb, strh) (and probably should be e.g. not i.e. if you want to be pedantic :))

[gberry]

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

1852

Aren't there more of these opcodes? Also don't you need to make sure that the Orig node is the stored value operand, and not an address operand?

[mcrosier]

Address Geoff's comments:
-Update description
-Make sure the use is the stores first source operand (i.e., the value being stored).

[mcrosier]

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

1852

I'll have to see if there are other opcodes. I don't think we have pre/post or versions at this point.

1855

I tried to come up with a test case, but I don't think this problem can be exposed.

define void @test(i64 %ptr32, i8* %ptr8, i64 %x)  {
entry:
  %and = and i64 %ptr32, -8
  %shr = lshr i64 %x, 8
  %and1 = and i64 %shr, 7
  %or = or i64 %and, %and1
  %trunc = trunc i64 %or to i8
  %conv = inttoptr i8 %trunc to i8*
  store i8 1, i8* %conv
  ret void
}

Basically, in the cases I tried it looks like there will be a zero-extend between the 'strb/strh' and the 'or' preventing such a case from happening. Regardless, I think the check is correct (but not testable AFAICT).

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
   case AArch64::ORRXrs:
     if (UserNode->getOperand(1) != Orig)
       return;
     return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
                                              Depth);
   case AArch64::BFMWri:
   case AArch64::BFMXri:
     return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
+
+  case AArch64::STRBui:
+  case AArch64::STRBBui:
+    if (UserNode->getOperand(0) != Orig)
+      return;
+    UserNode->dump();
+    UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xff);
+    return;
+
+  case AArch64::STRHui:
+  case AArch64::STRHHui:
+    if (UserNode->getOperand(0) != Orig)
+      return;
+    UsefulBits &= APInt(UsefulBits.getBitWidth(), 0xffff);
+    return;
   }
 }
 
 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
   if (Depth >= 6)
     return;
   // Initialize UsefulBits
   if (!Depth) {

test/CodeGen/AArch64/bitfield-insert.ll

; CHECK: lsl
   %or.1 = or i32 %conv, %shl.1  ;   B1 B0 A A
   %shl.2 = shl i32 %or.1, 8     ;   B0 A A 0
   %or.2 = or i32 %conv, %shl.2  ;   B0 A A A
   %shl.3 = shl i32 %or.2, 8     ;   A A A 0
   %or.3 = or i32 %conv, %shl.3  ;   A A A A
   %shl.4 = shl i32 %or.3, 8     ;   A A A 0
   ret i32 %shl.4
 }
+
+define void @test_nouseful_strb(i32* %ptr32, i8* %ptr8, i32 %x)  {
+entry:
+; CHECK-LABEL: @test_nouseful_strb
+; CHECK: ldr [[REG1:w[0-9]+]],
+; CHECK-NOT:  and {{w[0-9]+}}, {{w[0-9]+}}, #0xf8
+; CHECK-NEXT: bfxil [[REG1]], w2, #16, #3
+; CHECK-NEXT: strb [[REG1]],
+; CHECK-NEXT: ret
+  %0 = load i32, i32* %ptr32, align 8
+  %and = and i32 %0, -8
+  %shr = lshr i32 %x, 16
+  %and1 = and i32 %shr, 7
+  %or = or i32 %and, %and1
+  %trunc = trunc i32 %or to i8
+  store i8 %trunc, i8* %ptr8
+  ret void
+}
+
+define void @test_nouseful_strh(i32* %ptr32, i16* %ptr16, i32 %x)  {
+entry:
+; CHECK-LABEL: @test_nouseful_strh
+; CHECK: ldr [[REG1:w[0-9]+]],
+; CHECK-NOT:  and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0
+; CHECK-NEXT: bfxil [[REG1]], w2, #16, #4
+; CHECK-NEXT: strh [[REG1]],
+; CHECK-NEXT: ret
+  %0 = load i32, i32* %ptr32, align 8
+  %and = and i32 %0, -16
+  %shr = lshr i32 %x, 16
+  %and1 = and i32 %shr, 15
+  %or = or i32 %and, %and1
+  %trunc = trunc i32 %or to i16
+  store i16 %trunc, i16* %ptr16
+  ret void
+}