[ARM] PR25722 Support and tests for transform of LDR rt, = to MOV

[peter.smith]

Summary

This change implements the transformation in processInstruction() for the LDR rt, =expression to MOV rt, expression when the expression can be evaluated and can fit into the immediate field of the MOV or a MVN.

Across the ARM and Thumb instruction sets there are several cases to consider, each with a different range of representatble constants.
In ARM we have:

• Modified immediate (All ARM architectures)
• MOVW (v6t2 and above)

In Thumb we have:

• Modified immediate (v6t2, v7m and v8m.mainline)
• MOVW (v6t2, v7m, v8.mainline and v8m.baseline)
• Narrow Thumb MOV that can be used in an IT block (non flag-setting)

If the immediate fits any of the available alternatives then we make the transformation.

Fixes 25722.

[t.p.northover]

Couple of comments on this one, but only one that looks like it could be a real problem:

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

6905

ARM::MOVi16's actual predicate is "[IsARM, HasV6T2]". It's probably an academic distinction, but checking for v8m in ARM-mode code looks weird.

6932

It looks like SP is a permitted register for t2LDRpci but not the Thumb MOVs.

[peter.smith]

Hello Tim,

Thanks very much for the review. I'll send an update out tomorrow.

Peter

[peter.smith]

I've updated the patch to not do any kind of translation when the destination is SP or PC. Now that I think about it I have seen bootcode where the stack pointer has been set using ldr sp,=value so this would have caused problems.

I've added changed the ARM check from hasV8MBaseline to has v6T2Ops as that matches TableGen and befits the ARM presence of MOVW in V6T2 onwards.

[t.p.northover]

Thanks for updating the patch Peter. This looks good to me now.

Now that I think about it I have seen bootcode where the stack pointer has been set using ldr sp,=value so this would have caused problems.

That doesn't surprise me at all, though I couldn't actually remember seeing any.

Cheers.

Tim.

[rengolin]

Committed in r269354

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool isThumbOne() const {
     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
   }
   bool isThumbTwo() const {
     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
   }
   bool hasThumb() const {
     return getSTI().getFeatureBits()[ARM::HasV4TOps];
   }
+  bool hasThumb2() const {
+    return getSTI().getFeatureBits()[ARM::FeatureThumb2];
+  }
   bool hasV6Ops() const {
     return getSTI().getFeatureBits()[ARM::HasV6Ops];
   }
   bool hasV6MOps() const {
     return getSTI().getFeatureBits()[ARM::HasV6MOps];
   }
   bool hasV7Ops() const {
     return getSTI().getFeatureBits()[ARM::HasV7Ops];
case AsmToken::Colon: {
     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
     return false;
   }
   case AsmToken::Equal: {
     S = Parser.getTok().getLoc();
     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
       return Error(S, "unexpected token in operand");
-
     Parser.Lex(); // Eat '='
     const MCExpr *SubExprVal;
     if (getParser().parseExpression(SubExprVal))
       return true;
     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
     return false;
   }
bool ARMAsmParser::processInstruction(MCInst &Inst,
   case ARM::t2LDRSBpcrel:
     Inst.setOpcode(ARM::t2LDRSBpci);
     return true;
   case ARM::t2LDRSHpcrel:
     Inst.setOpcode(ARM::t2LDRSHpci);
     return true;
   case ARM::LDRConstPool:
   case ARM::tLDRConstPool:
-  case ARM::t2LDRConstPool:  {
-    // Handle the pseudo instruction for ldr rn,=
-    // For now we always create the constant pool entry and load from it
-    // FIXME: Use a MOV or MVN when the immediate will fit
+  case ARM::t2LDRConstPool: {
+    // Pseudo instruction ldr rt, =immediate is converted to a
+    // MOV rt, immediate if immediate is known and representable
+    // otherwise we create a constant pool entry that we load from.
     MCInst TmpInst;
+    const ARMOperand &PoolOperand =
+      static_cast<ARMOperand &>(*Operands[3]);
+    const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
     if (Inst.getOpcode() == ARM::LDRConstPool)
       TmpInst.setOpcode(ARM::LDRi12);
     else if (Inst.getOpcode() == ARM::tLDRConstPool)
       TmpInst.setOpcode(ARM::tLDRpci);
     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
       TmpInst.setOpcode(ARM::t2LDRpci);
-    const ARMOperand &PoolOperand =
-      static_cast<ARMOperand &>(*Operands[3]);
-    const MCExpr *PoolExpr = PoolOperand.getConstantPoolImm();
+    // If SubExprVal is a constant we may be able to use a MOV
+    if (isa<MCConstantExpr>(SubExprVal)) {
+      int64_t Value =
+        (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
+      bool UseMov  = true;
+      bool MovHasS = true;
+      if (Inst.getOpcode() == ARM::LDRConstPool) {
+        // ARM Constant
+        if (ARM_AM::getSOImmVal(Value) != -1) {
+          Value = ARM_AM::getSOImmVal(Value);
+          TmpInst.setOpcode(ARM::MOVi);
+        }
+        else if (ARM_AM::getSOImmVal(~Value) != -1) {
+          Value = ARM_AM::getSOImmVal(~Value);
+          TmpInst.setOpcode(ARM::MVNi);
+        }
+        else if (hasV8MBaseline() &&
+                 Value >=0 && Value < 65536) {
+          TmpInst.setOpcode(ARM::MOVi16);
+          MovHasS = false;
+        }
+        else
+          UseMov = false;
+      }
+      else {
+        // Thumb/Thumb2 Constant
+        if (hasThumb2() &&
+            ARM_AM::getT2SOImmVal(Value) != -1)
+          TmpInst.setOpcode(ARM::t2MOVi);
+        else if (hasThumb2() &&
+                 ARM_AM::getT2SOImmVal(~Value) != -1) {
+          TmpInst.setOpcode(ARM::t2MVNi);
+          Value = ~Value;
+        }
+        else if (hasV8MBaseline() &&
+                 Value >=0 && Value < 65536) {
+          TmpInst.setOpcode(ARM::t2MOVi16);
+          MovHasS = false;
+        }
+        else
+          UseMov = false;
+      }
+      if (UseMov) {
+        TmpInst.addOperand(Inst.getOperand(0));           // Rt
+        TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
+        TmpInst.addOperand(Inst.getOperand(2));           // CondCode
+        TmpInst.addOperand(Inst.getOperand(3));           // CondCode
+        if (MovHasS)
+          TmpInst.addOperand(MCOperand::createReg(0));    // S
+        Inst = TmpInst;
+        return true;
+      }
+    }
+    // No opportunity to use MOV/MVN create constant pool
     const MCExpr *CPLoc =
-      getTargetStreamer().addConstantPoolEntry(PoolExpr,
+      getTargetStreamer().addConstantPoolEntry(SubExprVal,
                                                PoolOperand.getStartLoc());
     TmpInst.addOperand(Inst.getOperand(0));           // Rt
-    TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // Offset to pool
-    if (Inst.getOpcode() == ARM::LDRConstPool)
-      TmpInst.addOperand(MCOperand::createImm(0));    // ARM uses two operands
+    TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
+    if (TmpInst.getOpcode() == ARM::LDRi12)
+      TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
     Inst = TmpInst;
-    return false;
+    return true;
   }
-   break;
   // Handle NEON VST complex aliases.
   case ARM::VST1LNdWB_register_Asm_8:
   case ARM::VST1LNdWB_register_Asm_16:
   case ARM::VST1LNdWB_register_Asm_32: {
     MCInst TmpInst;
     // Shuffle the operands around so the lane index operand is in the
     // right place.
     unsigned Spacing;

test/MC/ARM/ldr-pseudo-cond-darwin.s

+@RUN: llvm-mc -triple armv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-THUMB2 --check-prefix=CHECK %s
+
+@
+@ Check that ldr to constant pool correctly transfers the condition codes
+@
+@ simple test
+.section __TEXT,a,regular,pure_instructions
+@ CHECK-LABEL: f0:
+f0:
+  it eq
+  ldreq r0, =0x10002
+@ CHECK: ldreq r0, Ltmp0
+
+@ loading multiple constants
+.section __TEXT,b,regular,pure_instructions
+@ CHECK-LABEL: f1:
+f1:
+  ite eq
+  ldreq r0, =0x10003
+@ CHECK: ldreq r0, Ltmp1
+  ldrne r0, =0x10004
+@ CHECK: ldrne r0, Ltmp2
+
+@ transformation to mov
+.section __TEXT,d,regular,pure_instructions
+@ CHECK-LABEL: f2:
+f2:
+@ Can use the narrow Thumb mov as it does not set flags in an IT block
+  it eq
+  ldreq r1, =0x1
+@ CHECK: moveq r1, #1
+
+@ Must use the wide Thumb mov if the constant can't be represented
+  ite eq
+  ldreq r2, = 0x1f000000
+@ CHECK-ARM moveq r2, #520093696
+@ CHECK-THUMB2 moveq.w r2, #520093696
+  ldrne r3, = 0x00001234
+@ CHECK movwne r2, #4660
+
+@
+@ Constant Pools
+@
+@ CHECK: .section __TEXT,a,regular,pure_instructions
+@ CHECK: .p2align 2
+@ CHECK: Ltmp0:
+@ CHECK: .long 65538
+
+@ CHECK: .section __TEXT,b,regular,pure_instructions
+@ CHECK: .p2align 2
+@ CHECK: Ltmp1:
+@ CHECK: .long 65539
+@ CHECK: Ltmp2:
+@ CHECK: .long 65540

test/MC/ARM/ldr-pseudo-cond.s

+@RUN: llvm-mc -triple armv7-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-THUMB2 --check-prefix=CHECK %s
+
+@
+@ Check that ldr to constant pool correctly transfers the condition codes
+@
+@ simple test
+.section a,"ax",%progbits
+@ CHECK-LABEL: f0:
+f0:
+  it eq
+  ldreq r0, =0x10002
+@ CHECK: ldreq r0, .Ltmp[[TMP0:[0-9]+]]
+
+@ loading multiple constants
+.section b,"ax",%progbits
+@ CHECK-LABEL: f1:
+f1:
+  ite eq
+  ldreq r0, =0x10003
+@ CHECK: ldreq r0, .Ltmp[[TMP1:[0-9]+]]
+  ldrne r0, =0x10004
+@ CHECK: ldrne r0, .Ltmp[[TMP2:[0-9]+]]
+
+@ transformation to mov
+.section c, "ax", %progbits
+@ CHECK-LABEL: f2:
+f2:
+@ Can use the narrow Thumb mov as it does not set flags in an IT block
+  it eq
+  ldreq r1, =0x1
+@ CHECK: moveq r1, #1
+
+@ Must use the wide Thumb mov if the constant can't be represented
+  ite eq
+  ldreq r2, = 0x1f000000
+@ CHECK-ARM moveq r2, #520093696
+@ CHECK-THUMB2 moveq.w r2, #520093696
+  ldrne r3, = 0x00001234
+@ CHECK movwne r2, #4660
+
+@
+@ Constant Pools
+@
+@ CHECK: .section a,"ax",%progbits
+@ CHECK: .p2align 2
+@ CHECK: .Ltmp[[TMP0]]
+@ CHECK: .long 65538
+
+@ CHECK: .section b,"ax",%progbits
+@ CHECK: .p2align 2
+@ CHECK: .Ltmp[[TMP1]]
+@ CHECK: .long 65539
+@ CHECK: .Ltmp[[TMP2]]
+@ CHECK: .long 65540

test/MC/ARM/ldr-pseudo-darwin.s

 @ This test has a partner (ldr-pseudo.s) that contains matching
 @ tests for the ldr-pseudo on linux targets. We need separate files
 @ because the syntax for switching sections and temporary labels differs
 @ between darwin and linux. Any tests added here should have a matching
 @ test added there.
 
-@RUN: llvm-mc -triple   armv7-apple-darwin %s | FileCheck %s
-@RUN: llvm-mc -triple thumbv5-apple-darwin %s | FileCheck %s
-@RUN: llvm-mc -triple thumbv7-apple-darwin %s | FileCheck %s
-
+@RUN: llvm-mc -triple   armv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK %s
+@RUN: llvm-mc -triple   armv5-base-apple-darwin %s | FileCheck --check-prefix=CHECK-ARMV5 --check-prefix=CHECK %s        
+@RUN: llvm-mc -triple thumbv5-base-apple-darwin %s | FileCheck --check-prefix=CHECK-THUMB --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv7-base-apple-darwin %s | FileCheck --check-prefix=CHECK-THUMB2 --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv8m.base-base-apple-darwin %s | FileCheck --check-prefix=CHECK-BASELINE --check-prefix=CHECK %s
 @
 @ Check that large constants are converted to ldr from constant pool
 @
 @ simple test
 .section __TEXT,b,regular,pure_instructions
 @ CHECK-LABEL: f3:
 f3:
   ldr r0, =0x10002

 f15:
   ldr r0, =0x10001+9
 @ CHECK: ldr r0, Ltmp14
   adds r0, r0, #1
   ldr r0, =bar+4
 @ CHECK: ldr r0, Ltmp15
   adds r0, r0, #1
 
+@ transformation to mov
+.section __TEXT,m,regular,pure_instructions
+@ CHECK-LABEL: f16:
+f16:
+
+@ Representable in ARM, and Thumb with support mov.w or movw
+  ldr r1, =0x1
+@ CHECK-ARM: mov r1, #1
+@ CHECK-ARMV5: mov r1, #1
+@ CHECK-THUMB: ldr r1, Ltmp16
+@ CHECK-THUMB2: mov.w r1, #1
+@ CHECK-BASELINE: movw r1, #1
+
+@ Immediate is representable in A1 and T2 modified immediate only not movw
+  ldr r2, =0x120000
+@ CHECK-ARM: mov r2, #1179648
+@ CHECK-ARMV5: mov r2, #1179648
+@ CHECK-THUMB: ldr r2, Ltmp17
+@ CHECK-THUMB2: mov.w r2, #1179648
+@ CHECK-BASELINE: ldr r2, Ltmp16
+
+@ Immediate can be represented only with movw instruction
+  ldr r3, =0x1234
+@ CHECK-ARM: movw r3, #4660
+@ CHECK-ARMV5: ldr r3, Ltmp16
+@ CHECK-THUMB: ldr r3, Ltmp18
+@ CHECK-THUMB2: movw r3, #4660
+@ CHECK-BASELINE: movw r3, #4660
+
+@ Immediate can be represented only with T2 modified immediate
+  ldr r4, =0xabababab
+@ CHECK-ARM: ldr r4, Ltmp16
+@ CHECK-ARMV5: ldr r4, Ltmp17
+@ CHECK-THUMB: ldr r4, Ltmp19
+@ CHECK-THUMB2: mov.w r4, #2880154539
+@ CHECK-BASELINE: ldr r4, Ltmp17
+
+@ Immediate can be represented only with A1 modified immediate
+  ldr r5, =0x1000000b
+@ CHECK-ARM: mov r5, #268435467
+@ CHECK-ARMV5: mov r5, #268435467
+@ CHECK-THUMB: ldr r5, Ltmp20
+@ CHECK-THUMB2: ldr r5, Ltmp16
+@ CHECK-BASELINE: ldr r5, Ltmp18
+
+@ Negative numbers can be used with MVN or in Thumb2 with modified immediate
+  ldr r6, =-1
+@ CHECK-ARM: mvn r6, #0
+@ CHECK-ARMV5: mvn r6, #0
+@ CHECK-THUMB: ldr r6, Ltmp21
+@ CHECK-THUMB2: mov.w r6, #-1
+@ CHECK-BASELINE: ldr r6, Ltmp19
+  ldr r7, =-0x100
+@ CHECK-ARM: mvn r7, #255
+@ CHECK-ARMV5: mvn r7, #255
+@ CHECK-THUMB: ldr r7, Ltmp22
+@ CHECK-THUMB2: mvn r7, #255
+@ CHECK-BASELINE: ldr r7, Ltmp20
+
+@ Constant expressions can be used
+  .equ expr, 0x10 + 0x10
+  ldr r0, = expr
+@ CHECK-ARM: mov r0, #32
+@ CHECK-ARMV5: mov r0, #32
+@ CHECK-THUMB: ldr r0, Ltmp23
+@ CHECK-THUMB2: mov.w r0, #32
+@ CHECK-BASELINE: movw r0, #32
+  ldr r1, = expr - 0x10
+@ CHECK-ARM: mov r1, #16
+@ CHECK-ARMV5: mov r1, #16
+@ CHECK-THUMB: ldr r1, Ltmp24
+@ CHECK-THUMB2: mov.w r1, #16
+@ CHECK-BASELINE: movw r1, #16
+
+@ usage of translation in macro
+.macro usemov_in_a_macro
+  ldr r2, =0x3
+  ldr r3, =expr
+.endm
+@ CHECK-LABEL: f17:
+f17:
+  usemov_in_a_macro
+@ CHECK-ARM: mov r2, #3
+@ CHECK-ARM: mov r3, #32
+@ CHECK-ARMV5: mov r2, #3
+@ CHECK-ARMV5: mov r3, #32
+@ CHECK-THUMB: ldr r2, Ltmp25
+@ CHECK-THUMB: ldr r3, Ltmp26
+@ CHECK-THUMB2: mov.w r2, #3
+@ CHECK-THUMB2: mov.w r3, #32
+@ CHECK-BASELINE: movw r2, #3
+@ CHECK-BASELINE: movw r3, #32
 @
 @ Constant Pools
 @
 @ CHECK: .section __TEXT,b,regular,pure_instructions
 @ CHECK: .data_region
 @ CHECK: .p2align 2
 @ CHECK-LABEL: Ltmp0:
 @ CHECK: .long 65538

test/MC/ARM/ldr-pseudo.s

 @ This test has a partner (ldr-pseudo-darwin.s) that contains matching
 @ tests for the ldr-pseudo on darwin targets. We need separate files
 @ because the syntax for switching sections and temporary labels differs
 @ between darwin and linux. Any tests added here should have a matching
 @ test added there.
 
-@RUN: llvm-mc -triple   armv7-unknown-linux-gnueabi %s | FileCheck %s
-@RUN: llvm-mc -triple thumbv5-unknown-linux-gnueabi %s | FileCheck %s
-@RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s | FileCheck %s
-
+@RUN: llvm-mc -triple   armv7-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-ARM --check-prefix=CHECK %s
+@RUN: llvm-mc -triple   armv5-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-ARMV5 --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv5-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-THUMB --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-THUMB2 --check-prefix=CHECK %s
+@RUN: llvm-mc -triple thumbv8m.base-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-BASELINE --check-prefix=CHECK %s
 @
 @ Check that large constants are converted to ldr from constant pool
 @
 @ simple test
 .section b,"ax",%progbits
 @ CHECK-LABEL: f3:
 f3:
   ldr r0, =0x10002

 f15:
   ldr r0, =0x10001+9
 @ CHECK: ldr r0, .Ltmp[[TMP14:[0-9]+]]
   adds r0, r0, #1
   ldr r0, =bar+4
 @ CHECK: ldr r0, .Ltmp[[TMP15:[0-9]+]]
   adds r0, r0, #1
 
+@ transformation to mov
+.section m, "ax", %progbits
+@ CHECK-LABEL: f16:
+f16:
+
+@ Representable in ARM, and Thumb with support mov.w or movw
+  ldr r1, =0x1
+@ CHECK-ARM: mov r1, #1
+@ CHECK-ARMV5: mov r1, #1
+@ CHECK-THUMB: ldr r1, .Ltmp[[TMP16:[0-9]+]]
+@ CHECK-THUMB2: mov.w r1, #1
+@ CHECK-BASELINE: movw r1, #1
+
+@ Immediate is representable in A1 and T2 modified immediate only not movw
+  ldr r2, =0x120000
+@ CHECK-ARM: mov r2, #1179648
+@ CHECK-ARMV5: mov r2, #1179648
+@ CHECK-THUMB: ldr r2, .Ltmp[[TMP17:[0-9]+]]
+@ CHECK-THUMB2: mov.w r2, #1179648
+@ CHECK-BASELINE: ldr r2, .Ltmp[[TMP16:[0-9]+]]
+
+@ Immediate can be represented only with movw instruction
+  ldr r3, =0x1234
+@ CHECK-ARM: movw r3, #4660
+@ CHECK-ARMV5: ldr r3, .Ltmp[[TMP16:[0-9]+]]
+@ CHECK-THUMB: ldr r3, .Ltmp[[TMP18:[0-9]+]]
+@ CHECK-THUMB2: movw r3, #4660
+@ CHECK-BASELINE: movw r3, #4660
+
+@ Immediate can be represented only with T2 modified immediate
+  ldr r4, =0xabababab
+@ CHECK-ARM: ldr r4, .Ltmp[[TMP16:[0-9]+]]
+@ CHECK-ARMV5: ldr r4, .Ltmp[[TMP17:[0-9]+]]
+@ CHECK-THUMB: ldr r4, .Ltmp[[TMP19:[0-9]+]]
+@ CHECK-THUMB2: mov.w r4, #2880154539
+@ CHECK-BASELINE: ldr r4, .Ltmp[[TMP17:[0-9]+]]
+
+@ Immediate can be represented only with A1 modified immediate
+  ldr r5, =0x1000000b
+@ CHECK-ARM: mov r5, #268435467
+@ CHECK-ARMV5: mov r5, #268435467
+@ CHECK-THUMB: ldr r5, .Ltmp[[TMP20:[0-9]+]]
+@ CHECK-THUMB2: ldr r5, .Ltmp[[TMP16:[0-9]+]]
+@ CHECK-BASELINE: ldr r5, .Ltmp[[TMP18:[0-9]+]]
+
+@ Negative numbers can be used with MVN or in Thumb2 with modified immediate
+  ldr r6, =-1
+@ CHECK-ARM: mvn r6, #0
+@ CHECK-ARMV5: mvn r6, #0
+@ CHECK-THUMB: ldr r6, .Ltmp[[TMP21:[0-9]+]]
+@ CHECK-THUMB2: mov.w r6, #-1
+@ CHECK-BASELINE: ldr r6, .Ltmp[[TMP19:[0-9]+]]
+  ldr r7, =-0x100
+@ CHECK-ARM: mvn r7, #255
+@ CHECK-ARMV5: mvn r7, #255
+@ CHECK-THUMB: ldr r7, .Ltmp[[TMP22:[0-9]+]]
+@ CHECK-THUMB2: mvn r7, #255
+@ CHECK-BASELINE: ldr r7, .Ltmp[[TMP20:[0-9]+]]
+
+@ Constant expressions can be used
+  .equ expr, 0x10 + 0x10
+  ldr r0, = expr
+@ CHECK-ARM: mov r0, #32
+@ CHECK-ARMV5: mov r0, #32
+@ CHECK-THUMB: ldr r0, .Ltmp[[TMP23:[0-9]+]]
+@ CHECK-THUMB2: mov.w r0, #32
+@ CHECK-BASELINE: movw r0, #32
+  ldr r1, = expr - 0x10
+@ CHECK-ARM: mov r1, #16
+@ CHECK-ARMV5: mov r1, #16
+@ CHECK-THUMB: ldr r1, .Ltmp[[TMP24:[0-9]+]]
+@ CHECK-THUMB2: mov.w r1, #16
+@ CHECK-BASELINE: movw r1, #16
+
+@ usage of translation in macro
+.macro usemov_in_a_macro
+  ldr r2, =0x3
+  ldr r3, =expr
+.endm
+@ CHECK-LABEL: f17:
+f17:
+  usemov_in_a_macro
+@ CHECK-ARM: mov r2, #3
+@ CHECK-ARM: mov r3, #32
+@ CHECK-ARMV5: mov r2, #3
+@ CHECK-ARMV5: mov r3, #32
+@ CHECK-THUMB: ldr r2, .Ltmp[[TMP25:[0-9]+]]
+@ CHECK-THUMB: ldr r3, .Ltmp[[TMP26:[0-9]+]]
+@ CHECK-THUMB2: mov.w r2, #3
+@ CHECK-THUMB2: mov.w r3, #32
+@ CHECK-BASELINE: movw r2, #3
+@ CHECK-BASELINE: movw r3, #32
 @
 @ Constant Pools
 @
 @ CHECK: .section b,"ax",%progbits
 @ CHECK: .p2align 2
 @ CHECK: .Ltmp[[TMP0]]
 @ CHECK: .long 65538