[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions

[hvarga]

Summary

This patch implements microMIPS32r6 SLT, SLTI, SLTIU and SLTU instructions.

There was a problem with the previous implementation of this patch (D19354) and because of that commit rL267137 was reverted.
After committing of the previous patch, test-suite failed with error message in the form of:

fatal error: error in backend: Cannot select: t21: i32 = setcc t2, Constant:i32<6>, setgt:ch

There was a problem with selecting SLT instruction in LLVM backend.

For that reason, it is decided to revert commit rL267137 and make this patch which besides implementation of instructions and standard regression tests also includes one additional CodeGen test (slt.ll).

[sdardis]

Some nits. Can you extend the rest of the set*.ll tests?

lib/Target/Mips/MicroMipsInstrInfo.td

1009

The SetgeImmPats patterns can be included for microMIPS if you extend that parameter list to include XOR_MM like the SeqeqPats patterns.

1047

Also include the "sltu $rs, $rt, $imm" alias.

lib/Target/Mips/MipsInstrInfo.td

2189–2191

This alias should be included in [NotinMicroMips].

2576

See my above comment on extending SetgeImmPats.

test/CodeGen/Mips/slt.ll

4

Use a CHECK-LABEL: to match the function here, and write a CHECK line that matches slt taking $4 as one of it operands as its an argument register or just "CHECK: slt".

9

Same here.

[hvarga]

Added MipsPats for conditional branches in MicroMips.
Added predicate NotInMicroMips for existing Mips implementations.
Added cases for BNE_MM and BEQ_MM in getAnalyzableBrOpc, getEquivalentCompactForm and getOppositeBranchOpc.
Added tests for microMips in set*.ll files.

This update has been contributed by @mamidzic.

[sdardis]

Two major points: The multiclass patterns you've copied can instead be extended. LUi is also covered in a NotInMicroMips predicate. The rest is just formatting nits over the assembly. More details inline.

Thanks.

lib/Target/Mips/MicroMipsInstrInfo.td

1040–1069

This multiclass definition is unnecessary. Instead, change BrcondPats in MipsInstrInfo.td so that the pattern is using BEQ instead use BEQOp. You can then instantiate the pattern for microMIPS.

1071–1077

Similarly here. You can extend SetgeImmPats in MipsInstrInfo.td to take and XORiOp parameter.

1082–1086

With the changes you've made here, some of those patterns (SetlePats, SetgtPats) combine microMIPS and MIPS instructions.

For these multiclass instantiations, extend the definitions in MipsInstroInfo.td to take an XORiOp parameter.

1123–1126

Align the simm32_relaxed:$imm under GPR32Opnd like:

def : MipsInstAlias<"sltu $rs, $rt, $imm",
                    (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
                              simm32_relaxed:$imm), 0>;

lib/Target/Mips/MipsInstrInfo.td

1694

Move LUi out of this NotInMicromips block.

test/CodeGen/Mips/brconlt.ll

17

Formatting: line up the sltius in the immediate block so that they are all in the same column, one space after the longest check prefix. And in the other cases below.

test/CodeGen/Mips/setcc-se.ll

9 ↗

(On Diff #62472)

Can you instead match this with "<MCInst #{{[0-9]+}} SLTiu_MM" ? And the other cases below, as it a better match to the expected output.

[hvarga]

Reworked BrcondPats, SetlePats, SetgePats and SetgeImmPats multiclasses so that they can work for microMips too without interfering with the existing implementations.
Micromips now extends Mips BrcondPats, SeteqPats, SetlePats, SetgtPats, SetgePats and SetgeImmPats multiclasses.
Fixed LUi being in the notInMicroMips predicate block.
Changed the indentations on test files according to the comments.

This update has been contributed by @mamidzic.

[sdardis]

LGTM with two things: move the BrcondPats out of the NotInMicroMips block, otherwise we get the same bug that this patch addresses, except it affects microMIPS64R6. The second is the placement of a comment. More details inline.

lib/Target/Mips/Mips64InstrInfo.td

539–540 ↗

(On Diff #63777)

By moving the pattern instantiation into the block covered by NotInMicroMips, LLVM cannot fall back to picking MIPS64R6 instructions for microMIPS64R6. The instruction mapping tables will correct this for direct object emission and the assembly is identical for microMIPS64R6.

Can you move this out of the NotInMicroMips block?

549 ↗

(On Diff #63777)

Place this comment above the 'let AdditionalPredicates..' line.

lib/Target/Mips/MicroMips32r6InstrInfo.td

 class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>;
 class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>;
 class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
-      MMR6Arch<"addu16">;
+      MMR6Arch<"addu16"> {
+  int AddedComplexity  = 1;
+}
 class AND16_MMR6_DESC : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
       MMR6Arch<"and16">;
 class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
-      MMR6Arch<"or16">;
+      MMR6Arch<"or16"> {
+  int AddedComplexity = 1;
+}
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
       MMR6Arch<"sll16">;
 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,

lib/Target/Mips/MicroMipsInstrFormats.td

 
 class MMArch {
   string Arch = "micromips";
-  list<dag> Pattern = [];
 }
 
 class ADD_FM_MM<bits<6> op, bits<10> funct> : MMArch {

lib/Target/Mips/MicroMipsInstrInfo.td

 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
               (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
 
+defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
+defm : SetlePats<GPR32, SLT_MM, SLTu_MM>;
+defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
+defm : SetgePats<GPR32, SLT_MM, SLTu_MM>;
+
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//

                     (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"tne $rs, $rt",
                     (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"slt $rs, $rt, $imm",
+                    (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
 def : MipsInstAlias<"sll $rd, $rt, $rs",
                     (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : MipsInstAlias<"sra $rd, $rt, $rs",

lib/Target/Mips/MipsInstrInfo.td

 }
 def ADDi  : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd>, ADDI_FM<0x8>,
             ISA_MIPS1_NOT_32R6_64R6;
+let AdditionalPredicates = [NotInMicroMips] in {
 def SLTi  : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xa>;
 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
             SLTI_FM<0xb>;
-let AdditionalPredicates = [NotInMicroMips] in {
 def ANDi  : MMRel, StdMMR6Rel,
             ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
             ADDI_FM<0xc>;

             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
 def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
 def SUB   : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
+let AdditionalPredicates = [NotInMicroMips] in {
 def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
+}
 let AdditionalPredicates = [NotInMicroMips] in {
 def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
             ADD_FM<0, 0x24>;

                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
 def : MipsInstAlias<"negu $rt, $rs",
                     (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
+let Predicates = [NotInMicroMips] in {
 def : MipsInstAlias<
           "slt $rs, $rt, $imm",
           (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
+}
 def : MipsInstAlias<
           "sltu $rt, $rs, $imm",
           (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;

                 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
 }
 
+let AdditionalPredicates = [NotInMicroMips] in {
 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
 defm : SetlePats<GPR32, SLT, SLTu>;
 defm : SetgtPats<GPR32, SLT, SLTu>;
 defm : SetgePats<GPR32, SLT, SLTu>;
+}
 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
 
 // bswap pattern

test/CodeGen/Mips/brconlt.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
 
 @i = global i32 5, align 4
 @j = global i32 10, align 4

   br i1 %cmp, label %if.end, label %if.then
 
 ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
+; MM32R6:   slt ${{[0-9]+}}, ${{[0-9]+}}
 ; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
 ; 16: $[[LABEL]]:
 

test/CodeGen/Mips/seteq.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 1, align 4
 @j = global i32 10, align 4

   store i32 %conv, i32* @r1, align 4
 ; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
 ; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
+; MMR6:   sltiu   ${{[0-9]+}}, ${{[0-9]+}}, 1
 ; 16: move  ${{[0-9]+}}, $24
   ret void
 }

test/CodeGen/Mips/setltk.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4

   %cmp = icmp slt i32 %0, 10
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16: slti  $[[REGISTER:[0-9]+]], 10
-; 16: move  $[[REGISTER]], $24
+; 16:     slti  $[[REGISTER:[0-9]+]], 10
+; MM32R6:   slti    $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
+; 16:     move  $[[REGISTER]], $24
   ret void
 }

test/CodeGen/Mips/setne.ll

 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @i = global i32 1, align 4
 @j = global i32 10, align 4

   store i32 %conv, i32* @r1, align 4
 ; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
 ; 16: sltu  ${{[0-9]+}}, $[[REGISTER]]
+; MMR6: sltu    ${{[0-9]+}}, $zero, ${{[0-9]+}}
 ; 16: move  ${{[0-9]+}}, $24
   ret void
 }

test/CodeGen/Mips/slt.ll

+; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
+
+define i32 @slt(i32 signext %a) nounwind readnone {
+  %1 = icmp slt i32 %a, 7
+  %2 = select i1 %1, i32 3, i32 4
+  ret i32 %2
+}
+
+define i32 @sgt(i32 signext %a) {
+entry:
+  %cmp = icmp sgt i32 %a, 32767
+  %cond = select i1 %cmp, i32 7, i32 5
+  ret i32 %cond
+}
+
+; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}

test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
+0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5
+0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256
+0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256
+0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0x47 0x7c # CHECK: di

test/MC/Mips/micromips32r6/valid.s

   seleqz.d $f2, $f4, $f8   # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
   selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
   selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
+  slt $3, $4, $5           # CHECK: slt $3, $4, $5         # encoding: [0x00,0xa4,0x1b,0x50]
+  slti $3, $4, 256         # CHECK: slti $3, $4, 256       # encoding: [0x90,0x64,0x01,0x00]
+  sltiu $3, $4, 256        # CHECK: sltiu $3, $4, 256      # encoding: [0xb0,0x64,0x01,0x00]
+  sltu $3, $4, $5          # CHECK: sltu $3, $4, $5        # encoding: [0x00,0xa4,0x1b,0x90]
   class.s $f2, $f3         # CHECK: class.s $f2, $f3       # encoding: [0x54,0x62,0x00,0x60]
   class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x54,0x82,0x02,0x60]
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]