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Differential D18855

[mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions
ClosedPublic

Authored by zbuljan on Apr 7 2016, 6:23 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL266980: [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions
Summary

The patch implements microMIPSr6 TLBP, TLBR, TLBWI and TLBWR instructions.

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 52907.Apr 7 2016, 6:23 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptApr 7 2016, 6:23 AM
Herald added subscribers: sdardis, dsanders. · View Herald Transcript
sdardis added a reviewer: sdardis.Apr 7 2016, 9:15 AM

Can you add corresponding invalid tests for these instructions in test/MC/Mips/micromips{32r6, 64r6}/invalid.s ? They do not take an immediate or registers.

zbuljan updated this revision to Diff 53198.Apr 11 2016, 12:36 AM
zbuljan edited edge metadata.

Added invalid tests for TLBP, TLBR, TLBWI and TLBWR instructions.

sdardis accepted this revision.Apr 12 2016, 2:25 AM
sdardis edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Apr 12 2016, 2:25 AM
Closed by commit rL266980: [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions (authored by zbuljan). · Explain WhyApr 21 2016, 4:38 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
11 lines
test/
MC/
Disassembler/
Mips/
micromips32r6/
4 lines
micromips64r6/
4 lines
Mips/
micromips32r6/
12 lines
4 lines
micromips64r6/
12 lines
4 lines

Diff 53198

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 2,071 Lines • ▼ Show 20 Lines
class JR_HB_ENC : JR_HB_FM<8>; class JR_HB_ENC : JR_HB_FM<8>;
class JALR_HB_ENC : JALR_HB_FM<9>; class JALR_HB_ENC : JALR_HB_FM<9>;
def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
FrmOther, asmstr>; FrmOther, asmstr>;
let AdditionalPredicates = [NotInMicroMips] in {
def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
}
class CacheOp<string instr_asm, Operand MemOpnd> : class CacheOp<string instr_asm, Operand MemOpnd> :
InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
!strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther, !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
instr_asm> { instr_asm> {
let DecoderMethod = "DecodeCacheOp"; let DecoderMethod = "DecodeCacheOp";
} }
def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>, def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
▲ Show 20 Lines • Show All 552 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show First 20 Lines • Show All 270 Lines • ▼ Show 20 Lines
0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0 0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0
0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3 0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3
0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10 0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10
0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5 0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5
0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0 0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0
0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6 0x54 0x06 0x30 0x3b # CHECK: mfhc1 $zero, $f6
0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16 0x02 0xf0 0x8d 0x3c # CHECK: mfhc2 $23, $16
0x00 0x00 0x03 0x7c # CHECK: tlbp
0x00 0x00 0x13 0x7c # CHECK: tlbr
0x00 0x00 0x23 0x7c # CHECK: tlbwi
0x00 0x00 0x33 0x7c # CHECK: tlbwr

test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show First 20 Lines • Show All 209 Lines • ▼ Show 20 Lines
0x58 0xe6 0x49 0x50 # CHECK: daddu $9, $6, $7 0x58 0xe6 0x49 0x50 # CHECK: daddu $9, $6, $7
0x58 0x69 0x49 0x50 # CHECK: daddu $9, $9, $3 0x58 0x69 0x49 0x50 # CHECK: daddu $9, $9, $3
0x5d 0x26 0xc5 0x67 # CHECK: daddiu $9, $6, -15001 0x5d 0x26 0xc5 0x67 # CHECK: daddiu $9, $6, -15001
0x5d 0x29 0x00 0x0a # CHECK: daddiu $9, $9, 10 0x5d 0x29 0x00 0x0a # CHECK: daddiu $9, $9, 10
0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943 0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079 0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5 0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5
0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5 0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5
0x00 0x00 0x03 0x7c # CHECK: tlbp
0x00 0x00 0x13 0x7c # CHECK: tlbr
0x00 0x00 0x23 0x7c # CHECK: tlbwi
0x00 0x00 0x33 0x7c # CHECK: tlbwr

test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 269 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc] mfc0 $3, $7 # CHECK: mfc0 $3, $7, 0 # encoding: [0x00,0x67,0x00,0xfc]
mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc] mfc0 $3, $7, 3 # CHECK: mfc0 $3, $7, 3 # encoding: [0x00,0x67,0x18,0xfc]
mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b] mfc1 $5, $f10 # CHECK: mfc1 $5, $f10 # encoding: [0x54,0xaa,0x20,0x3b]
mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c] mfc2 $15, $5 # CHECK: mfc2 $15, $5 # encoding: [0x01,0xe5,0x4d,0x3c]
mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4] mfhc0 $20, $21 # CHECK: mfhc0 $20, $21, 0 # encoding: [0x02,0x95,0x00,0xf4]
mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4] mfhc0 $1, $2, 1 # CHECK: mfhc0 $1, $2, 1 # encoding: [0x00,0x22,0x08,0xf4]
mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b] mfhc1 $zero, $f6 # CHECK: mfhc1 $zero, $f6 # encoding: [0x54,0x06,0x30,0x3b]
mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c] mfhc2 $23, $16 # CHECK: mfhc2 $23, $16 # encoding: [0x02,0xf0,0x8d,0x3c]
tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]

test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmtc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmtc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmfc0 $4, $3, -1 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate dmfc0 $4, $3, 8 # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 192 Lines • ▼ Show 20 Linesa:
daddu $9, $6, $7 # CHECK: daddu $9, $6, $7 # encoding: [0x58,0xe6,0x49,0x50] daddu $9, $6, $7 # CHECK: daddu $9, $6, $7 # encoding: [0x58,0xe6,0x49,0x50]
daddu $9, $3 # CHECK: daddu $9, $9, $3 # encoding: [0x58,0x69,0x49,0x50] daddu $9, $3 # CHECK: daddu $9, $9, $3 # encoding: [0x58,0x69,0x49,0x50]
daddu $9, $6, -15001 # CHECK: daddiu $9, $6, -15001 # encoding: [0x5d,0x26,0xc5,0x67] daddu $9, $6, -15001 # CHECK: daddiu $9, $6, -15001 # encoding: [0x5d,0x26,0xc5,0x67]
daddu $9, 10 # CHECK: daddiu $9, $9, 10 # encoding: [0x5d,0x29,0x00,0x0a] daddu $9, 10 # CHECK: daddiu $9, $9, 10 # encoding: [0x5d,0x29,0x00,0x0a]
daddu $19, 26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x5e,0x73,0x69,0x3f] daddu $19, 26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x5e,0x73,0x69,0x3f]
daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f] daddu $24, $2, 18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x5f,0x02,0x46,0x9f]
dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb] dsubu $3, 5 # CHECK: daddiu $3, $3, -5 # encoding: [0x5c,0x63,0xff,0xfb]
dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb] dsubu $3, $4, 5 # CHECK: daddiu $3, $4, -5 # encoding: [0x5c,0x64,0xff,0xfb]
tlbp # CHECK: tlbp # encoding: [0x00,0x00,0x03,0x7c]
tlbr # CHECK: tlbr # encoding: [0x00,0x00,0x13,0x7c]
tlbwi # CHECK: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
tlbwr # CHECK: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
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