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Differential D18352

[mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions
ClosedPublic

Authored by zbuljan on Mar 22 2016, 7:41 AM.

Details

Reviewers
dsanders
sdardis
vkalintiris
zoran.jovanovic
hvarga
Commits
rL270030: [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions
Summary

The patch implements microMIPSr6 BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions.

Diff Detail

Event Timeline

zbuljan updated this revision to Diff 51286.Mar 22 2016, 7:41 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a reviewer: vkalintiris. · View Herald TranscriptMar 22 2016, 7:41 AM
Herald added a subscriber: dsanders. · View Herald Transcript
sdardis requested changes to this revision.Apr 19 2016, 8:08 AM
sdardis added a reviewer: sdardis.
sdardis added a subscriber: sdardis.

Small things mostly, comments inlined.

For the invalid/valid tests, can you sort the instructions you've added into alphabetical order?

lib/Target/Mips/MicroMips32r6InstrFormats.td
909

Rename this to POOL32I_BRANCH_COP_1_2_FM_MMR6. The class below is a copy-paste which is then not necessary and so can be deleted.

916

Just to be explicit, the encoding here is correct. The documentation isn't 100%.

922–933

See my above comment.

lib/Target/Mips/MicroMips32r6InstrInfo.td
209–212

See my comments on changing the class name to POOL32I_BRANCH_COP_1_2_FM_MMR6.

1159

Formatting, break the line after "BRANCH_DESC_BASE," and indent "HARDFLOAT {" appropriately.

test/MC/Disassembler/Mips/micromips32r6/valid.txt
283–290

You don't need to check each instruction twice if there is no real difference between the operands.

Just once is sufficient provided you do not use zero values.

This applies to the rest of the */valid.s tests.

test/MC/Mips/micromips32r6/invalid.s
116–131

For these invalid tests, checking once for each type of error for each instruction is sufficient.

This revision now requires changes to proceed.Apr 19 2016, 8:08 AM
sdardis added inline comments.Apr 20 2016, 2:09 AM
lib/Target/Mips/MicroMips32r6InstrInfo.td
1159

class BRANCH_COP1_MMR6_DESC also needs to inherit the relevant parameterised InstSE<> class.

This instruction should also define the register $at, like all other branches. $at is required to be defined by these instructions in case a long branch fixup needs to be emitted.

1168

This instruction needs to define at as well, but you can skip the InstSE<> class inheritance as COP2 is implementation specific and likely to be targeted by intrinsics anyway.

zbuljan updated this revision to Diff 56124.May 4 2016, 4:13 AM
zbuljan edited edge metadata.

Used only one format class POOL32I_BRANCH_COP_1_2_FM_MMR6 (other one was redundant so it is deleted).
Modified desc. class BRANCH_COP1_MMR6_DESC_BASE to inherit the relevant parameterised InstSE<> class.
Register $at is now defined in both desc. classes (BRANCH_COP1_MMR6_DESC_BASE and BRANCH_COP2_MMR6_DESC_BASE).
Removed redundant tests and added additional invalid tests.

sdardis requested changes to this revision.May 6 2016, 3:45 AM
sdardis edited edge metadata.

One change and one nit. The inheritance order needs to be changed so that the various fields of the instruction records get set correctly. Comments inlined.

lib/Target/Mips/MicroMips32r6InstrFormats.td
982

This class needs to inherit from MMR6Arch, as the current ordering does not set the Arch and BaseOpcode properly. The inheritance ordering should be similar to that of the existing microMIPSR6 branches, such as BGEC_MMR6.

lib/Target/Mips/MicroMips32r6InstrInfo.td
1181–1183

As coprocessor 2 is implementation dependant, $ft should be $rt.

This revision now requires changes to proceed.May 6 2016, 3:45 AM
zbuljan updated this revision to Diff 57339.May 16 2016, 5:28 AM
zbuljan edited edge metadata.

Rebased to work with TOT.
Changed POOL32I_BRANCH_COP_1_2_FM_MMR6 format class to inherit from MMR6Arch.

zbuljan updated this revision to Diff 57564.May 18 2016, 12:46 AM
zbuljan edited edge metadata.

Rebased to work with TOT.

sdardis accepted this revision.May 18 2016, 4:13 AM
sdardis edited edge metadata.

LGTM with 2 tiny nits.

test/MC/Mips/micromips32r6/valid.s
338–345

Checking each instruction once is sufficient. Just avoid using $zero or 0 as an operand because that may mask errors if values default to zero.

test/MC/Mips/micromips64r6/valid.s
276–283

Here too.

This revision is now accepted and ready to land.May 18 2016, 4:13 AM
Closed by commit rL270030: [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions (authored by zbuljan). · Explain WhyMay 19 2016, 12:37 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
AsmParser/
4 lines
13 lines
32 lines
10 lines
test/
MC/
Disassembler/
Mips/
micromips32r6/
4 lines
micromips64r6/
4 lines
Mips/
micromips32r6/
20 lines
8 lines
micromips64r6/
20 lines
8 lines

Diff 57564

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Show First 20 Lines • Show All 1,561 Lines • ▼ Show 20 Lines if (MCID.isBranch() || MCID.isCall()) {
case Mips::BGEZ_MM: case Mips::BGEZ_MM:
case Mips::BGTZ_MM: case Mips::BGTZ_MM:
case Mips::BLEZ_MM: case Mips::BLEZ_MM:
case Mips::BLTZ_MM: case Mips::BLTZ_MM:
case Mips::BGEZAL_MM: case Mips::BGEZAL_MM:
case Mips::BLTZAL_MM: case Mips::BLTZAL_MM:
case Mips::BC1F_MM: case Mips::BC1F_MM:
case Mips::BC1T_MM: case Mips::BC1T_MM:
case Mips::BC1EQZC_MMR6:
case Mips::BC1NEZC_MMR6:
case Mips::BC2EQZC_MMR6:
case Mips::BC2NEZC_MMR6:
assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); assert(MCID.getNumOperands() == 2 && "unexpected number of operands");
Offset = Inst.getOperand(1); Offset = Inst.getOperand(1);
if (!Offset.isImm()) if (!Offset.isImm())
break; // We'll deal with this situation later on when applying fixups. break; // We'll deal with this situation later on when applying fixups.
if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm())) if (!isIntN(inMicroMipsMode() ? 17 : 18, Offset.getImm()))
return Error(IDLoc, "branch target out of range"); return Error(IDLoc, "branch target out of range");
if (OffsetToAlignment(Offset.getImm(), if (OffsetToAlignment(Offset.getImm(),
1LL << (inMicroMipsMode() ? 1 : 2))) 1LL << (inMicroMipsMode() ? 1 : 2)))
▲ Show 20 Lines • Show All 4,767 Lines • Show Last 20 Lines

lib/Target/Mips/MicroMips32r6InstrFormats.td

Show First 20 Lines • Show All 900 Lines • ▼ Show 20 Linesclass POOL32A_TLBINV_FM_MMR6<string instr_asm, bits<10> funct>
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x0; let Inst{31-26} = 0x0;
let Inst{25-16} = 0x0; let Inst{25-16} = 0x0;
let Inst{15-6} = funct; let Inst{15-6} = funct;
let Inst{5-0} = 0b111100; let Inst{5-0} = 0b111100;
} }
class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode> class POOL32A_MFTC0_FM_MMR6<string instr_asm, bits<5> funct, bits<6> opcode>
sdardisUnsubmitted
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Rename this to POOL32I_BRANCH_COP_1_2_FM_MMR6. The class below is a copy-paste which is then not necessary and so can be deleted.

sdardis: Rename this to POOL32I_BRANCH_COP_1_2_FM_MMR6. The class below is a copy-paste which is then…
: MMR6Arch<instr_asm>, MipsR6Inst { : MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> rt; bits<5> rt;
bits<5> rs; bits<5> rs;
bits<3> sel; bits<3> sel;
bits<32> Inst; bits<32> Inst;
sdardisUnsubmitted
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Just to be explicit, the encoding here is correct. The documentation isn't 100%.

sdardis: Just to be explicit, the encoding here is correct. The documentation isn't 100%.
let Inst{31-26} = 0b000000; let Inst{31-26} = 0b000000;
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = rs; let Inst{20-16} = rs;
let Inst{15-14} = 0; let Inst{15-14} = 0;
let Inst{13-11} = sel; let Inst{13-11} = sel;
let Inst{10-6} = funct; let Inst{10-6} = funct;
let Inst{5-0} = opcode; let Inst{5-0} = opcode;
} }
class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct> class POOL32F_MFTC1_FM_MMR6<string instr_asm, bits<8> funct>
: MMR6Arch<instr_asm> { : MMR6Arch<instr_asm> {
bits<5> rt; bits<5> rt;
bits<5> fs; bits<5> fs;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0b010101; let Inst{31-26} = 0b010101;
sdardisUnsubmitted
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See my above comment.

sdardis: See my above comment.
let Inst{25-21} = rt; let Inst{25-21} = rt;
let Inst{20-16} = fs; let Inst{20-16} = fs;
let Inst{15-14} = 0; let Inst{15-14} = 0;
let Inst{13-6} = funct; let Inst{13-6} = funct;
let Inst{5-0} = 0b111011; let Inst{5-0} = 0b111011;
} }
class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct> class POOL32A_MFTC2_FM_MMR6<string instr_asm, bits<10> funct>
Show All 32 Linesclass POOL32A_DVPEVP_FM_MMR6<string instr_asm, bits<10> funct>
let Inst{31-26} = 0b000000; let Inst{31-26} = 0b000000;
let Inst{25-21} = 0b00000; let Inst{25-21} = 0b00000;
let Inst{20-16} = rs; let Inst{20-16} = rs;
let Inst{15-6} = funct; let Inst{15-6} = funct;
let Inst{5-0} = 0b111100; let Inst{5-0} = 0b111100;
} }
class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst { class POOL32B_LWP_SWP_FM_MMR6<bits<4> funct> : MipsR6Inst {
sdardisUnsubmitted
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This class needs to inherit from MMR6Arch, as the current ordering does not set the Arch and BaseOpcode properly. The inheritance ordering should be similar to that of the existing microMIPSR6 branches, such as BGEC_MMR6.

sdardis: This class needs to inherit from MMR6Arch, as the current ordering does not set the Arch and…
bits<5> rd; bits<5> rd;
bits<21> addr; bits<21> addr;
bits<5> base = addr{20-16}; bits<5> base = addr{20-16};
bits<12> offset = addr{11-0}; bits<12> offset = addr{11-0};
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = 0x8; let Inst{31-26} = 0x8;
let Inst{25-21} = rd; let Inst{25-21} = rd;
let Inst{20-16} = base; let Inst{20-16} = base;
let Inst{15-12} = funct; let Inst{15-12} = funct;
let Inst{11-0} = offset; let Inst{11-0} = offset;
} }
class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst { class CMP_BRANCH_OFF21_FM_MMR6<string opstr, bits<6> funct> : MipsR6Inst {
bits<5> rs; bits<5> rs;
bits<21> offset; bits<21> offset;
bits<32> Inst; bits<32> Inst;
let Inst{31-26} = funct; let Inst{31-26} = funct;
let Inst{25-21} = rs; let Inst{25-21} = rs;
let Inst{20-0} = offset; let Inst{20-0} = offset;
} }
class POOL32I_BRANCH_COP_1_2_FM_MMR6<string instr_asm, bits<5> funct>
: MMR6Arch<instr_asm> {
bits<5> rt;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = 0b010000;
let Inst{25-21} = funct;
let Inst{20-16} = rt;
let Inst{15-0} = offset;
}

lib/Target/Mips/MicroMips32r6InstrInfo.td

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Lines
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>; class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
class LI16_MMR6_ENC : LI_FM_MM16; class LI16_MMR6_ENC : LI_FM_MM16;
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>; class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>; class SDBBP16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b111011>;
class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6; class SUBU16_MMR6_ENC : POOL16A_SUBU16_FM_MMR6;
class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>; class XOR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1000>;
class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>; class TLBINV_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinv", 0x10d>;
class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>; class TLBINVF_MMR6_ENC : POOL32A_TLBINV_FM_MMR6<"tlbinvf", 0x14d>;
class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>; class DVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"dvp", 0b0001100101>;
class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>; class EVP_MMR6_ENC : POOL32A_DVPEVP_FM_MMR6<"evp", 0b0011100101>;
class BC1EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1eqzc", 0b01000>;
class BC1NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc1nezc", 0b01001>;
sdardisUnsubmitted
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See my comments on changing the class name to POOL32I_BRANCH_COP_1_2_FM_MMR6.

sdardis: See my comments on changing the class name to POOL32I_BRANCH_COP_1_2_FM_MMR6.
class BC2EQZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2eqzc", 0b01010>;
class BC2NEZC_MMR6_ENC : POOL32I_BRANCH_COP_1_2_FM_MMR6<"bc2nezc", 0b01011>;
class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd,
RegisterOperand GPROpnd> RegisterOperand GPROpnd>
: BRANCH_DESC_BASE { : BRANCH_DESC_BASE {
dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); dag InOperandList = (ins GPROpnd:$rt, opnd:$offset);
dag OutOperandList = (outs); dag OutOperandList = (outs);
string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); string AsmString = !strconcat(instr_asm, "\t$rt, $offset");
list<Register> Defs = [AT]; list<Register> Defs = [AT];
▲ Show 20 Lines • Show All 928 Lines • ▼ Show 20 Linesclass TLBINV_MMR6_DESC_BASE<string opstr> {
dag InOperandList = (ins); dag InOperandList = (ins);
string AsmString = opstr; string AsmString = opstr;
list<dag> Pattern = []; list<dag> Pattern = [];
} }
class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">;
class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">;
class DVPEVP_MMR6_DESC_BASE<string opstr> { class DVPEVP_MMR6_DESC_BASE<string opstr> {
sdardisUnsubmitted
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Formatting, break the line after "BRANCH_DESC_BASE," and indent "HARDFLOAT {" appropriately.

sdardis: Formatting, break the line after "BRANCH_DESC_BASE," and indent "HARDFLOAT {" appropriately.
sdardisUnsubmitted
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class BRANCH_COP1_MMR6_DESC also needs to inherit the relevant parameterised InstSE<> class.

This instruction should also define the register $at, like all other branches. $at is required to be defined by these instructions in case a long branch fixup needs to be emitted.

sdardis: class BRANCH_COP1_MMR6_DESC also needs to inherit the relevant parameterised InstSE<> class.
dag OutOperandList = (outs); dag OutOperandList = (outs);
dag InOperandList = (ins GPR32Opnd:$rs); dag InOperandList = (ins GPR32Opnd:$rs);
string AsmString = !strconcat(opstr, "\t$rs"); string AsmString = !strconcat(opstr, "\t$rs");
list<dag> Pattern = []; list<dag> Pattern = [];
} }
class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">; class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">;
class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">; class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">;
sdardisUnsubmitted
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This instruction needs to define at as well, but you can skip the InstSE<> class inheritance as COP2 is implementation specific and likely to be targeted by intrinsics anyway.

sdardis: This instruction needs to define at as well, but you can skip the InstSE<> class inheritance as…
class BEQZC_MMR6_DESC class BEQZC_MMR6_DESC
: CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>, : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
MMR6Arch<"beqzc">; MMR6Arch<"beqzc">;
class BNEZC_MMR6_DESC class BNEZC_MMR6_DESC
: CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>, : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21_mm, GPR32Opnd>,
MMR6Arch<"bnezc">; MMR6Arch<"bnezc">;
class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
!strconcat(opstr, "\t$rt, $offset"), [], II_BC1CCZ, FrmI>,
HARDFLOAT, BRANCH_DESC_BASE {
list<Register> Defs = [AT];
}
class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">;
sdardisUnsubmitted
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As coprocessor 2 is implementation dependant, $ft should be $rt.

sdardis: As coprocessor 2 is implementation dependant, $ft should be $rt.
class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">;
class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE {
dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset);
dag OutOperandList = (outs);
string AsmString = !strconcat(opstr, "\t$rt, $offset");
list<Register> Defs = [AT];
}
class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">;
class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Instruction Definitions // Instruction Definitions
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DecoderNamespace = "MicroMipsR6" in { let DecoderNamespace = "MicroMipsR6" in {
def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6; def ADD_MMR6 : StdMMR6Rel, ADD_MMR6_DESC, ADD_MMR6_ENC, ISA_MICROMIPS32R6;
▲ Show 20 Lines • Show All 289 Lines • ▼ Show 20 Lines
def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC, def CLASS_D_MMR6 : StdMMR6Rel, CLASS_D_MMR6_ENC, CLASS_D_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC, def TLBINV_MMR6 : StdMMR6Rel, TLBINV_MMR6_ENC, TLBINV_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC, def TLBINVF_MMR6 : StdMMR6Rel, TLBINVF_MMR6_ENC, TLBINVF_MMR6_DESC,
ISA_MICROMIPS32R6; ISA_MICROMIPS32R6;
def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6; def DVP_MMR6 : R6MMR6Rel, DVP_MMR6_ENC, DVP_MMR6_DESC, ISA_MICROMIPS32R6;
def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6; def EVP_MMR6 : R6MMR6Rel, EVP_MMR6_ENC, EVP_MMR6_DESC, ISA_MICROMIPS32R6;
def BC1EQZC_MMR6 : R6MMR6Rel, BC1EQZC_MMR6_DESC, BC1EQZC_MMR6_ENC,
ISA_MICROMIPS32R6;
def BC1NEZC_MMR6 : R6MMR6Rel, BC1NEZC_MMR6_DESC, BC1NEZC_MMR6_ENC,
ISA_MICROMIPS32R6;
def BC2EQZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2EQZC_MMR6_ENC, BC2EQZC_MMR6_DESC,
ISA_MICROMIPS32R6;
def BC2NEZC_MMR6 : R6MMR6Rel, MipsR6Inst, BC2NEZC_MMR6_ENC, BC2NEZC_MMR6_DESC,
ISA_MICROMIPS32R6;
} }
def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6; def BGEC_MMR6 : R6MMR6Rel, BGEC_MMR6_ENC, BGEC_MMR6_DESC, ISA_MICROMIPS32R6;
def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6; def BGEUC_MMR6 : R6MMR6Rel, BGEUC_MMR6_ENC, BGEUC_MMR6_DESC, ISA_MICROMIPS32R6;
def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6; def BLTC_MMR6 : R6MMR6Rel, BLTC_MMR6_ENC, BLTC_MMR6_DESC, ISA_MICROMIPS32R6;
def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6; def BLTUC_MMR6 : R6MMR6Rel, BLTUC_MMR6_ENC, BLTUC_MMR6_DESC, ISA_MICROMIPS32R6;
def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6; def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6;
def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6; def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6;
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lib/Target/Mips/Mips32r6InstrInfo.td

Show First 20 Lines • Show All 709 Lines • ▼ Show 20 Lines
def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6; def ADDIUPC : R6MMR6Rel, ADDIUPC_ENC, ADDIUPC_DESC, ISA_MIPS32R6;
def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6; def ALIGN : R6MMR6Rel, ALIGN_ENC, ALIGN_DESC, ISA_MIPS32R6;
def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6; def ALUIPC : R6MMR6Rel, ALUIPC_ENC, ALUIPC_DESC, ISA_MIPS32R6;
def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6; def AUI : R6MMR6Rel, AUI_ENC, AUI_DESC, ISA_MIPS32R6;
def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6; def AUIPC : R6MMR6Rel, AUIPC_ENC, AUIPC_DESC, ISA_MIPS32R6;
def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6; def BAL : BAL_ENC, BAL_DESC, ISA_MIPS32R6;
def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6; def BALC : R6MMR6Rel, BALC_ENC, BALC_DESC, ISA_MIPS32R6;
let AdditionalPredicates = [NotInMicroMips] in {
def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT; def BC1EQZ : BC1EQZ_ENC, BC1EQZ_DESC, ISA_MIPS32R6, HARDFLOAT;
def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT; def BC1NEZ : BC1NEZ_ENC, BC1NEZ_DESC, ISA_MIPS32R6, HARDFLOAT;
def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6; def BC2EQZ : BC2EQZ_ENC, BC2EQZ_DESC, ISA_MIPS32R6;
def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6;
}
def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6;
def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6;
def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6;
def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
▲ Show 20 Lines • Show All 179 Lines • Show Last 20 Lines

test/MC/Disassembler/Mips/micromips32r6/valid.txt

Show First 20 Lines • Show All 274 Lines • ▼ Show 20 Lines
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
0x00 0x00 0x47 0x7c # CHECK: di 0x00 0x00 0x47 0x7c # CHECK: di
0x00 0x0f 0x47 0x7c # CHECK: di $15 0x00 0x0f 0x47 0x7c # CHECK: di $15
0x00 0x00 0x43 0x7c # CHECK: tlbinv 0x00 0x00 0x43 0x7c # CHECK: tlbinv
0x00 0x00 0x53 0x7c # CHECK: tlbinvf 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9 0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7 0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7
0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4 0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4
0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6 0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0 0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0
0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8 0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8
0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1 0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
sdardisUnsubmitted
Not Done
ReplyInline Actions

You don't need to check each instruction twice if there is no real difference between the operands.

Just once is sufficient provided you do not use zero values.

This applies to the rest of the */valid.s tests.

sdardis: You don't need to check each instruction twice if there is no real difference between the…
0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12 0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14 0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0 0x00 0x67 0x00 0xfc # CHECK: mfc0 $3, $7, 0
0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3 0x00 0x67 0x18 0xfc # CHECK: mfc0 $3, $7, 3
0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10 0x54 0xaa 0x20 0x3b # CHECK: mfc1 $5, $f10
0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5 0x01 0xe5 0x4d 0x3c # CHECK: mfc2 $15, $5
0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0 0x02 0x95 0x00 0xf4 # CHECK: mfhc0 $20, $21, 0
0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1 0x00 0x22 0x08 0xf4 # CHECK: mfhc0 $1, $2, 1
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0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5 0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5 0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7 0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5 0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7 0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5 0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4) 0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4) 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8

test/MC/Disassembler/Mips/micromips64r6/valid.txt

Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4) 0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
0x58 0x64 0x7b 0x3c # CHECK: dsbh $3, $4 0x58 0x64 0x7b 0x3c # CHECK: dsbh $3, $4
0x58 0x64 0xfb 0x3c # CHECK: dshd $3, $4 0x58 0x64 0xfb 0x3c # CHECK: dshd $3, $4
0x58 0x64 0x28 0x00 # CHECK: dsll $3, $4, 5 0x58 0x64 0x28 0x00 # CHECK: dsll $3, $4, 5
0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5 0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5
0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6 0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5 0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6 0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6
0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 4
0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 4
0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 8
0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 8

test/MC/Mips/micromips32r6/invalid.s

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
sdardisUnsubmitted
Not Done
ReplyInline Actions

For these invalid tests, checking once for each type of error for each instruction is sufficient.

sdardis: For these invalid tests, checking once for each type of error for each instruction is…
tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
# bposge32 is microMIPS DSP instruction # bposge32 is microMIPS DSP instruction
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range

test/MC/Mips/micromips32r6/valid.s

Show First 20 Lines • Show All 329 Lines • ▼ Show 20 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10] sll $2, $3 # CHECK: sllv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x10]
sra $2, $3 # CHECK: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90] sra $2, $3 # CHECK: srav $2, $2, $3 # encoding: [0x00,0x43,0x10,0x90]
srl $2, $3 # CHECK: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50] srl $2, $3 # CHECK: srlv $2, $2, $3 # encoding: [0x00,0x43,0x10,0x50]
sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00] sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80] sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40] srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
bc1eqzc $f0, 4 # CHECK: bc1eqzc $f0, 4 # encoding: [0x41,0x00,0x00,0x02]
bc1eqzc $f31, 4 # CHECK: bc1eqzc $f31, 4 # encoding: [0x41,0x1f,0x00,0x02]
bc1nezc $f0, 4 # CHECK: bc1nezc $f0, 4 # encoding: [0x41,0x20,0x00,0x02]
bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02]
bc2eqzc $0, 8 # CHECK: bc2eqzc $0, 8 # encoding: [0x41,0x40,0x00,0x04]
bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04]
bc2nezc $0, 8 # CHECK: bc2nezc $0, 8 # encoding: [0x41,0x60,0x00,0x04]
bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04]
sdardisUnsubmitted
Not Done
ReplyInline Actions

Checking each instruction once is sufficient. Just avoid using $zero or 0 as an operand because that may mask errors if values default to zero.

sdardis: Checking each instruction once is sufficient. Just avoid using $zero or 0 as an operand because…

test/MC/Mips/micromips64r6/invalid.s

Show First 20 Lines • Show All 248 Lines • ▼ Show 20 Lines# RUN: FileCheck %s < %t1
dsll32 $3, $4, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate dsll32 $3, $4, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
dsll32 $3, $4, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate dsll32 $3, $4, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
dsra $4, $5, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate dsra $4, $5, 64 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
dsra $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate dsra $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate dsra32 $4, $5, 32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate dsra32 $4, $5, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
# bposge32 is microMIPS DSP instruction # bposge32 is microMIPS DSP instruction
bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range

test/MC/Mips/micromips64r6/valid.s

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Linesa:
dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c] dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c]
dshd $3, $4 # CHECK: dshd $3, $4 # encoding: [0x58,0x64,0xfb,0x3c] dshd $3, $4 # CHECK: dshd $3, $4 # encoding: [0x58,0x64,0xfb,0x3c]
dsll $3, $4, 5 # CHECK: dsll $3, $4, 5 # encoding: [0x58,0x64,0x28,0x00] dsll $3, $4, 5 # CHECK: dsll $3, $4, 5 # encoding: [0x58,0x64,0x28,0x00]
dsll32 $3, $4, 5 # CHECK: dsll32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x08] dsll32 $3, $4, 5 # CHECK: dsll32 $3, $4, 5 # encoding: [0x58,0x64,0x28,0x08]
dsllv $4, $5, $6 # CHECK: dsllv $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x10] dsllv $4, $5, $6 # CHECK: dsllv $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x10]
dsra $4, $5, 5 # CHECK: dsra $4, $5, 5 # encoding: [0x58,0x85,0x28,0x80] dsra $4, $5, 5 # CHECK: dsra $4, $5, 5 # encoding: [0x58,0x85,0x28,0x80]
dsra32 $4, $5, 5 # CHECK: dsra32 $4, $5, 5 # encoding: [0x58,0x85,0x28,0x84] dsra32 $4, $5, 5 # CHECK: dsra32 $4, $5, 5 # encoding: [0x58,0x85,0x28,0x84]
dsrav $4, $5, $6 # CHECK: dsrav $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x90] dsrav $4, $5, $6 # CHECK: dsrav $4, $5, $6 # encoding: [0x58,0xa6,0x20,0x90]
bc1eqzc $f0, 4 # CHECK: bc1eqzc $f0, 4 # encoding: [0x41,0x00,0x00,0x02]
bc1eqzc $f31, 4 # CHECK: bc1eqzc $f31, 4 # encoding: [0x41,0x1f,0x00,0x02]
bc1nezc $f0, 4 # CHECK: bc1nezc $f0, 4 # encoding: [0x41,0x20,0x00,0x02]
bc1nezc $f31, 4 # CHECK: bc1nezc $f31, 4 # encoding: [0x41,0x3f,0x00,0x02]
bc2eqzc $0, 8 # CHECK: bc2eqzc $0, 8 # encoding: [0x41,0x40,0x00,0x04]
bc2eqzc $31, 8 # CHECK: bc2eqzc $31, 8 # encoding: [0x41,0x5f,0x00,0x04]
bc2nezc $0, 8 # CHECK: bc2nezc $0, 8 # encoding: [0x41,0x60,0x00,0x04]
bc2nezc $31, 8 # CHECK: bc2nezc $31, 8 # encoding: [0x41,0x7f,0x00,0x04]
sdardisUnsubmitted
Not Done
ReplyInline Actions

Here too.

sdardis: Here too.
1: 1: