[Power9] basic support for Power 9 direct move instructions

[amehsan]

Summary

Adding a feature and also define instructions in td files. After updating my repository I still do not see Power 9 processor model, so in the current code, the new feature is not used. I will add that to Power 9 processor model once that piece of code is committed.

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

1246

Why 32-bit register inputs? The instruction takes two doubleword inputs in 64-bit registers and puts them in the VSR. The inputs should probably be:
(ins g8rc:$rA, g8rc:$rB).

1250

Same thing here. The output should be a 64-bit register.

[amehsan]

lib/Target/PowerPC/PPCInstrVSX.td

1246

That is an oversight. It does not impact encoding and decoding of the instruction, so testing was not able to catch it. That raises a quesiton: On Power8 and Power9 32 bit GPRs are the lower half of 64 bit GPRs and in 64 bit mode, the upper 32 bit cannot be accessed independently. So why do we need to distinguish between the two sets? I talked a little bit with other people and checked the source code and so far I do not have an answer for this question. One potential answer is that we need the distinction for processors that support some optional features of ISA, such as SPE. I will fix this anyway to be on the safe side.

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

1246

If you look at the definitions in lib/Target/PowerPC/PPCRegisterInfo.td, you'll see that the register classes have a different alignment/spill size. I am not aware of any other differences.

[amehsan]

lib/Target/PowerPC/PPCInstrVSX.td

1246

Then I suspect which one we use in a given instruction does not really matter (given how GPRC and G8RC are related to each other on Power). If that is the only difference, (and if tablegen language allows) I think a better design would have just one register class. But the alignment of that register class should be chosen depending on whether or not "In64BitMode" predicate is on or off.

[nemanjai]

I am not sure that tblgen actually supports this. I think what you're
suggesting is something along the lines of:

def GPRC : RegisterClass<"PPC", [i32], In64BitMode ? 64 : 32, ...

and I don't think that such functionality exists in tblgen. Of course, I
might be wrong.

[kbarton]

Some minor formatting changes, add the ISA3_0 feature, and change the input register class on one of the instructions.
With these changes, this LGTM.

lib/Target/PowerPC/PPC.td

137 ↗

(On Diff #50925)

Please remove blank lines to remain consistent with other feature definitions.

141 ↗

(On Diff #50925)

Please make sure this also requires the ISA3_0 feature that is defined in D18032

142 ↗

(On Diff #50925)

Remove blank line

lib/Target/PowerPC/PPCInstrVSX.td

1242

Please change this to g8rc:$rA

[kbarton]

lib/Target/PowerPC/PPCInstrVSX.td

1242

I was wrong with this - gprc is the correct register class to use here.

[amehsan]

lib/Target/PowerPC/PPC.td

141 ↗

(On Diff #50925)

I believe we don't want P9DirectMove to imply ISA3_0, but as we discussed separately, I will totally remove this feature. I will guard the instructions with

let Predicate = [ISA3_0, HasDirectMove]

[amehsan]

Removing P9DirectMove feature

[amehsan]

Committed r265031.

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
   def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
                           "xscvdpspn $XT, $XB", IIC_VecFP, []>;
   def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
                           "xscvspdpn $XT, $XB", IIC_VecFP, []>;
 
 } // AddedComplexity = 400
 } // HasP8Vector
 
-let Predicates = [HasDirectMove, HasVSX] in {
+let Predicates = [HasDirectMove] in {
   // VSX direct move instructions
   def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT),
                               "mfvsrd $rA, $XT", IIC_VecGeneral,
                               [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
       Requires<[In64BitMode]>;
   def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
                                "mfvsrwz $rA, $XT", IIC_VecGeneral,
                                [(set i32:$rA, (PPCmfvsr f64:$XT))]>;
   def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA),
                               "mtvsrd $XT, $rA", IIC_VecGeneral,
                               [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
       Requires<[In64BitMode]>;
   def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwa $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsra i32:$rA))]>;
   def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA),
                                "mtvsrwz $XT, $rA", IIC_VecGeneral,
                                [(set f64:$XT, (PPCmtvsrz i32:$rA))]>;
-} // HasDirectMove, HasVSX
+} // HasDirectMove
+
+let Predicates = [IsISA3_0, HasDirectMove] in {
+  def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA),
+                              "mtvsrws $XT, $rA", IIC_VecGeneral,
+                              []>;
+
+  def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB),
+                       "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral,
+                       []>, Requires<[In64BitMode]>;
+
+  def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT),
+                              "mfvsrld $rA, $XT", IIC_VecGeneral,
+                              []>, Requires<[In64BitMode]>;
+
+} // IsISA3_0, HasDirectMove
 
 /*  Direct moves of various widths from GPR's into VSR's. Each move lines
     the value up into element 0 (both BE and LE). Namely, entities smaller than
     a doubleword are shifted left and moved for BE. For LE, they're moved, then
     swapped to go into the least significant element of the VSR.
 */
 def MovesToVSR {
   dag BE_BYTE_0 =

test/MC/Disassembler/PowerPC/vsx.txt

 # CHECK: stxvx 57, 12, 27
 0x7f 0x2c 0xdb 0x19
 
 # CHECK: stxvl 57, 12, 27
 0x7f 0x2c 0xdb 0x1b
 
 # CHECK: stxvll 57, 12, 27
 0x7f 0x2c 0xdb 0x5b
+
+# CHECK: mtvsrws 34, 3
+0x7c 0x43 0x03 0x27
+
+# CHECK: mtvsrdd 34, 3, 12
+0x7c 0x43 0x63 0x67
+
+# CHECK: mfvsrld 3, 34
+0x7c 0x43 0x02 0x67

test/MC/PowerPC/vsx.s

 
 # Store Vector (Left-justified) with Length
 # CHECK-BE: stxvl 57, 12, 27                   # encoding: [0x7f,0x2c,0xdb,0x1b]
 # CHECK-LE: stxvl 57, 12, 27                   # encoding: [0x1b,0xdb,0x2c,0x7f]
             stxvl 57, 12, 27
 # CHECK-BE: stxvll 57, 12, 27                  # encoding: [0x7f,0x2c,0xdb,0x5b]
 # CHECK-LE: stxvll 57, 12, 27                  # encoding: [0x5b,0xdb,0x2c,0x7f]
             stxvll 57, 12, 27
+
+# P9 Direct Move Instructions
+# CHECK-BE: mtvsrws 34, 3                      # encoding: [0x7c,0x43,0x03,0x27]
+# CHECK-LE: mtvsrws 34, 3                      # encoding: [0x27,0x03,0x43,0x7c]
+            mtvsrws 34, 3
+
+# CHECK-BE: mtvsrdd 34, 3, 12                  # encoding: [0x7c,0x43,0x63,0x67]
+# CHECK-LE: mtvsrdd 34, 3, 12                  # encoding: [0x67,0x63,0x43,0x7c]
+            mtvsrdd 34, 3, 12
+
+# CHECK-BE: mfvsrld 3, 34                      # encoding: [0x7c,0x43,0x02,0x67]
+# CHECK-LE: mfvsrld 3, 34                      # encoding: [0x67,0x02,0x43,0x7c]
+            mfvsrld 3, 34