Power 9 Atomic instructions, load monitored and move XER to CR

[nemanjai]

Summary

This patch provides the implementation for the following instructions:
lwat,
ldat,
stwat,
stdat,
ldmx
mcrxrx

[cycheng]

lib/Target/PowerPC/PPCInstr64Bit.td

248

Depending on FC value, input might be $(rD+1), $(rD+2)
I believe that's why we need "hasExtraSrcRegAllocReq".

I am curious about the effect of "hasExtraSrcRegAllocReq", looks like it disallows register changing in AggressiveAntiDepBreaker::ScanInstruction, because it is dangerous to do that for this instruction.

249

Do we need to check $FC value? Or it's user's responsibility?

Even though it looks like user's responsibility:

an Invalid function code will cause the system data storage error handler to be invoked.

920

I don't know when we need to add "isPPC64", Does LDAT and STDAT also require this attribute?

[nemanjai]

lib/Target/PowerPC/PPCInstr64Bit.td

248

This is a good point, I added the comment to the 32-bit versions but forgot to add it here. It would certainly be a very bad idea for AADB to rename the target register when we may have values we need in the next register or two. All that being said, this should actually be hasExtraDefRegAllocReq. I'll fix it and re-post.

249

I think that if we decide to provide access to this instruction through a builtin, we should diagnose invalid FC's supplied by the user. However, I don't think attempting to diagnose it in the .td files is the right way to go.

920

You are correct, those instructions are actually 64-bit only instructions. Not just names for the same instructions but that use 64-bit registers rather than 32-bit ones. I'll be sure to add that.

[kbarton]

LGTM

[nemanjai]

Committed revision 265022.

lib/Target/PowerPC/PPC.td

 def FeatureFloat128 :
   SubtargetFeature<"float128", "HasFloat128", "true",
                    "Enable the __float128 data type for IEEE-754R Binary128.",
                    [FeatureVSX]>;
 
 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
   "Treat vector data stream cache control instructions as deprecated">;
 
+def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
+                                     "true",
+                                     "Enable instructions added in ISA 3.0.">;
+
 /*  Since new processors generally contain a superset of features of those that
     came before them, the idea is to make implementations of new processors
     less error prone and easier to read.
     Namely:
         list<SubtargetFeature> Power8FeatureList = ...
         list<SubtargetFeature> FutureProcessorSpecificFeatureList =
             [ features that Power8 does not support ]
         list<SubtargetFeature> FutureProcessorFeatureList =

lib/Target/PowerPC/PPCInstr64Bit.td

 let mayLoad = 1, hasSideEffects = 0 in {
 def LDARX : XForm_1<31,  84, (outs g8rc:$rD), (ins memrr:$ptr),
                     "ldarx $rD, $ptr", IIC_LdStLDARX, []>;
 
 // Instruction to support lock versions of atomics
 // (EH=1 - see Power ISA 2.07 Book II 4.4.2)
 def LDARXL : XForm_1<31,  84, (outs g8rc:$rD), (ins memrr:$ptr),
                      "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isDOT;
+
+let hasExtraSrcRegAllocReq = 1 in
+def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC),
+                         "ldat $rD, $rA, $FC", IIC_LdStLoad>,
+           Requires<[IsISA3_0]>;
 }
 
 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
                     "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isDOT;
 
+let mayStore = 1, hasSideEffects = 0 in
+def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC),
+                          "stdat $rS, $rA, $FC", IIC_LdStStore>,
+            Requires<[IsISA3_0]>;
+
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
 def TCRETURNdi8 :Pseudo< (outs),
                         (ins calltarget:$dst, i32imm:$offset),
                  "#TC_RETURNd8 $dst $offset",
                  []>;
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
def LDU  : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
                     []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
                     NoEncode<"$ea_result">;
 
 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
                    (ins memrr:$addr),
                    "ldux $rD, $addr", IIC_LdStLDUX,
                    []>, RegConstraint<"$addr.ptrreg = $ea_result">,
                    NoEncode<"$ea_result">, isPPC64;
+
+def LDMX : XForm_1<31, 309, (outs g8rc:$rD), (ins memrr:$src),
+                   "ldmx $rD, $src", IIC_LdStLD, []>, isPPC64,
+           Requires<[IsISA3_0]>;
 }
 }
 
 // Support for medium and large code model.
 let hasSideEffects = 0 in {
 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
                        "#ADDIStocHA", []>, isPPC64;
 let mayLoad = 1 in

lib/Target/PowerPC/PPCInstrFormats.td

 
 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
                     string asmstr, InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let A = xo2;
 }
 
+// XForm_base_r3xo for instructions such as P9 atomics where we don't want
+// to specify an SDAG pattern for matching.
+class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                    string asmstr, InstrItinClass itin>
+  : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> {
+}
+
+class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+            InstrItinClass itin>
+  : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> {
+  let FRA = 0;
+  let FRB = 0;
+}
+
 // XX*-Form (VSX)
 class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
               InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<5> A;
   bits<5> B;
 

lib/Target/PowerPC/PPCInstrInfo.td

 def IsE500  : Predicate<"PPCSubTarget->isE500()">;
 def HasSPE  : Predicate<"PPCSubTarget->HasSPE()">;
 def HasICBT : Predicate<"PPCSubTarget->hasICBT()">;
 def HasPartwordAtomics : Predicate<"PPCSubTarget->hasPartwordAtomics()">;
 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
 def NaNsFPMath   : Predicate<"!TM.Options.NoNaNsFPMath">;
 def HasBPERMD : Predicate<"PPCSubTarget->hasBPERMD()">;
 def HasExtDiv : Predicate<"PPCSubTarget->hasExtDiv()">;
+def IsISA3_0 : Predicate<"PPCSubTarget->isISA3_0()">;
 
 //===----------------------------------------------------------------------===//
 // PowerPC Multiclass Definitions.
 
 multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                     string asmbase, string asmstr, InstrItinClass itin,
                     list<dag> pattern> {
   let BaseName = asmbase in {
def LBARXL : XForm_1<31,  52, (outs gprc:$rD), (ins memrr:$src),
                      Requires<[HasPartwordAtomics]>;
 
 def LHARXL : XForm_1<31,  116, (outs gprc:$rD), (ins memrr:$src),
                      "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT,
                      Requires<[HasPartwordAtomics]>;
 
 def LWARXL : XForm_1<31,  20, (outs gprc:$rD), (ins memrr:$src),
                      "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isDOT;
+
+// The atomic instructions use the destination register as well as the next one
+// or two registers in order (modulo 31).
+let hasExtraSrcRegAllocReq = 1 in
+def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC),
+                         "lwat $rD, $rA, $FC", IIC_LdStLoad>,
+           Requires<[IsISA3_0]>;
 }
 
 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in {
 def STBCX : XForm_1<31, 694, (outs), (ins gprc:$rS, memrr:$dst),
                     "stbcx. $rS, $dst", IIC_LdStSTWCX, []>,
                     isDOT, Requires<[HasPartwordAtomics]>;
 
 def STHCX : XForm_1<31, 726, (outs), (ins gprc:$rS, memrr:$dst),
                     "sthcx. $rS, $dst", IIC_LdStSTWCX, []>,
                     isDOT, Requires<[HasPartwordAtomics]>;
 
 def STWCX : XForm_1<31, 150, (outs), (ins gprc:$rS, memrr:$dst),
                     "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isDOT;
 }
 
+let mayStore = 1, hasSideEffects = 0 in
+def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC),
+                          "stwat $rS, $rA, $FC", IIC_LdStStore>,
+            Requires<[IsISA3_0]>;
+
 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
 def TRAP  : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>;
 
 def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm),
                      "twi $to, $rA, $imm", IIC_IntTrapW, []>;
 def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB),
                  "tw $to, $rA, $rB", IIC_IntTrapW, []>;
 def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm),
def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
             PPC970_DGroup_First, PPC970_Unit_CRU;
 
 // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that
 // is dependent on the cr fields being copied.
 def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins),
                      "mfcr $rT", IIC_SprMFCR>,
                      PPC970_MicroCode, PPC970_Unit_CRU;
 } // hasExtraSrcRegAllocReq = 1
+
+def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
+                   "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
 } // hasSideEffects = 0
 
 // Pseudo instruction to perform FADD in round-to-zero mode.
 let usesCustomInserter = 1, Uses = [RM] in {
   def FADDrtz: Pseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "",
                       [(set f64:$FRT, (PPCfaddrtz f64:$FRA, f64:$FRB))]>;
 }
 

lib/Target/PowerPC/PPCSubtarget.h

protected:
   bool IsLittleEndian;
   bool HasICBT;
   bool HasInvariantFunctionDescriptors;
   bool HasPartwordAtomics;
   bool HasDirectMove;
   bool HasHTM;
   bool HasFusion;
   bool HasFloat128;
+  bool IsISA3_0;
 
   /// When targeting QPX running a stock PPC64 Linux kernel where the stack
   /// alignment has not been changed, we need to keep the 16-byte alignment
   /// of the stack.
   bool IsQPXStackUnaligned;
 
   const PPCTargetMachine &TM;
   PPCFrameLowering FrameLowering;
unsigned getPlatformStackAlignment() const {
     if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
       return 32;
 
     return 16;
   }
   bool hasHTM() const { return HasHTM; }
   bool hasFusion() const { return HasFusion; }
   bool hasFloat128() const { return HasFloat128; }
+  bool isISA3_0() const { return IsISA3_0; }
 
   const Triple &getTargetTriple() const { return TargetTriple; }
 
   /// isDarwin - True if this is any darwin platform.
   bool isDarwin() const { return TargetTriple.isMacOSX(); }
   /// isBGQ - True if this is a BG/Q platform.
   bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
 

lib/Target/PowerPC/PPCSubtarget.cpp

void PPCSubtarget::initializeEnvironment() {
   HasICBT = false;
   HasInvariantFunctionDescriptors = false;
   HasPartwordAtomics = false;
   HasDirectMove = false;
   IsQPXStackUnaligned = false;
   HasHTM = false;
   HasFusion = false;
   HasFloat128 = false;
+  IsISA3_0 = false;
 }
 
 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty() || CPU == "generic") {
     // If cross-compiling with -march=ppc64le without -mcpu
     if (TargetTriple.getArch() == Triple::ppc64le)

lib/Target/PowerPC/README_P9.txt

. (set v?:$XT, (int_ppc_vsx_lxvl xoaddr:$src))
     (set v?:$XT, (int_ppc_vsx_lxvll xoaddr:$src))
 
   . (int_ppc_vsx_stxvl xoaddr:$dst))
     (int_ppc_vsx_stxvll xoaddr:$dst))
 
 - Load Vector Word & Splat Indexed: lxvwsx
   . Likely needs an intrinsic
   . (set v?:$XT, (int_ppc_vsx_lxvwsx xoaddr:$src))
+
+Atomic operations (l[dw]at, st[dw]at):
+- Provide custom lowering for common atomic operations to use these
+  instructions with the correct Function Code
+- Ensure the operands are in the correct register (i.e. RT+1, RT+2)
+- Provide builtins since not all FC's necessarily have an existing LLVM
+  atomic operation
+
+Load Doubleword Monitored (ldmx):
+- Investigate whether there are any uses for this. It seems to be related to
+  Garbage Collection so it isn't likely to be all that useful for most
+  languages we deal with.
+
+Move to CR from XER Extended (mcrxrx):
+- Is there a use for this in LLVM?

test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt

 0x4c 0x00 0x01 0x2c
 
 # CHECK: stwcx. 2, 3, 4                  
 0x7c 0x43 0x21 0x2d
 
 # CHECK: stdcx. 2, 3, 4                  
 0x7c 0x43 0x21 0xad
 
+# CHECK: stwat 2, 3, 28
+0x7c 0x43 0xe5 0x8c
+
+# CHECK: stdat 2, 3, 28
+0x7c 0x43 0xe5 0xcc
+
 # CHECK: ptesync
 0x7c 0x40 0x04 0xac
 
 # CHECK: eieio                           
 0x7c 0x00 0x06 0xac
 
 # CHECK: waitimpl
 0x7c 0x40 0x00 0x7c

 0x7c 0x43 0x20 0xe9
 
 # CHECK: lwarx 2, 3, 4, 1
 0x7c 0x43 0x20 0x29
 
 # CHECK: ldarx 2, 3, 4, 1
 0x7c 0x43 0x20 0xa9
 
+# CHECK: lwat 2, 3, 28
+0x7c 0x43 0xe4 0x8c
+
+# CHECK: ldat 2, 3, 28
+0x7c 0x43 0xe4 0xcc
+
 # CHECK: sync
 0x7c 0x00 0x04 0xac
 
 # CHECK: sync
 0x7c 0x00 0x04 0xac
 
 # CHECK: lwsync
 0x7c 0x20 0x04 0xac

test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 0x7c 0x43 0x20 0x2a
 
 # CHECK: ldu 2, 128(4)                   
 0xe8 0x44 0x00 0x81
 
 # CHECK: ldux 2, 3, 4                    
 0x7c 0x43 0x20 0x6a
 
+# CHECK: ldmx 2, 3, 4
+0x7c 0x43 0x22 0x6a
+
 # CHECK: stb 2, 128(4)                   
 0x98 0x44 0x00 0x80
 
 # CHECK: stbx 2, 3, 4                    
 0x7c 0x43 0x21 0xae
 
 # CHECK: stbu 2, 128(4)                  
 0x9c 0x44 0x00 0x80

 0x7c 0x40 0x00 0x26
 
 # CHECK: mtocrf 16, 2                    
 0x7c 0x51 0x01 0x20
 
 # CHECK: mfocrf 16, 8                    
 0x7e 0x10 0x80 0x26
 
+# CHECK: mcrxrx 7
+0x7f 0x80 0x04 0x80
+
 # CHECK: mtsrin 10, 12
 0x7d 0x40 0x61 0xe4
+
 # CHECK: mfsrin 10, 12
 0x7d 0x40 0x65 0x26

test/MC/PowerPC/ppc64-encoding-bookII.s

 # CHECK-LE: isync                           # encoding: [0x2c,0x01,0x00,0x4c]
             isync
 
 # FIXME:    stbcx. 2, 3, 4
 # FIXME:    sthcx. 2, 3, 4
 # CHECK-BE: stwcx. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0x2d]
 # CHECK-LE: stwcx. 2, 3, 4                  # encoding: [0x2d,0x21,0x43,0x7c]
             stwcx. 2, 3, 4
+
 # CHECK-BE: stdcx. 2, 3, 4                  # encoding: [0x7c,0x43,0x21,0xad]
 # CHECK-LE: stdcx. 2, 3, 4                  # encoding: [0xad,0x21,0x43,0x7c]
             stdcx. 2, 3, 4
 
+# CHECK-BE: stwat 2, 3, 28                  # encoding: [0x7c,0x43,0xe5,0x8c]
+# CHECK-LE: stwat 2, 3, 28                  # encoding: [0x8c,0xe5,0x43,0x7c]
+            stwat 2, 3, 28
+
+# CHECK-BE: stdat 2, 3, 28                  # encoding: [0x7c,0x43,0xe5,0xcc]
+# CHECK-LE: stdat 2, 3, 28                  # encoding: [0xcc,0xe5,0x43,0x7c]
+            stdat 2, 3, 28
+
 # CHECK-BE: ptesync                         # encoding: [0x7c,0x40,0x04,0xac]
 # CHECK-LE: ptesync                         # encoding: [0xac,0x04,0x40,0x7c]
             sync 2
 # CHECK-BE: eieio                           # encoding: [0x7c,0x00,0x06,0xac]
 # CHECK-LE: eieio                           # encoding: [0xac,0x06,0x00,0x7c]
             eieio
 # CHECK-BE: waitimpl                        # encoding: [0x7c,0x40,0x00,0x7c]
 # CHECK-LE: waitimpl                        # encoding: [0x7c,0x00,0x40,0x7c]

 # CHECK-BE: lwarx 2, 3, 4, 1                # encoding: [0x7c,0x43,0x20,0x29]
 # CHECK-LE: lwarx 2, 3, 4, 1                # encoding: [0x29,0x20,0x43,0x7c]
             lwarx 2, 3, 4, 1
 
 # CHECK-BE: ldarx 2, 3, 4, 1                # encoding: [0x7c,0x43,0x20,0xa9]
 # CHECK-LE: ldarx 2, 3, 4, 1                # encoding: [0xa9,0x20,0x43,0x7c]
             ldarx 2, 3, 4, 1
 
+# CHECK-BE: lwat 2, 3, 28                   # encoding: [0x7c,0x43,0xe4,0x8c]
+# CHECK-LE: lwat 2, 3, 28                   # encoding: [0x8c,0xe4,0x43,0x7c]
+            lwat 2, 3, 28
+
+# CHECK-BE: ldat 2, 3, 28                   # encoding: [0x7c,0x43,0xe4,0xcc]
+# CHECK-LE: ldat 2, 3, 28                   # encoding: [0xcc,0xe4,0x43,0x7c]
+            ldat 2, 3, 28
+
 # CHECK-BE: sync                            # encoding: [0x7c,0x00,0x04,0xac]
 # CHECK-LE: sync                            # encoding: [0xac,0x04,0x00,0x7c]
             sync
 # CHECK-BE: sync                            # encoding: [0x7c,0x00,0x04,0xac]
 # CHECK-LE: sync                            # encoding: [0xac,0x04,0x00,0x7c]
             msync
 # CHECK-BE: lwsync                          # encoding: [0x7c,0x20,0x04,0xac]
 # CHECK-LE: lwsync                          # encoding: [0xac,0x04,0x20,0x7c]

test/MC/PowerPC/ppc64-encoding.s

 # CHECK-LE: ldx 2, 3, 4                     # encoding: [0x2a,0x20,0x43,0x7c]
             ldx 2, 3, 4
 # CHECK-BE: ldu 2, 128(4)                   # encoding: [0xe8,0x44,0x00,0x81]
 # CHECK-LE: ldu 2, 128(4)                   # encoding: [0x81,0x00,0x44,0xe8]
             ldu 2, 128(4)
 # CHECK-BE: ldux 2, 3, 4                    # encoding: [0x7c,0x43,0x20,0x6a]
 # CHECK-LE: ldux 2, 3, 4                    # encoding: [0x6a,0x20,0x43,0x7c]
             ldux 2, 3, 4
+# CHECK-BE: ldmx 2, 3, 4                    # encoding: [0x7c,0x43,0x22,0x6a]
+# CHECK-LE: ldmx 2, 3, 4                    # encoding: [0x6a,0x22,0x43,0x7c]
+            ldmx 2, 3, 4
 
 # Fixed-point store instructions
 
 # CHECK-BE: stb 2, 128(4)                   # encoding: [0x98,0x44,0x00,0x80]
 # CHECK-LE: stb 2, 128(4)                   # encoding: [0x80,0x00,0x44,0x98]
             stb 2, 128(4)
 # CHECK-BE: stbx 2, 3, 4                    # encoding: [0x7c,0x43,0x21,0xae]
 # CHECK-LE: stbx 2, 3, 4                    # encoding: [0xae,0x21,0x43,0x7c]

 # CHECK-LE: mfcr 2                          # encoding: [0x26,0x00,0x40,0x7c]
             mfcr 2
 # CHECK-BE: mtocrf 16, 2                    # encoding: [0x7c,0x51,0x01,0x20]
 # CHECK-LE: mtocrf 16, 2                    # encoding: [0x20,0x01,0x51,0x7c]
             mtocrf 16, 2
 # CHECK-BE: mfocrf 16, 8                    # encoding: [0x7e,0x10,0x80,0x26]
 # CHECK-LE: mfocrf 16, 8                    # encoding: [0x26,0x80,0x10,0x7e]
             mfocrf 16, 8
+# CHECK-BE: mcrxrx 7                        # encoding: [0x7f,0x80,0x04,0x80]
+# CHECK-LE: mcrxrx 7                        # encoding: [0x80,0x04,0x80,0x7f]
+            mcrxrx 7
 
 # Move to/from segment register
 # CHECK-BE: mtsr    12, 10                    # encoding: [0x7d,0x4c,0x01,0xa4]
 # CHECK-LE: mtsr    12, 10                    # encoding: [0xa4,0x01,0x4c,0x7d]
             mtsr    12,%r10
 # CHECK-BE: mfsr    10, 12                    # encoding: [0x7d,0x4c,0x04,0xa6]
 # CHECK-LE: mfsr    10, 12                    # encoding: [0xa6,0x04,0x4c,0x7d]
             mfsr    %r10,12
 
 # CHECK-BE: mtsrin  10, 12                    # encoding: [0x7d,0x40,0x61,0xe4]
 # CHECK-LE: mtsrin  10, 12                    # encoding: [0xe4,0x61,0x40,0x7d]
             mtsrin  %r10,%r12
 # CHECK-BE: mfsrin  10, 12                    # encoding: [0x7d,0x40,0x65,0x26]
 # CHECK-LE: mfsrin  10, 12                    # encoding: [0x26,0x65,0x40,0x7d]
             mfsrin  %r10,%r12