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[Power9] basic support for Power 9 direct move instructions
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Authored by amehsan on Mar 11 2016, 12:22 PM.

Details

Summary

Adding a feature and also define instructions in td files. After updating my repository I still do not see Power 9 processor model, so in the current code, the new feature is not used. I will add that to Power 9 processor model once that piece of code is committed.

Diff Detail

Event Timeline

amehsan updated this revision to Diff 50461.Mar 11 2016, 12:22 PM
amehsan retitled this revision from to [Power9] basic support for Power 9 direct move instructions.
amehsan updated this object.
amehsan added reviewers: kbarton, nemanjai, hfinkel.
amehsan added a subscriber: llvm-commits.
nemanjai added inline comments.Mar 14 2016, 3:29 AM
lib/Target/PowerPC/PPCInstrVSX.td
1247

Why 32-bit register inputs? The instruction takes two doubleword inputs in 64-bit registers and puts them in the VSR. The inputs should probably be:
(ins g8rc:$rA, g8rc:$rB).

1251

Same thing here. The output should be a 64-bit register.

amehsan added inline comments.Mar 17 2016, 4:11 AM
lib/Target/PowerPC/PPCInstrVSX.td
1247

That is an oversight. It does not impact encoding and decoding of the instruction, so testing was not able to catch it. That raises a quesiton: On Power8 and Power9 32 bit GPRs are the lower half of 64 bit GPRs and in 64 bit mode, the upper 32 bit cannot be accessed independently. So why do we need to distinguish between the two sets? I talked a little bit with other people and checked the source code and so far I do not have an answer for this question. One potential answer is that we need the distinction for processors that support some optional features of ISA, such as SPE. I will fix this anyway to be on the safe side.

amehsan updated this revision to Diff 50925.Mar 17 2016, 4:50 AM
nemanjai added inline comments.Mar 17 2016, 7:15 AM
lib/Target/PowerPC/PPCInstrVSX.td
1247

If you look at the definitions in lib/Target/PowerPC/PPCRegisterInfo.td, you'll see that the register classes have a different alignment/spill size. I am not aware of any other differences.

amehsan added inline comments.Mar 17 2016, 10:34 AM
lib/Target/PowerPC/PPCInstrVSX.td
1247

Then I suspect which one we use in a given instruction does not really matter (given how GPRC and G8RC are related to each other on Power). If that is the only difference, (and if tablegen language allows) I think a better design would have just one register class. But the alignment of that register class should be chosen depending on whether or not "In64BitMode" predicate is on or off.

nemanjai edited edge metadata.Mar 17 2016, 10:44 PM

I am not sure that tblgen actually supports this. I think what you're
suggesting is something along the lines of:

def GPRC : RegisterClass<"PPC", [i32], In64BitMode ? 64 : 32, ...

and I don't think that such functionality exists in tblgen. Of course, I
might be wrong.

kbarton accepted this revision.Mar 30 2016, 7:20 AM
kbarton edited edge metadata.

Some minor formatting changes, add the ISA3_0 feature, and change the input register class on one of the instructions.
With these changes, this LGTM.

lib/Target/PowerPC/PPC.td
137

Please remove blank lines to remain consistent with other feature definitions.

141

Please make sure this also requires the ISA3_0 feature that is defined in D18032

142

Remove blank line

lib/Target/PowerPC/PPCInstrVSX.td
1243

Please change this to g8rc:$rA

This revision is now accepted and ready to land.Mar 30 2016, 7:20 AM
kbarton added inline comments.Mar 30 2016, 8:05 AM
lib/Target/PowerPC/PPCInstrVSX.td
1243

I was wrong with this - gprc is the correct register class to use here.

amehsan added inline comments.Mar 30 2016, 5:38 PM
lib/Target/PowerPC/PPC.td
141

I believe we don't want P9DirectMove to imply ISA3_0, but as we discussed separately, I will totally remove this feature. I will guard the instructions with

let Predicate = [ISA3_0, HasDirectMove]

amehsan updated this revision to Diff 52241.Mar 31 2016, 10:45 AM
amehsan edited edge metadata.

Removing P9DirectMove feature

amehsan closed this revision.Mar 31 2016, 10:53 AM

Committed r265031.