[mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPSr6 SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions:

• added DAG patterns for proper selection of shift instructions
• added alias definitions for microMIPS instructions
• separated microMIPS instructions from equivalent MIPS instructions using NotInMicroMips predicate
• updated .ll files with tests for microMIPSr6 instructions
• added tests for the standard encodings
• added invalid operand tests
• fixed opcode strings in desc. classes for a couple of 16-bit instructions

[sdardis]

Comments inlined. Can you rebase and repost?

test/CodeGen/Mips/llvm-ir/ashr.ll

229

Since you've posted this patch, the LLVM backend for MIPS was changed to use the static relocation model, so this should be:

jals      __ashrti3

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

192–200

sllv, srav and srlv appear twice here. Once is enough. There are more occurrences in the other tests.

[zbuljan]

Rebased to work with TOT.
Added -relocation-model=pic switch to microMIPS CodeGen tests for consistency with other tests.
Removed redundant tests for sllv, srav and srlv.

[sdardis]

LGTM.

lib/Target/Mips/MicroMips32r6InstrInfo.td

class ANDI16_MMR6_DESC : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>,
       MMR6Arch<"andi16">;
 class NOT16_MMR6_DESC : NotMM16<"not16", GPRMM16Opnd>, MMR6Arch<"not16">;
 class OR16_MMR6_DESC : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
       MMR6Arch<"or16">;
 class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
       MMR6Arch<"sll16">;
 class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
       MMR6Arch<"srl16">;
-class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"srl16">,
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">,
       MicroMipsR6Inst16;
 class LI16_MMR6_DESC : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd>,
-      MMR6Arch<"srl16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
-class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"srl16">,
+      MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
+class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
       MicroMipsR6Inst16;
 class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
       MicroMipsR6Inst16;
 class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
-      MMR6Arch<"sdbbp16">, MicroMipsR6Inst16;
+      MMR6Arch<"subu16">, MicroMipsR6Inst16;
 class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-      MMR6Arch<"sdbbp16">;
+      MMR6Arch<"xor16">;
 
 class LW_MMR6_DESC : MMR6Arch<"lw">, MipsR6Inst {
   dag OutOperandList = (outs GPR32Opnd:$rt);
   dag InOperandList = (ins mem:$addr);
   string AsmString = "lw\t$rt, $addr";
   let DecoderMethod = "DecodeMemMMImm16";
   let canFoldAsLoad = 1;
   let mayLoad = 1;

lib/Target/Mips/MicroMipsInstrInfo.td

def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
               (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
               (ANDi_MM GPR32:$src, immZExt16:$imm)>;
 
 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
               (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
               (SLL_MM GPR32:$src, immZExt5:$imm)>;
+def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
+              (SLLV_MM GPR32:$lhs, GPR32:$rhs)>;
 
 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
               (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>;
 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
               (SRL_MM GPR32:$src, immZExt5:$imm)>;
+def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
+              (SRLV_MM GPR32:$lhs, GPR32:$rhs)>;
+
+def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
+              (SRA_MM GPR32:$src, immZExt5:$imm)>;
+def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
+              (SRAV_MM GPR32:$lhs, GPR32:$rhs)>;
 
 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
               (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
 def : MipsPat<(store GPR32:$src, addr:$addr),
               (SW_MM GPR32:$src, addr:$addr)>;
 
 def : MipsPat<(load addrimm4lsl2:$addr),
               (LW16_MM addrimm4lsl2:$addr)>;

 def : MipsInstAlias<"tgeu $rs, $rt",
                     (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"tlt $rs, $rt",
                     (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"tltu $rs, $rt",
                     (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
 def : MipsInstAlias<"tne $rs, $rt",
                     (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
+def : MipsInstAlias<"sll $rd, $rt, $rs",
+                    (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"sra $rd, $rt, $rs",
+                    (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"srl $rd, $rt, $rs",
+                    (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+def : MipsInstAlias<"sll $rd, $rt",
+                    (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"sra $rd, $rt",
+                    (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"srl $rd, $rt",
+                    (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
+def : MipsInstAlias<"sll $rd, $shamt",
+                    (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
+def : MipsInstAlias<"sra $rd, $shamt",
+                    (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
+def : MipsInstAlias<"srl $rd, $shamt",
+                    (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
 }

lib/Target/Mips/MipsInstrInfo.td

 def NOR   : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
 
 /// Shift Instructions
 let AdditionalPredicates = [NotInMicroMips] in {
 def SLL  : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
                                    immZExt5>, SRA_FM<0, 0>;
 def SRL  : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
                                    immZExt5>, SRA_FM<2, 0>;
-}
 def SRA  : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
                                    immZExt5>, SRA_FM<3, 0>;
 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
            SRLV_FM<4, 0>;
 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
            SRLV_FM<6, 0>;
 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
            SRLV_FM<7, 0>;
+}
 
 // Rotate Instructions
 def ROTR  : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
                                     immZExt5>,
             SRA_FM<2, 1>, ISA_MIPS32R2;
 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
             SRLV_FM<6, 1>, ISA_MIPS32R2;
 
def : MipsInstAlias<"tgeu $rs, $rt",
                       (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
   def : MipsInstAlias<"tlt $rs, $rt",
                       (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
   def : MipsInstAlias<"tltu $rs, $rt",
                       (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
   def : MipsInstAlias<"tne $rs, $rt",
                       (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
 }
-def  : MipsInstAlias<"sll $rd, $rt, $rs",
-                     (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
 def : MipsInstAlias<"sub, $rd, $rs, $imm",
                     (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
                           InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
 def : MipsInstAlias<"sub $rs, $imm",
                     (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
                     0>, ISA_MIPS1_NOT_32R6_64R6;
 def : MipsInstAlias<"subu, $rd, $rs, $imm",
                     (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
                            InvertedImOperand:$imm), 0>;
 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
                                              InvertedImOperand:$imm), 0>;
+let AdditionalPredicates = [NotInMicroMips] in {
+  def : MipsInstAlias<"sll $rd, $rt, $rs",
+                      (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"sra $rd, $rt, $rs",
                       (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
   def : MipsInstAlias<"srl $rd, $rt, $rs",
                       (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
+}
 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
 def : MipsInstAlias<"sync",
                     (SYNC 0), 1>, ISA_MIPS2;
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :

test/CodeGen/Mips/llvm-ir/ashr.ll

 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
 
 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i1:
 
   ; ALL:        move    $2, $4
 
   %r = ashr i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i8:
 
   ; FIXME: The andi instruction is redundant.
-  ; ALL:        andi    $[[T0:[0-9]+]], $5, 255
+  ; GP32:       andi    $[[T0:[0-9]+]], $5, 255
+  ; GP64:       andi    $[[T0:[0-9]+]], $5, 255
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 255
   ; ALL:        srav    $2, $4, $[[T0]]
 
   %r = ashr i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i16:
 
   ; FIXME: The andi instruction is redundant.
-  ; ALL:        andi    $[[T0:[0-9]+]], $5, 65535
+  ; GP32:       andi    $[[T0:[0-9]+]], $5, 65535
+  ; GP64:       andi    $[[T0:[0-9]+]], $5, 65535
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 65535
   ; ALL:        srav    $2, $4, $[[T0]]
 
   %r = ashr i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) {
 entry:
; ALL-LABEL: ashr_i64:
   ; 32R6:       or        $[[T10:[0-9]+]], $[[T9]], $[[T6]]
   ; 32R6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
   ; 32R6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
   ; 32R6:       jr        $ra
   ; 32R6:       or        $3, $[[T0]], $[[T11]]
 
   ; GP64:       dsrav     $2, $4, $5
 
+  ; MMR3:       srlv      $[[T0:[0-9]+]], $5, $7
+  ; MMR3:       sll16     $[[T1:[0-9]+]], $4, 1
+  ; MMR3:       not16     $[[T2:[0-9]+]], $7
+  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR3:       srav      $[[T5:[0-9]+]], $4, $7
+  ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
+  ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; MMR3:       sra       $[[T8:[0-9]+]], $4, 31
+  ; MMR3:       movn      $2, $[[T8]], $[[T6]]
+
+  ; MMR6:       srav      $[[T0:[0-9]+]], $4, $7
+  ; MMR6:       andi16    $[[T1:[0-9]+]], $7, 32
+  ; MMR6:       seleqz    $[[T2:[0-9]+]], $[[T0]], $[[T1]]
+  ; MMR6:       sra       $[[T3:[0-9]+]], $4, 31
+  ; MMR6:       selnez    $[[T4:[0-9]+]], $[[T3]], $[[T1]]
+  ; MMR6:       or        $[[T5:[0-9]+]], $[[T4]], $[[T2]]
+  ; MMR6:       srlv      $[[T6:[0-9]+]], $5, $7
+  ; MMR6:       not       $[[T7:[0-9]+]], $7
+  ; MMR6:       sll16     $[[T8:[0-9]+]], $4, 1
+  ; MMR6:       sllv      $[[T9:[0-9]+]], $[[T8]], $[[T7]]
+  ; MMR6:       or16      $[[T10:[0-9]+]], $[[T6]]
+  ; MMR6:       seleqz    $[[T11:[0-9]+]], $[[T10]], $[[T1]]
+  ; MMR6:       selnez    $[[T12:[0-9]+]], $[[T0]], $[[T1]]
+  ; MMR6:       or        $3, $[[T12]], $[[T11]]
+
   %r = ashr i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: ashr_i128:
 
; ALL-LABEL: ashr_i128:
   ; 64R6:           not       $[[T9:[0-9]+]], $[[T1]]
   ; 64R6:           dsllv     $[[T10:[0-9]+]], $[[T8]], $[[T9]]
   ; 64R6:           or        $[[T11:[0-9]+]], $[[T10]], $[[T7]]
   ; 64R6:           seleqz    $[[T12:[0-9]+]], $[[T11]], $[[T3]]
   ; 64R6:           selnez    $[[T13:[0-9]+]], $[[T0]], $[[T3]]
   ; 64R6:           jr        $ra
   ; 64R6:           or        $3, $[[T13]], $[[T12]]
 
+  ; MM:             lw        $25, %call16(__ashrti3)($2)
+
   %r = ashr i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/lshr.ll

 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
 
 define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i1:
 
   ; ALL:        move    $2, $4
 
   %r = lshr i1 %a, %b
   ret i1 %r
 }
 
 define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) {
 entry:
 ; ALL-LABEL: lshr_i8:
 
   ; ALL:        srlv    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        andi    $2, $[[T0]], 255
+  ; GP32:       andi    $2, $[[T0]], 255
+  ; GP64:       andi    $2, $[[T0]], 255
+  ; MM:         andi16  $2, $[[T0]], 255
 
   %r = lshr i8 %a, %b
   ret i8 %r
 }
 
 define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) {
 entry:
 ; ALL-LABEL: lshr_i16:
 
   ; ALL:        srlv    $[[T0:[0-9]+]], $4, $5
-  ; ALL:        andi    $2, $[[T0]], 65535
+  ; GP32:       andi    $2, $[[T0]], 65535
+  ; GP64:       andi    $2, $[[T0]], 65535
+  ; MM:         andi16  $2, $[[T0]], 65535
 
   %r = lshr i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i32:
; ALL-LABEL: lshr_i64:
   ; 32R6:       srlv      $[[T7:[0-9]+]], $4, $7
   ; 32R6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
   ; 32R6:       or        $3, $[[T8]], $[[T6]]
   ; 32R6:       jr        $ra
   ; 32R6:       seleqz    $2, $[[T7]], $[[T5]]
 
   ; GP64:         dsrlv   $2, $4, $5
 
+  ; MMR3:       srlv      $[[T0:[0-9]+]], $5, $7
+  ; MMR3:       sll16     $[[T1:[0-9]+]], $4, 1
+  ; MMR3:       not16     $[[T2:[0-9]+]], $7
+  ; MMR3:       sllv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR3:       srlv      $[[T5:[0-9]+]], $4, $7
+  ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
+  ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; MMR3:       lui       $[[T8:[0-9]+]], 0
+  ; MMR3:       movn      $2, $[[T8]], $[[T6]]
+
+  ; MMR6:       srlv      $[[T0:[0-9]+]], $5, $7
+  ; MMR6:       not       $[[T1:[0-9]+]], $7
+  ; MMR6:       sll16     $[[T2:[0-9]+]], $4, 1
+  ; MMR6:       sllv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
+  ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
+  ; MMR6:       srlv      $[[T7:[0-9]+]], $4, $7
+  ; MMR6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+  ; MMR6:       or        $3, $[[T8]], $[[T6]]
+  ; MMR6:       seleqz    $2, $[[T7]], $[[T5]]
+
   %r = lshr i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: lshr_i128:
 
; ALL-LABEL: lshr_i128:
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsrlv     $[[T9:[0-9]+]], $4, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $3, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $2, $[[T9]], $[[T7]]
 
+  ; MM:             lw        $25, %call16(__lshrti3)($2)
+
   %r = lshr i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/llvm-ir/shl.ll

 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefix=ALL -check-prefix=GP64 \
 ; RUN:    -check-prefix=64R6 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6
 
 define signext i1 @shl_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: shl_i1:
 
   ; ALL:        move    $2, $4
 
   %r = shl i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @shl_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: shl_i8:
 
   ; NOT-R2-R6:  andi    $[[T0:[0-9]+]], $5, 255
   ; NOT-R2-R6:  sllv    $[[T1:[0-9]+]], $4, $[[T0]]
   ; NOT-R2-R6:  sll     $[[T2:[0-9]+]], $[[T1]], 24
   ; NOT-R2-R6:  sra     $2, $[[T2]], 24
 
   ; R2-R6:      andi    $[[T0:[0-9]+]], $5, 255
   ; R2-R6:      sllv    $[[T1:[0-9]+]], $4, $[[T0]]
   ; R2-R6:      seb     $2, $[[T1]]
 
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 255
+  ; MM:         sllv    $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MM:         seb     $2, $[[T1]]
+
   %r = shl i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @shl_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: shl_i16:
 
   ; NOT-R2-R6:  andi    $[[T0:[0-9]+]], $5, 65535
   ; NOT-R2-R6:  sllv    $[[T1:[0-9]+]], $4, $[[T0]]
   ; NOT-R2-R6:  sll     $[[T2:[0-9]+]], $[[T1]], 16
   ; NOT-R2-R6:  sra     $2, $[[T2]], 16
 
   ; R2-R6:      andi    $[[T0:[0-9]+]], $5, 65535
   ; R2-R6:      sllv    $[[T1:[0-9]+]], $4, $[[T0]]
   ; R2-R6:      seh     $2, $[[T1]]
 
+  ; MM:         andi16  $[[T0:[0-9]+]], $5, 65535
+  ; MM:         sllv    $[[T1:[0-9]+]], $4, $[[T0]]
+  ; MM:         seh     $2, $[[T1]]
+
   %r = shl i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @shl_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: shl_i32:
 
; ALL-LABEL: shl_i64:
   ; 32R6:       sllv      $[[T7:[0-9]+]], $5, $7
   ; 32R6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
   ; 32R6:       or        $2, $[[T8]], $[[T6]]
   ; 32R6:       jr        $ra
   ; 32R6:       seleqz    $3, $[[T7]], $[[T5]]
 
   ; GP64:       dsllv     $2, $4, $5
 
+  ; MMR3:       sllv      $[[T0:[0-9]+]], $4, $7
+  ; MMR3:       srl16     $[[T1:[0-9]+]], $5, 1
+  ; MMR3:       not16     $[[T2:[0-9]+]], $7
+  ; MMR3:       srlv      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; MMR3:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR3:       sllv      $[[T5:[0-9]+]], $5, $7
+  ; MMR3:       andi16    $[[T6:[0-9]+]], $7, 32
+  ; MMR3:       movn      $[[T7:[0-9]+]], $[[T5]], $[[T6]]
+  ; MMR3:       lui       $[[T8:[0-9]+]], 0
+  ; MMR3:       movn      $3, $[[T8]], $[[T6]]
+
+  ; MMR6:       sllv      $[[T0:[0-9]+]], $4, $7
+  ; MMR6:       not       $[[T1:[0-9]+]], $7
+  ; MMR6:       srl16     $[[T2:[0-9]+]], $5, 1
+  ; MMR6:       srlv      $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+  ; MMR6:       or16      $[[T4:[0-9]+]], $[[T0]]
+  ; MMR6:       andi16    $[[T5:[0-9]+]], $7, 32
+  ; MMR6:       seleqz    $[[T6:[0-9]+]], $[[T4]], $[[T5]]
+  ; MMR6:       sllv      $[[T7:[0-9]+]], $5, $7
+  ; MMR6:       selnez    $[[T8:[0-9]+]], $[[T7]], $[[T5]]
+  ; MMR6:       or        $2, $[[T8]], $[[T6]]
+  ; MMR6:       seleqz    $3, $[[T7]], $[[T5]]
+
   %r = shl i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @shl_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: shl_i128:
 
; ALL-LABEL: shl_i128:
   ; 64R6:           sll       $[[T7:[0-9]+]], $[[T6]], 0
   ; 64R6:           seleqz    $[[T8:[0-9]+]], $[[T5]], $[[T7]]
   ; 64R6:           dsllv     $[[T9:[0-9]+]], $5, $7
   ; 64R6:           selnez    $[[T10:[0-9]+]], $[[T9]], $[[T7]]
   ; 64R6:           or        $2, $[[T10]], $[[T8]]
   ; 64R6:           jr        $ra
   ; 64R6:           seleqz    $3, $[[T9]], $[[T7]]
 
+  ; MM:             lw        $25, %call16(__ashlti3)($2)
+
   %r = shl i128 %a, %b
   ret i128 %r
 }

test/CodeGen/Mips/micromips-shift.ll

 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
 ; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
 
 @a = global i32 10, align 4
 @b = global i32 0, align 4
 @c = global i32 10, align 4
 @d = global i32 0, align 4
 
 define i32 @shift_left() nounwind {
 entry:

test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

 0xa4 0x60 0x08 0xaa # CHECK: she $5, 8($4)
 0xa4 0x60 0x08 0xae # CHECK: swe $5, 8($4)
 0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3)
 0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3)
 0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3)
 0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4)
 0x44 0x60 0x08 0x6c # CHECK: lle $2, 8($4)
 0x44 0x60 0x08 0xac # CHECK: sce $2, 8($4)
+0x65 0x00 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x65 0x00 0x90 0x10 # CHECK: srav $2, $3, $5
+0x65 0x00 0x50 0x10 # CHECK: srlv $2, $3, $5
+0x43 0x00 0x10 0x10 # CHECK: sllv $2, $2, $3
+0x43 0x00 0x90 0x10 # CHECK: srav $2, $2, $3
+0x43 0x00 0x50 0x10 # CHECK: srlv $2, $2, $3
+0x63 0x00 0x00 0x38 # CHECK: sll $3, $3, 7
+0x63 0x00 0x80 0x38 # CHECK: sra $3, $3, 7
+0x63 0x00 0x40 0x38 # CHECK: srl $3, $3, 7

test/MC/Disassembler/Mips/micromips32r3/valid.txt

 0x60 0xa4 0xaa 0x08 # CHECK: she $5, 8($4)
 0x60 0xa4 0xae 0x08 # CHECK: swe $5, 8($4)
 0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3)
 0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3)
 0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3)
 0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4)
 0x60 0x44 0x6c 0x08 # CHECK: lle $2, 8($4)
 0x60 0x44 0xac 0x08 # CHECK: sce $2, 8($4)
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
+0x00 0x43 0x10 0x10 # CHECK: sllv $2, $2, $3
+0x00 0x43 0x10 0x90 # CHECK: srav $2, $2, $3
+0x00 0x43 0x10 0x50 # CHECK: srlv $2, $2, $3
+0x00 0x63 0x38 0x00 # CHECK: sll $3, $3, 7
+0x00 0x63 0x38 0x80 # CHECK: sra $3, $3, 7
+0x00 0x63 0x38 0x40 # CHECK: srl $3, $3, 7

test/MC/Disassembler/Mips/micromips32r6/valid.txt

 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
 0x00 0x00 0x43 0x7c # CHECK: tlbinv
 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
+0x00 0x43 0x10 0x10 # CHECK: sllv $2, $2, $3
+0x00 0x43 0x10 0x90 # CHECK: srav $2, $2, $3
+0x00 0x43 0x10 0x50 # CHECK: srlv $2, $2, $3
+0x00 0x63 0x38 0x00 # CHECK: sll $3, $3, 7
+0x00 0x63 0x38 0x80 # CHECK: sra $3, $3, 7
+0x00 0x63 0x38 0x40 # CHECK: srl $3, $3, 7

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
 0x00 0x00 0x43 0x7c # CHECK: tlbinv
 0x00 0x00 0x53 0x7c # CHECK: tlbinvf
 0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5
 0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5
 0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5
+0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
+0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
+0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
+0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
+0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
+0x00 0x43 0x10 0x10 # CHECK: sllv $2, $2, $3
+0x00 0x43 0x10 0x90 # CHECK: srav $2, $2, $3
+0x00 0x43 0x10 0x50 # CHECK: srlv $2, $2, $3
+0x00 0x63 0x38 0x00 # CHECK: sll $3, $3, 7
+0x00 0x63 0x38 0x80 # CHECK: sra $3, $3, 7
+0x00 0x63 0x38 0x40 # CHECK: srl $3, $3, 7

test/MC/Mips/micromips-shift-instructions.s

 # CHECK-EL: sll    $4, $3, 7      # encoding: [0x83,0x00,0x00,0x38]
 # CHECK-EL: sllv   $2, $3, $5     # encoding: [0x65,0x00,0x10,0x10]
 # CHECK-EL: sra    $4, $3, 7      # encoding: [0x83,0x00,0x80,0x38]
 # CHECK-EL: srav   $2, $3, $5     # encoding: [0x65,0x00,0x90,0x10]
 # CHECK-EL: srl    $4, $3, 7      # encoding: [0x83,0x00,0x40,0x38]
 # CHECK-EL: srlv   $2, $3, $5     # encoding: [0x65,0x00,0x50,0x10]
 # CHECK-EL: rotr   $9, $6, 7      # encoding: [0x26,0x01,0xc0,0x38]
 # CHECK-EL: rotrv  $9, $6, $7     # encoding: [0xc7,0x00,0xd0,0x48]
+# CHECK-EL: sllv   $2, $3, $5     # encoding: [0x65,0x00,0x10,0x10]
+# CHECK-EL: srav   $2, $3, $5     # encoding: [0x65,0x00,0x90,0x10]
+# CHECK-EL: srlv   $2, $3, $5     # encoding: [0x65,0x00,0x50,0x10]
+# CHECK-EL: sllv   $2, $2, $3     # encoding: [0x43,0x00,0x10,0x10]
+# CHECK-EL: srav   $2, $2, $3     # encoding: [0x43,0x00,0x90,0x10]
+# CHECK-EL: srlv   $2, $2, $3     # encoding: [0x43,0x00,0x50,0x10]
+# CHECK-EL: sll    $3, $3, 7      # encoding: [0x63,0x00,0x00,0x38]
+# CHECK-EL: sra    $3, $3, 7      # encoding: [0x63,0x00,0x80,0x38]
+# CHECK-EL: srl    $3, $3, 7      # encoding: [0x63,0x00,0x40,0x38]
 #------------------------------------------------------------------------------
 # Big endian
 #------------------------------------------------------------------------------
 # CHECK-EB: sll $4, $3, 7         # encoding: [0x00,0x83,0x38,0x00]
 # CHECK-EB: sllv  $2, $3, $5      # encoding: [0x00,0x65,0x10,0x10]
 # CHECK-EB: sra $4, $3, 7         # encoding: [0x00,0x83,0x38,0x80]
 # CHECK-EB: srav  $2, $3, $5      # encoding: [0x00,0x65,0x10,0x90]
 # CHECK-EB: srl $4, $3, 7         # encoding: [0x00,0x83,0x38,0x40]
 # CHECK-EB: srlv  $2, $3, $5      # encoding: [0x00,0x65,0x10,0x50]
 # CHECK-EB: rotr  $9, $6, 7       # encoding: [0x01,0x26,0x38,0xc0]
 # CHECK-EB: rotrv $9, $6, $7      # encoding: [0x00,0xc7,0x48,0xd0]
+# CHECK-EB: sllv $2, $3, $5       # encoding: [0x00,0x65,0x10,0x10]
+# CHECK-EB: srav $2, $3, $5       # encoding: [0x00,0x65,0x10,0x90]
+# CHECK-EB: srlv $2, $3, $5       # encoding: [0x00,0x65,0x10,0x50]
+# CHECK-EB: sllv $2, $2, $3       # encoding: [0x00,0x43,0x10,0x10]
+# CHECK-EB: srav $2, $2, $3       # encoding: [0x00,0x43,0x10,0x90]
+# CHECK-EB: srlv $2, $2, $3       # encoding: [0x00,0x43,0x10,0x50]
+# CHECK-EB: sll $3, $3, 7         # encoding: [0x00,0x63,0x38,0x00]
+# CHECK-EB: sra $3, $3, 7         # encoding: [0x00,0x63,0x38,0x80]
+# CHECK-EB: srl $3, $3, 7         # encoding: [0x00,0x63,0x38,0x40]
      sll    $4, $3, 7
      sllv   $2, $3, $5
      sra    $4, $3, 7
      srav   $2, $3, $5
      srl    $4, $3, 7
      srlv   $2, $3, $5
      rotr   $9, $6, 7
      rotrv  $9, $6, $7
+     sll    $2, $3, $5
+     sra    $2, $3, $5
+     srl    $2, $3, $5
+     sll    $2, $3
+     sra    $2, $3
+     srl    $2, $3
+     sll    $3, 7
+     sra    $3, 7
+     srl    $3, 7

test/MC/Mips/micromips/invalid.s

# RUN: FileCheck %s < %t1
   sra $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   sra $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, -1      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   srl $2, $3, 32      # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   ins $2, $3, -1, 1   # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   ins $2, $3, 32, 1   # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
   ins $2, $3, 0, -1   # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
   ins $2, $3, 0, 33   # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
+  sll $3, -1          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sll $3, 32          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, -1          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, 32          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, -1          # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate

test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
   swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sll $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate

test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   seleqz.d $f2, $f4, $f8   # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
   selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
   selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
   class.s $f2, $f3         # CHECK: class.s $f2, $f3       # encoding: [0x54,0x62,0x00,0x60]
   class.d $f2, $f4         # CHECK: class.d $f2, $f4       # encoding: [0x54,0x82,0x02,0x60]
   deret                    # CHECK: deret                  # encoding: [0x00,0x00,0xe3,0x7c]
   tlbinv                   # CHECK: tlbinv                 # encoding: [0x00,0x00,0x43,0x7c]
   tlbinvf                  # CHECK: tlbinvf                # encoding: [0x00,0x00,0x53,0x7c]
+  sllv $2, $3, $5          # CHECK: sllv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x10]
+  sra $4, $3, 7            # CHECK: sra $4, $3, 7          # encoding: [0x00,0x83,0x38,0x80]
+  srav $2, $3, $5          # CHECK: srav $2, $3, $5        # encoding: [0x00,0x65,0x10,0x90]
+  srl $4, $3, 7            # CHECK: srl $4, $3, 7          # encoding: [0x00,0x83,0x38,0x40]
+  srlv $2, $3, $5          # CHECK: srlv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x50]
+  sll $2, $3, $5           # CHECK: sllv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x10]
+  sra $2, $3, $5           # CHECK: srav $2, $3, $5        # encoding: [0x00,0x65,0x10,0x90]
+  srl $2, $3, $5           # CHECK: srlv $2, $3, $5        # encoding: [0x00,0x65,0x10,0x50]
+  sll $2, $3               # CHECK: sllv $2, $2, $3        # encoding: [0x00,0x43,0x10,0x10]
+  sra $2, $3               # CHECK: srav $2, $2, $3        # encoding: [0x00,0x43,0x10,0x90]
+  srl $2, $3               # CHECK: srlv $2, $2, $3        # encoding: [0x00,0x43,0x10,0x50]
+  sll $3, 7                # CHECK: sll $3, $3, 7          # encoding: [0x00,0x63,0x38,0x00]
+  sra $3, 7                # CHECK: sra $3, $3, 7          # encoding: [0x00,0x63,0x38,0x80]
+  srl $3, 7                # CHECK: srl $3, $3, 7          # encoding: [0x00,0x63,0x38,0x40]

test/MC/Mips/micromips64r6/invalid.s

# RUN: FileCheck %s < %t1
   swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
   swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
   swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
   swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
   swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+  sll $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sra $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, -1           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  srl $4, $3, 32           # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
+  sll $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sll $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  sra $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, -1               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
+  srl $3, 32               # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate

test/MC/Mips/micromips64r6/valid.s

a:
         ceil.l.d $f1, $f3        # CHECK: ceil.l.d $f1, $f3       # encoding: [0x54,0x23,0x53,0x3b]
         floor.l.s $f1, $f3       # CHECK: floor.l.s $f1, $f3      # encoding: [0x54,0x23,0x03,0x3b]
         floor.l.d $f1, $f3       # CHECK: floor.l.d $f1, $f3      # encoding: [0x54,0x23,0x43,0x3b]
         tlbinv                   # CHECK: tlbinv                  # encoding: [0x00,0x00,0x43,0x7c]
         tlbinvf                  # CHECK: tlbinvf                 # encoding: [0x00,0x00,0x53,0x7c]
         dinsu $4, $2, 32, 5      # CHECK: dinsu $4, $2, 32, 5     # encoding: [0x58,0x82,0x20,0x34]
         dinsm $4, $2, 3, 5       # CHECK: dinsm $4, $2, 3, 5      # encoding: [0x58,0x82,0x38,0xc4]
         dins $4, $2, 3, 5        # CHECK: dins $4, $2, 3, 5       # encoding: [0x58,0x82,0x38,0xcc]
+        sllv $2, $3, $5          # CHECK: sllv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x10]
+        sra $4, $3, 7            # CHECK: sra $4, $3, 7           # encoding: [0x00,0x83,0x38,0x80]
+        srav $2, $3, $5          # CHECK: srav $2, $3, $5         # encoding: [0x00,0x65,0x10,0x90]
+        srl $4, $3, 7            # CHECK: srl $4, $3, 7           # encoding: [0x00,0x83,0x38,0x40]
+        srlv $2, $3, $5          # CHECK: srlv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x50]
+        sll $2, $3, $5           # CHECK: sllv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x10]
+        sra $2, $3, $5           # CHECK: srav $2, $3, $5         # encoding: [0x00,0x65,0x10,0x90]
+        srl $2, $3, $5           # CHECK: srlv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x50]
+        sll $2, $3               # CHECK: sllv $2, $2, $3         # encoding: [0x00,0x43,0x10,0x10]
+        sra $2, $3               # CHECK: srav $2, $2, $3         # encoding: [0x00,0x43,0x10,0x90]
+        srl $2, $3               # CHECK: srlv $2, $2, $3         # encoding: [0x00,0x43,0x10,0x50]
+        sll $3, 7                # CHECK: sll $3, $3, 7           # encoding: [0x00,0x63,0x38,0x00]
+        sra $3, 7                # CHECK: sra $3, $3, 7           # encoding: [0x00,0x63,0x38,0x80]
+        srl $3, 7                # CHECK: srl $3, $3, 7           # encoding: [0x00,0x63,0x38,0x40]
+
 1: