[AMDGPU] Disassembler: Support for all VOP1 instructions.

[SamWot]

Summary

Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget:

• VGPR_32 and VReg_64 operand register classes
• VS_32 and VS_64 operand register classes with inline and literal constants
• Tests for VOP1 instructions.

This change contains changes from reviews D16723 and D16920 because it is dependent on them.

[SamWot]

Updated review with latests LLVM master

[SamWot]

Fix dmask encoding

[• tstellarAMD]

Did you upload the wrong patch? This seems to be a combination of the original disassembler patch and also the one that adds VOP1 support.

[SamWot]

In D17194#357549, @tstellarAMD wrote:

Did you upload the wrong patch? This seems to be a combination of the original disassembler patch and also the one that adds VOP1 support.

This patch contain changes from original disassembler patch. This was made intentionally, because review was created before original disassembler was submitted to master and without it this patch doesn't work and doesn't apply to LLVM master. Now this is not needed and I will update review.

[SamWot]

Updated patch

[• tstellarAMD]

LGTM, but there are 3 warnings which need to be fixed before committing.

[SamWot]

Fix warnings

[SamWot]

Submitted by nhaustov

lib/Target/AMDGPU/AMDGPUInstructions.td

class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
 
   let Namespace = "AMDGPU";
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString = asm;
   let Pattern = pattern;
   let Itinerary = NullALU;
 
+  // SoftFail is a field the disassembler can use to provide a way for
+  // instructions to not match without killing the whole decode process. It is
+  // mainly used for ARM, but Tablegen expects this field to exist or it fails
+  // to build the decode table.
+  field bits<64> SoftFail = 0;
+
+  let DecoderNamespace = Namespace;
+  
   let TSFlags{63} = isRegisterLoad;
   let TSFlags{62} = isRegisterStore;
 }
 
 class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
     : AMDGPUInst<outs, ins, asm, pattern> {
 
   field bits<32> Inst = 0xffffffff;

lib/Target/AMDGPU/CIInstructions.td

 
 defm S_DCACHE_INV_VOL : SMRD_Inval <smrd<0x1d, 0x22>,
   "s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
 
 //===----------------------------------------------------------------------===//
 // MUBUF Instructions
 //===----------------------------------------------------------------------===//
 
+let DisableSIDecoder = 1 in {
 defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,
   "buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol
 >;
+}
 
 //===----------------------------------------------------------------------===//
 // Flat Instructions
 //===----------------------------------------------------------------------===//
 
 defm FLAT_LOAD_UBYTE : FLAT_Load_Helper <
   flat<0x8, 0x10>, "flat_load_ubyte", VGPR_32
 >;

 defm FLAT_ATOMIC_DEC_X2 : FLAT_ATOMIC <
   flat<0x5d, 0x6c>, "flat_atomic_dec_x2", VReg_64
 >;
 
 } // End SubtargetPredicate = isCIVI
 
 // CI Only flat instructions
 
-let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst in {
+let SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst, DisableVIDecoder = 1 in {
 
 defm FLAT_ATOMIC_FCMPSWAP : FLAT_ATOMIC <
   flat<0x3e>, "flat_atomic_fcmpswap", VGPR_32, VReg_64
 >;
 defm FLAT_ATOMIC_FMIN : FLAT_ATOMIC <
   flat<0x3f>, "flat_atomic_fmin", VGPR_32
 >;
 defm FLAT_ATOMIC_FMAX : FLAT_ATOMIC <
   flat<0x40>, "flat_atomic_fmax", VGPR_32
 >;
 defm FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_ATOMIC <
   flat<0x5e>, "flat_atomic_fcmpswap_x2", VReg_64, VReg_128
 >;
 defm FLAT_ATOMIC_FMIN_X2 : FLAT_ATOMIC <
   flat<0x5f>, "flat_atomic_fmin_x2", VReg_64
 >;
 defm FLAT_ATOMIC_FMAX_X2 : FLAT_ATOMIC <
   flat<0x60>, "flat_atomic_fmax_x2", VReg_64
 >;
 
-} // End SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst
+} // End SubtargetPredicate = isCI, VIAssemblerPredicate = DisableInst, DisableVIDecoder = 1
 
 let Predicates = [isCI] in {
 
 // Convert (x - floor(x)) to fract(x)
 def : Pat <
   (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)),
              (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))),
   (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE)

lib/Target/AMDGPU/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
 
 tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
 tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
 tablegen(LLVM AMDGPUGenIntrinsics.inc -gen-tgt-intrinsic)
 tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)
 tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
 add_public_tablegen_target(AMDGPUCommonTableGen)
 
 add_llvm_target(AMDGPUCodeGen
   AMDILCFGStructurizer.cpp
   AMDGPUAlwaysInlinePass.cpp
   AMDGPUAnnotateKernelFeatures.cpp
   AMDGPUAnnotateUniformValues.cpp
   AMDGPUAsmPrinter.cpp
add_llvm_target(AMDGPUCodeGen
   SIMachineScheduler.cpp
   SIRegisterInfo.cpp
   SIShrinkInstructions.cpp
   SITypeRewriter.cpp
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(InstPrinter)
+add_subdirectory(Disassembler)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(Utils)

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h

+//===-- AMDGPUDisassembler.hpp - Disassembler for AMDGPU ISA ---*- C++ -*--===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+///
+/// This file contains declaration for AMDGPU ISA disassembler
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
+#define LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
+
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+
+namespace llvm {
+
+  class MCContext;
+  class MCInst;
+  class MCSubtargetInfo;
+
+  class AMDGPUDisassembler : public MCDisassembler {
+  private:
+    /// true if 32-bit literal constant is placed after instruction
+    mutable bool HasLiteral;
+    mutable ArrayRef<uint8_t> Bytes;
+
+  public:
+    AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
+      MCDisassembler(STI, Ctx), HasLiteral(false) {}
+
+    ~AMDGPUDisassembler() {}
+
+    DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
+                                ArrayRef<uint8_t> Bytes, uint64_t Address,
+                                raw_ostream &WS, raw_ostream &CS) const override;
+
+    /// Decode inline float value in SRC field
+    DecodeStatus DecodeImmedFloat(unsigned Imm, uint32_t &F) const;
+    /// Decode inline double value in SRC field
+    DecodeStatus DecodeImmedDouble(unsigned Imm, uint64_t &D) const;
+    /// Decode inline integer value in SRC field
+    DecodeStatus DecodeImmedInteger(unsigned Imm, int64_t &I) const;
+    /// Decode VGPR register
+    DecodeStatus DecodeVgprRegister(unsigned Val, unsigned &RegID, 
+                                    unsigned Size = 32) const;
+    /// Decode SGPR register
+    DecodeStatus DecodeSgprRegister(unsigned Val, unsigned &RegID, 
+                                    unsigned Size = 32) const;
+    /// Decode 32-bit register in SRC field
+    DecodeStatus DecodeSrc32Register(unsigned Val, unsigned &RegID) const;
+    /// Decode 64-bit register in SRC field
+    DecodeStatus DecodeSrc64Register(unsigned Val, unsigned &RegID) const;
+
+    /// Decode literal constant after instruction
+    DecodeStatus DecodeLiteralConstant(MCInst &Inst, uint64_t &Literal) const;
+
+    DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm, 
+                                            uint64_t Addr) const;
+    
+    DecodeStatus DecodeVSRegisterClass(MCInst &Inst, unsigned Imm, 
+                                       uint64_t Addr, bool Is32) const;
+
+    DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm, 
+                                          uint64_t Addr) const;
+
+    DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm, 
+                                          uint64_t Addr) const;
+
+    DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm, 
+                                            uint64_t Addr) const;
+  };
+} // namespace llvm
+
+#endif LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
 No newline at end of file

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

+//===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+///
+/// This file contains definition for AMDGPU ISA disassembler
+//
+//===----------------------------------------------------------------------===//
+
+// ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
+
+#include "AMDGPUDisassembler.h"
+#include "AMDGPU.h"
+#include "AMDGPURegisterInfo.h"
+#include "Utils/AMDGPUBaseInfo.h"
+
+#include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/TargetRegistry.h"
+
+
+using namespace llvm;
+
+#define DEBUG_TYPE "amdgpu-disassembler"
+
+typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
+
+
+static DecodeStatus DecodeVGPR_32RegisterClass(MCInst &Inst, unsigned Imm,
+                                               uint64_t Addr, const void *Decoder) {
+  const AMDGPUDisassembler *Dis = 
+    static_cast<const AMDGPUDisassembler *>(Decoder);
+  return Dis->DecodeVGPR_32RegisterClass(Inst, Imm, Addr);
+}
+
+static DecodeStatus DecodeVS_32RegisterClass(MCInst &Inst, unsigned Imm,
+                                             uint64_t Addr, const void *Decoder) {
+  const AMDGPUDisassembler *Dis = 
+    static_cast<const AMDGPUDisassembler *>(Decoder);
+  return Dis->DecodeVS_32RegisterClass(Inst, Imm, Addr);
+}
+
+static DecodeStatus DecodeVS_64RegisterClass(MCInst &Inst, unsigned Imm, 
+                                             uint64_t Addr, const void *Decoder) {
+  const AMDGPUDisassembler *Dis = 
+    static_cast<const AMDGPUDisassembler *>(Decoder);
+  return Dis->DecodeVS_64RegisterClass(Inst, Imm, Addr);
+}
+
+static DecodeStatus DecodeVReg_64RegisterClass(MCInst &Inst, unsigned Imm, 
+                                               uint64_t Addr, const void *Decoder) {
+  const AMDGPUDisassembler *Dis = 
+    static_cast<const AMDGPUDisassembler *>(Decoder);
+  return Dis->DecodeVReg_64RegisterClass(Inst, Imm, Addr);
+}
+
+static DecodeStatus DecodeVReg_96RegisterClass(MCInst &Inst, unsigned Imm, 
+                                               uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeVReg_128RegisterClass(MCInst &Inst, unsigned Imm, 
+                                                uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeSGPR_32RegisterClass(MCInst &Inst, unsigned Imm, 
+                                               uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeSReg_32RegisterClass(MCInst &Inst, unsigned Imm, 
+                                               uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeSReg_64RegisterClass(MCInst &Inst, unsigned Imm, 
+                                               uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeSReg_128RegisterClass(MCInst &Inst, unsigned Imm, 
+                                                uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeSReg_256RegisterClass(MCInst &Inst, unsigned Imm, 
+                                                uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+static DecodeStatus DecodeSReg_512RegisterClass(MCInst &Inst, unsigned Imm, 
+                                                uint64_t Addr, const void *Decoder) {
+  // ToDo
+  return MCDisassembler::Fail;
+}
+
+
+#define GET_SUBTARGETINFO_ENUM
+#include "AMDGPUGenSubtargetInfo.inc"
+#undef GET_SUBTARGETINFO_ENUM
+
+#include "AMDGPUGenDisassemblerTables.inc"
+
+//===----------------------------------------------------------------------===//
+//
+//===----------------------------------------------------------------------===//
+
+DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
+                                                ArrayRef<uint8_t> Bytes,
+                                                uint64_t Address, 
+                                                raw_ostream &WS,
+                                                raw_ostream &CS) const {
+  CommentStream = &CS;
+
+  // ToDo: AMDGPUDisassembler supports only VI ISA.
+  assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA.");
+
+  HasLiteral = false;
+  this->Bytes = Bytes;
+
+  // Try decode 32-bit instruction
+  if (Bytes.size() < 4) {
+    Size = 0;
+    return MCDisassembler::Fail;
+  }
+  uint32_t Insn =
+      (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
+
+  // Calling the auto-generated decoder function.
+  DecodeStatus Result =
+      decodeInstruction(DecoderTableVI32, MI, Insn, Address, this, STI);
+  if (Result != MCDisassembler::Success) {
+      Size = 0;
+      return MCDisassembler::Fail;
+  }
+  if (HasLiteral == true) {
+    Size = 8;
+    HasLiteral = false;
+  } else {
+    Size = 4;
+  }
+
+  return MCDisassembler::Success;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeImmedFloat(unsigned Imm, uint32_t &F) const {
+  // ToDo: case 248: 1/(2*PI) - is allowed only on VI
+  // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as 
+  // literal constant.
+  switch(Imm) {
+  case 240: F = FloatToBits(0.5f); return MCDisassembler::Success;
+  case 241: F = FloatToBits(-0.5f); return MCDisassembler::Success;
+  case 242: F = FloatToBits(1.0f); return MCDisassembler::Success;
+  case 243: F = FloatToBits(-1.0f); return MCDisassembler::Success;
+  case 244: F = FloatToBits(2.0f); return MCDisassembler::Success;
+  case 245: F = FloatToBits(-2.0f); return MCDisassembler::Success;
+  case 246: F = FloatToBits(4.0f); return MCDisassembler::Success;
+  case 247: F = FloatToBits(-4.0f); return MCDisassembler::Success;
+  case 248: F = 0x3e22f983; return MCDisassembler::Success; // 1/(2*PI)
+  default: return MCDisassembler::Fail;
+  }
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeImmedDouble(unsigned Imm, uint64_t &D) const {
+  switch(Imm) {
+  case 240: D = DoubleToBits(0.5); return MCDisassembler::Success;
+  case 241: D = DoubleToBits(-0.5); return MCDisassembler::Success;
+  case 242: D = DoubleToBits(1.0); return MCDisassembler::Success;
+  case 243: D = DoubleToBits(-1.0); return MCDisassembler::Success;
+  case 244: D = DoubleToBits(2.0); return MCDisassembler::Success;
+  case 245: D = DoubleToBits(-2.0); return MCDisassembler::Success;
+  case 246: D = DoubleToBits(4.0); return MCDisassembler::Success;
+  case 247: D = DoubleToBits(-4.0); return MCDisassembler::Success;
+  case 248: D = 0x3fc45f306dc9c882; return MCDisassembler::Success; // 1/(2*PI)
+  default: return MCDisassembler::Fail;
+  }
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeImmedInteger(unsigned Imm, 
+                                                    int64_t &I) const {
+  if ((Imm >= 128) && (Imm <= 192)) {
+    I = Imm - 128;
+    return MCDisassembler::Success;
+  } else if ((Imm >= 193) && (Imm <= 208)) {
+    I = 192 - Imm;
+    return MCDisassembler::Success;
+  }
+  return MCDisassembler::Fail;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeVgprRegister(unsigned Val,
+                                                    unsigned &RegID,
+                                                    unsigned Size) const {
+  if (Val > (256 - Size / 32)) {
+    return MCDisassembler::Fail;
+  }
+  unsigned RegClassID;
+  switch (Size) {
+  case 32: RegClassID = AMDGPU::VGPR_32RegClassID; break;
+  case 64: RegClassID = AMDGPU::VReg_64RegClassID; break;
+  case 96: RegClassID = AMDGPU::VReg_96RegClassID; break;
+  case 128: RegClassID = AMDGPU::VReg_128RegClassID; break;
+  case 256: RegClassID = AMDGPU::VReg_256RegClassID; break;
+  case 512: RegClassID = AMDGPU::VReg_512RegClassID; break;
+  default:
+    return MCDisassembler::Fail;
+  }
+
+  RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
+  return MCDisassembler::Success;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeSgprRegister(unsigned Val, 
+                                                    unsigned &RegID,
+                                                    unsigned Size) const {
+  // ToDo: SI/CI have 104 SGPRs, VI - 102
+  unsigned RegClassID;
+ 
+  switch (Size) {
+  case 32: 
+    if (Val > 101) {
+      return MCDisassembler::Fail;
+    }
+    RegClassID = AMDGPU::SGPR_32RegClassID;
+    break;
+  case 64:
+    if ((Val % 2 != 0) || (Val > 100)) {
+      return MCDisassembler::Fail;
+    }
+    Val /= 2;
+    RegClassID = AMDGPU::SGPR_64RegClassID;
+    break;
+  case 128:
+    // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 
+    // this bundle?
+    if ((Val % 4 != 0) || (Val > 96)) {
+      return MCDisassembler::Fail;
+    }
+    Val /= 4;
+    RegClassID = AMDGPU::SReg_128RegClassID;
+    break;
+  case 256:
+    // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 
+    // this bundle?
+    if ((Val % 4 != 0) || (Val > 92)) {
+      return MCDisassembler::Fail;
+    }
+    Val /= 4;
+    RegClassID = AMDGPU::SReg_256RegClassID;
+    break;
+  case 512:
+    // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 
+    // this bundle?
+    if ((Val % 4 != 0) || (Val > 84)) {
+      return MCDisassembler::Fail;
+    }
+    Val /= 4;
+    RegClassID = AMDGPU::SReg_512RegClassID;
+    break;
+  default:
+    return MCDisassembler::Fail;
+  }
+    
+  RegID = AMDGPUMCRegisterClasses[RegClassID].getRegister(Val);
+  return MCDisassembler::Success;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeSrc32Register(unsigned Val, 
+                                                     unsigned &RegID) const {
+  // ToDo: deal with out-of range registers  
+  using namespace AMDGPU;
+  if (Val <= 101) {
+    return DecodeSgprRegister(Val, RegID, 32);
+  } else if ((Val >= 256) && (Val <= 511)) {
+    return DecodeVgprRegister(Val - 256, RegID, 32);
+  } else {
+    switch(Val) {
+    case 102: RegID = getMCReg(FLAT_SCR_LO, STI); return MCDisassembler::Success;
+    case 103: RegID = getMCReg(FLAT_SCR_HI, STI); return MCDisassembler::Success;
+    // ToDo: no support for xnack_mask_lo/_hi register
+    case 104:
+    case 105: return MCDisassembler::Fail;
+    case 106: RegID = getMCReg(VCC_LO, STI); return MCDisassembler::Success;
+    case 107: RegID = getMCReg(VCC_HI, STI); return MCDisassembler::Success;
+    // ToDo: no support for tba_lo/_hi register
+    case 108:
+    case 109: return MCDisassembler::Fail;
+    // ToDo: no support for tma_lo/_hi register
+    case 110:
+    case 111: return MCDisassembler::Fail;
+    // ToDo: no support for ttmp[0:11] register
+    case 112:
+    case 113:
+    case 114:
+    case 115:
+    case 116:
+    case 117:
+    case 118:
+    case 119:
+    case 120:
+    case 121:
+    case 122:
+    case 123: return MCDisassembler::Fail;
+    case 124: RegID = getMCReg(M0, STI); return MCDisassembler::Success;
+    case 126: RegID = getMCReg(EXEC_LO, STI); return MCDisassembler::Success;
+    case 127: RegID = getMCReg(EXEC_HI, STI); return MCDisassembler::Success;
+    // ToDo: no support for vccz register
+    case 251: return MCDisassembler::Fail;
+    // ToDo: no support for execz register
+    case 252: return MCDisassembler::Fail;
+    case 253: RegID = getMCReg(SCC, STI); return MCDisassembler::Success;
+    default: return MCDisassembler::Fail;
+    }
+  }
+  return MCDisassembler::Fail;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeSrc64Register(unsigned Val, 
+                                                     unsigned &RegID) const {
+  // ToDo: deal with out-of range registers  
+  using namespace AMDGPU;
+  if (Val <= 101) {
+    return DecodeSgprRegister(Val, RegID, 64);
+  } else if ((Val >= 256) && (Val <= 511)) {
+    return DecodeVgprRegister(Val - 256, RegID, 64);
+  } else {
+    switch(Val) {
+    case 102: RegID = getMCReg(FLAT_SCR, STI); return MCDisassembler::Success;
+    case 106: RegID = getMCReg(VCC, STI); return MCDisassembler::Success;
+    case 126: RegID = getMCReg(EXEC, STI); return MCDisassembler::Success;
+    default: return MCDisassembler::Fail;
+    }
+  }
+  return MCDisassembler::Fail;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeLiteralConstant(MCInst &Inst, 
+                                                       uint64_t &Literal) const {
+  // For now all literal constants are supposed to be unsigned integer
+  // ToDo: deal with signed/unsigned 64-bit integer constants
+  // ToDo: deal with float/double constants
+  if (Bytes.size() < 8) {
+    return MCDisassembler::Fail;
+  }
+  Literal =
+    0 | (Bytes[7] << 24) | (Bytes[6] << 16) | (Bytes[5] << 8) | (Bytes[4] << 0);
+  return MCDisassembler::Success;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeVGPR_32RegisterClass(llvm::MCInst &Inst, 
+                                                            unsigned Imm, 
+                                                            uint64_t Addr) const {
+  unsigned RegID;
+  if (DecodeVgprRegister(Imm, RegID) == MCDisassembler::Success) {
+    Inst.addOperand(MCOperand::createReg(RegID));
+    return MCDisassembler::Success;
+  }
+  return MCDisassembler::Fail;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeVSRegisterClass(MCInst &Inst, 
+                                                       unsigned Imm,
+                                                       uint64_t Addr,
+                                                       bool Is32) const {
+  // ToDo: different opcodes allow different formats of this operands
+  if ((Imm >= 128) && (Imm <= 208)) {
+    // immediate integer
+    int64_t Val;
+    if (DecodeImmedInteger(Imm, Val) == MCDisassembler::Success) {
+      Inst.addOperand(MCOperand::createImm(Val));
+      return MCDisassembler::Success;
+    }
+  } else if ((Imm >= 240) && (Imm <= 248)) {
+    // immediate float/double
+    uint64_t Val;
+    DecodeStatus status;
+    if (Is32) {
+      uint32_t Val32;
+      status = DecodeImmedFloat(Imm, Val32);
+      Val = static_cast<uint64_t>(Val32);
+    } else {
+      status = DecodeImmedDouble(Imm, Val);
+    }
+    if (status == MCDisassembler::Success) {
+      Inst.addOperand(MCOperand::createImm(Val));
+      return MCDisassembler::Success;
+    }
+  } else if (Imm == 254) {
+    // LDS direct
+    // ToDo: implement LDS direct read
+  } else if (Imm == 255) {
+    // literal constant
+    HasLiteral = true;
+    uint64_t Literal;
+    if (DecodeLiteralConstant(Inst, Literal) == MCDisassembler::Success) {
+      Inst.addOperand(MCOperand::createImm(Literal));
+      return MCDisassembler::Success;
+    }
+    return MCDisassembler::Fail;
+  } else if ((Imm == 125) || 
+             ((Imm >= 209) && (Imm <= 239)) || 
+             (Imm == 249) || 
+             (Imm == 250) || 
+             (Imm >= 512)) {
+    // reserved
+    return MCDisassembler::Fail;
+  } else {
+    // register
+    unsigned RegID;
+    DecodeStatus status = Is32 ? DecodeSrc32Register(Imm, RegID) 
+                               : DecodeSrc64Register(Imm, RegID);
+    if (status == MCDisassembler::Success) {
+      Inst.addOperand(MCOperand::createReg(RegID));
+      return MCDisassembler::Success;
+    }
+  }
+  return MCDisassembler::Fail;
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeVS_32RegisterClass(MCInst &Inst, 
+                                                          unsigned Imm, 
+                                                          uint64_t Addr) const {
+  return DecodeVSRegisterClass(Inst, Imm, Addr, true);
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeVS_64RegisterClass(MCInst &Inst, 
+                                                          unsigned Imm, 
+                                                          uint64_t Addr) const {
+  return DecodeVSRegisterClass(Inst, Imm, Addr, false);
+}
+
+DecodeStatus AMDGPUDisassembler::DecodeVReg_64RegisterClass(llvm::MCInst &Inst, 
+                                                            unsigned Imm, 
+                                                            uint64_t Addr) const {
+  unsigned RegID;
+  if (DecodeVgprRegister(Imm, RegID, 64) == MCDisassembler::Success) {
+    Inst.addOperand(MCOperand::createReg(RegID));
+    return MCDisassembler::Success;
+  }
+  return MCDisassembler::Fail;
+}
+
+
+
+static MCDisassembler *createAMDGPUDisassembler(const Target &T,
+                                                const MCSubtargetInfo &STI,
+                                                MCContext &Ctx) {
+  return new AMDGPUDisassembler(STI, Ctx);
+}
+
+extern "C" void LLVMInitializeAMDGPUDisassembler() {
+  TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler);
+}

lib/Target/AMDGPU/Disassembler/CMakeLists.txt

+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_library(LLVMAMDGPUDisassembler
+  AMDGPUDisassembler.cpp
+  )
+
+add_dependencies(LLVMAMDGPUDisassembler AMDGPUCommonTableGen)

lib/Target/AMDGPU/Disassembler/LLVMBuild.txt

+;===- ./lib/Target/AMDGPU/Disassembler/LLVMBuild.txt ------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = AMDGPUDisassembler
+parent = AMDGPU
+required_libraries = AMDGPUDesc AMDGPUInfo AMDGPUUtils MC MCDisassembler Support
+add_to_library_groups = AMDGPU

lib/Target/AMDGPU/LLVMBuild.txt

 ;
 ; For more information on the LLVMBuild system, please see:
 ;
 ;   http://llvm.org/docs/LLVMBuild.html
 ;
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo Utils
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo Utils
 
 [component_0]
 type = TargetGroup
 name = AMDGPU
 parent = Target
 has_asmparser = 1
 has_asmprinter = 1
+has_disassembler = 1
 
 [component_1]
 type = Library
 name = AMDGPUCodeGen
 parent = AMDGPU
 required_libraries = Analysis AsmPrinter CodeGen Core IPO MC AMDGPUAsmParser AMDGPUAsmPrinter AMDGPUDesc AMDGPUInfo AMDGPUUtils Scalar SelectionDAG Support Target TransformUtils
 add_to_library_groups = AMDGPU

lib/Target/AMDGPU/SIInstrFormats.td

class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
   let TSFlags{17} = DS;
   let TSFlags{18} = MIMG;
   let TSFlags{19} = FLAT;
   let TSFlags{20} = WQM;
   let TSFlags{21} = VGPRSpill;
   let TSFlags{22} = VOPAsmPrefer32Bit;
 
   let SchedRW = [Write32Bit];
+
+  field bits<1> DisableSIDecoder = 0;
+  field bits<1> DisableVIDecoder = 0;
+  field bits<1> DisableDecoder = 0;
+
+  let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
 }
 
 class Enc32 {
   field bits<32> Inst;
   int Size = 4;
 }
 
 class Enc64 {
class VOP2_MADKe <bits<6> op> : Enc64 {
   let Inst{8-0} = src0;
   let Inst{16-9} = vsrc1;
   let Inst{24-17} = vdst;
   let Inst{30-25} = op;
   let Inst{31} = 0x0; // encoding
   let Inst{63-32} = src2;
 }
 
-class VOP3e <bits<9> op> : Enc64 {
-  bits<8> vdst;
+class VOP3a <bits<9> op> : Enc64 {
   bits<2> src0_modifiers;
   bits<9> src0;
   bits<2> src1_modifiers;
   bits<9> src1;
   bits<2> src2_modifiers;
   bits<9> src2;
   bits<1> clamp;
   bits<2> omod;
 
-  let Inst{7-0} = vdst;
   let Inst{8} = src0_modifiers{1};
   let Inst{9} = src1_modifiers{1};
   let Inst{10} = src2_modifiers{1};
   let Inst{11} = clamp;
   let Inst{25-17} = op;
   let Inst{31-26} = 0x34; //encoding
   let Inst{40-32} = src0;
   let Inst{49-41} = src1;
   let Inst{58-50} = src2;
   let Inst{60-59} = omod;
   let Inst{61} = src0_modifiers{0};
   let Inst{62} = src1_modifiers{0};
   let Inst{63} = src2_modifiers{0};
 }
 
+class VOP3e <bits<9> op> : VOP3a <op> {
+  bits<8> vdst;
+
+  let Inst{7-0} = vdst;
+}
+
+// Encoding used for VOPC instructions encoded as VOP3
+// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
+class VOP3ce <bits<9> op> : VOP3a <op> {
+  bits<8> sdst;
+
+  let Inst{7-0} = sdst;
+}
+
 class VOP3be <bits<9> op> : Enc64 {
   bits<8> vdst;
   bits<2> src0_modifiers;
   bits<9> src0;
   bits<2> src1_modifiers;
   bits<9> src1;
   bits<2> src2_modifiers;
   bits<9> src2;

lib/Target/AMDGPU/SIInstrInfo.cpp

switch (MI->getOpcode()) {
     case AMDGPU::V_MAC_F32_e32: {
       const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
       if (Src0->isImm() && !isInlineConstant(*Src0, 4))
         return nullptr;
       break;
     }
   }
 
-  const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::dst);
+  const MachineOperand *Dst = getNamedOperand(*MI, AMDGPU::OpName::vdst);
   const MachineOperand *Src0 = getNamedOperand(*MI, AMDGPU::OpName::src0);
   const MachineOperand *Src1 = getNamedOperand(*MI, AMDGPU::OpName::src1);
   const MachineOperand *Src2 = getNamedOperand(*MI, AMDGPU::OpName::src2);
 
   return BuildMI(*MBB, MI, MI->getDebugLoc(), get(AMDGPU::V_MAD_F32))
                  .addOperand(*Dst)
                  .addImm(0) // Src0 mods
                  .addOperand(*Src0)

lib/Target/AMDGPU/SIInstrInfo.td

 }
 
 multiclass EXP_m {
 
   let isPseudo = 1, isCodeGenOnly = 1 in {
     def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ;
   }
 
-  def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe;
+  def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe {
+    let DecoderNamespace="SICI";
+    let DisableDecoder = DisableSIDecoder;
+  }
 
-  def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi;
+  def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi {
+    let DecoderNamespace="VI";
+    let DisableDecoder = DisableVIDecoder;
+  }
 }
 
 //===----------------------------------------------------------------------===//
 // Scalar classes
 //===----------------------------------------------------------------------===//
 
 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   SOP1 <outs, ins, "", pattern>,
   SIMCInstr<opName, SISubtarget.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
   SOP1 <outs, ins, asm, []>,
   SOP1e <op.SI>,
   SIMCInstr<opName, SISubtarget.SI> {
   let isCodeGenOnly = 0;
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
   SOP1 <outs, ins, asm, []>,
   SOP1e <op.VI>,
   SIMCInstr<opName, SISubtarget.VI> {
   let isCodeGenOnly = 0;
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
                    list<dag> pattern> {
 
   def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
 
   def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
   field bits<7> sdst = 0;
 }
 
 class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :
   SOP2<outs, ins, asm, []>,
   SOP2e<op.SI>,
   SIMCInstr<opName, SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> :
   SOP2<outs, ins, asm, []>,
   SOP2e<op.VI>,
   SIMCInstr<opName, SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
                    list<dag> pattern> {
 
   def "" : SOP2_Pseudo <opName, outs, ins, pattern>;
 
   def _si : SOP2_Real_si <op, opName, outs, ins, asm>;
class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   let isCodeGenOnly = 1;
 }
 
 class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> :
   SOPK <outs, ins, asm, []>,
   SOPKe <op.SI>,
   SIMCInstr<opName, SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
   let isCodeGenOnly = 0;
 }
 
 class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> :
   SOPK <outs, ins, asm, []>,
   SOPKe <op.VI>,
   SIMCInstr<opName, SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
   let isCodeGenOnly = 0;
 }
 
 multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
                    string asm = opName#opAsm> {
   def "" : SOPK_Pseudo <opName, outs, ins, []>;
 
   def _si : SOPK_Real_si <op, opName, outs, ins, asm>;
multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins,
                        string argAsm, string asm = opName#argAsm> {
 
   def "" : SOPK_Pseudo <opName, outs, ins, []>;
 
   def _si : SOPK <outs, ins, asm, []>,
             SOPK64e <op.SI>,
             SIMCInstr<opName, SISubtarget.SI> {
               let AssemblerPredicates = [isSICI];
+              let DecoderNamespace = "SICI";
+              let DisableDecoder = DisableSIDecoder;
               let isCodeGenOnly = 0;
             }
 
   def _vi : SOPK <outs, ins, asm, []>,
             SOPK64e <op.VI>,
             SIMCInstr<opName, SISubtarget.VI> {
               let AssemblerPredicates = [isVI];
+              let DecoderNamespace = "VI";
+              let DisableDecoder = DisableVIDecoder;
               let isCodeGenOnly = 0;
             }
 }
 //===----------------------------------------------------------------------===//
 // SMRD classes
 //===----------------------------------------------------------------------===//
 
 class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   SMRD <outs, ins, "", pattern>,
   SIMCInstr<opName, SISubtarget.NONE> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins,
                     string asm> :
   SMRD <outs, ins, asm, []>,
   SMRDe <op, imm>,
   SIMCInstr<opName, SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
                     string asm, list<dag> pattern = []> :
   SMRD <outs, ins, asm, pattern>,
   SMEMe_vi <op, imm>,
   SIMCInstr<opName, SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
                    string asm, list<dag> pattern> {
 
   def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
 
   def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
defm _IMM : SMRD_m <
     (ins baseClass:$sbase, smrd_offset:$offset),
     opName#" $dst, $sbase, $offset", []
   >;
 
   def _IMM_ci : SMRD <
     (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
     opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
     let AssemblerPredicates = [isCIOnly];
+    let DecoderNamespace = "CI";
   }
 
   defm _SGPR : SMRD_m <
     op, opName#"_SGPR", 0, (outs dstClass:$dst),
     (ins baseClass:$sbase, SReg_32:$soff),
     opName#" $dst, $sbase, $soff", []
   >;
 }

 }
 
 // Returns the input arguments for VOP3 instructions for the given SrcVT.
 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
                 RegisterOperand Src2RC, int NumSrcArgs,
                 bit HasModifiers> {
 
   dag ret =
+    !if (!eq(NumSrcArgs, 0),
+      // VOP1 without input operands (V_NOP, V_CLREXCP)
+      (ins),
+      /* else */
     !if (!eq(NumSrcArgs, 1),
       !if (!eq(HasModifiers, 1),
         // VOP1 with modifiers
         (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
              ClampMod:$clamp, omod:$omod)
       /* else */,
         // VOP1 without modifiers
         (ins Src0RC:$src0)
/* NumSrcArgs == 3 */,
         // VOP3 with modifiers
         (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
              InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
              InputModsNoDefault:$src2_modifiers, Src2RC:$src2,
              ClampMod:$clamp, omod:$omod)
       /* else */,
         // VOP3 without modifiers
         (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
-      /* endif */ )));
+      /* endif */ ))));
 }
 
 // Returns the assembly string for the inputs and outputs of a VOP[12C]
 // instruction.  This does not add the _e32 suffix, so it can be reused
 // by getAsm64.
-class getAsm32 <bit HasDst, int NumSrcArgs> {
-  string dst = "$dst";
+class getAsm32 <bit HasDst, ValueType DstVT, int NumSrcArgs> {
+  string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
   string src0 = ", $src0";
   string src1 = ", $src1";
   string src2 = ", $src2";
   string ret = !if(HasDst, dst, "") #
                !if(!eq(NumSrcArgs, 1), src0, "") #
                !if(!eq(NumSrcArgs, 2), src0#src1, "") #
                !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
 }
 
 // Returns the assembly string for the inputs and outputs of a VOP3
 // instruction.
-class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> {
+class getAsm64 <bit HasDst, ValueType DstVT, int NumSrcArgs, bit HasModifiers> {
+  string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
   string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
   string src1 = !if(!eq(NumSrcArgs, 1), "",
                    !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
                                            " $src1_modifiers,"));
   string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
   string ret =
   !if(!eq(HasModifiers, 0),
-      getAsm32<HasDst, NumSrcArgs>.ret,
-      "$dst, "#src0#src1#src2#"$clamp"#"$omod");
+      getAsm32<HasDst, DstVT, NumSrcArgs>.ret,
+      dst#", "#src0#src1#src2#"$clamp"#"$omod");
 }
 
 class VOPProfile <list<ValueType> _ArgVT> {
 
   field list<ValueType> ArgVT = _ArgVT;
 
   field ValueType DstVT = ArgVT[0];
   field ValueType Src0VT = ArgVT[1];
   field ValueType Src1VT = ArgVT[2];
   field ValueType Src2VT = ArgVT[3];
   field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
   field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
   field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
   field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
   field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
   field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
 
   field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
   field bit HasDst32 = HasDst;
   field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
   field bit HasModifiers = hasModifiers<Src0VT>.ret;
 
-  field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs));
+  field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
 
   // VOP3b instructions are a special case with a second explicit
   // output. This is manually overridden for them.
   field dag Outs32 = Outs;
   field dag Outs64 = Outs;
 
   field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
   field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
                              HasModifiers>.ret;
 
-  field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret;
-  field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret;
+  field string Asm32 = getAsm32<HasDst, DstVT, NumSrcArgs>.ret;
+  field string Asm64 = getAsm64<HasDst, DstVT, NumSrcArgs, HasModifiers>.ret;
 }
 
 // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
 //        for the instruction patterns to work.
 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
 def VOP_F16_I16 : VOPProfile <[f16, i32, untyped, untyped]>;
 def VOP_I16_F16 : VOPProfile <[i32, f16, untyped, untyped]>;
 

 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
 
 // Write out to vcc or arbitrary SGPR.
 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
-  let Asm32 = "$dst, vcc, $src0, $src1";
-  let Asm64 = "$dst, $sdst, $src0, $src1";
-  let Outs32 = (outs DstRC:$dst);
-  let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
+  let Asm32 = "$vdst, vcc, $src0, $src1";
+  let Asm64 = "$vdst, $sdst, $src0, $src1";
+  let Outs32 = (outs DstRC:$vdst);
+  let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
 }
 
 // Write out to vcc or arbitrary SGPR and read in from vcc or
 // arbitrary SGPR.
 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
   // We use VCSrc_32 to exclude literal constants, even though the
   // encoding normally allows them since the implicit VCC use means
   // using one would always violate the constant bus
   // restriction. SGPRs are still allowed because it should
   // technically be possible to use VCC again as src0.
   let Src0RC32 = VCSrc_32;
-  let Asm32 = "$dst, vcc, $src0, $src1, vcc";
-  let Asm64 = "$dst, $sdst, $src0, $src1, $src2";
-  let Outs32 = (outs DstRC:$dst);
-  let Outs64 = (outs DstRC:$dst, SReg_64:$sdst);
+  let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
+  let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
+  let Outs32 = (outs DstRC:$vdst);
+  let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
 
   // Suppress src2 implied by type since the 32-bit encoding uses an
   // implicit VCC use.
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
 }
 
 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
   let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);

 
 // VOPC instructions are a special case because for the 32-bit
 // encoding, we want to display the implicit vcc write as if it were
 // an explicit $dst.
 class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, vt1, untyped]> {
   let Asm32 = "vcc, $src0, $src1";
   // The destination for 32-bit encoding is implicit.
   let HasDst32 = 0;
+  let Outs64 =  (outs DstRC:$sdst);
 }
 
 class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> {
   let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1);
-  let Asm64 = "$dst, $src0_modifiers, $src1";
+  let Asm64 = "$sdst, $src0_modifiers, $src1";
 }
 
 def VOPC_I1_F32_F32 : VOPC_Profile<f32>;
 def VOPC_I1_F64_F64 : VOPC_Profile<f64>;
 def VOPC_I1_I32_I32 : VOPC_Profile<i32>;
 def VOPC_I1_I64_I64 : VOPC_Profile<i64>;
 
 def VOPC_I1_F32_I32 : VOPC_Class_Profile<f32>;
 def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>;
 
 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
 def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> {
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
   let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2);
-  let Asm64 = "$dst, $src0, $src1, $src2";
+  let Asm64 = "$vdst, $src0, $src1, $src2";
 }
 
 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
 def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> {
   field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2);
-  field string Asm = "$dst, $src0, $vsrc1, $src2";
+  field string Asm = "$vdst, $src0, $vsrc1, $src2";
 }
 def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
   let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
   let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
                              HasModifiers>.ret;
-  let Asm32 = getAsm32<1, 2>.ret;
-  let Asm64 = getAsm64<1, 2, HasModifiers>.ret;
+  let Asm32 = getAsm32<1, f32, 2>.ret;
+  let Asm64 = getAsm64<1, f32, 2, HasModifiers>.ret;
 }
 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
 
+// This class is used only with VOPC instructions. Use $sdst for out operand
 class SIInstAlias <string asm, Instruction inst, VOPProfile p> :
     InstAlias <asm, (inst)>, PredicateControl {
 
   field bit isCompare;
   field bit isCommutable;
 
   let ResultInst =
     !if (p.HasDst32,
       !if (!eq(p.NumSrcArgs, 0),
         // 1 dst, 0 src
-        (inst p.DstRC:$dst),
+        (inst p.DstRC:$sdst),
       !if (!eq(p.NumSrcArgs, 1),
         // 1 dst, 1 src
-        (inst p.DstRC:$dst, p.Src0RC32:$src0),
+        (inst p.DstRC:$sdst, p.Src0RC32:$src0),
       !if (!eq(p.NumSrcArgs, 2),
         // 1 dst, 2 src
-        (inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1),
+        (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1),
       // else - unreachable
         (inst)))),
     // else
       !if (!eq(p.NumSrcArgs, 2),
         // 0 dst, 2 src
         (inst p.Src0RC32:$src0, p.Src1RC32:$src1),
       !if (!eq(p.NumSrcArgs, 1),
         // 0 dst, 1 src
class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
   field bits<8> vdst;
   field bits<9> src0;
 }
 
 class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> :
   VOP1<op.SI, outs, ins, asm, []>,
   SIMCInstr <opName#"_e32", SISubtarget.SI> {
   let AssemblerPredicate = SIAssemblerPredicate;
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> :
   VOP1<op.VI, outs, ins, asm, []>,
   SIMCInstr <opName#"_e32", SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
                    string asm = opName#p.Asm32> {
   def "" : VOP1_Pseudo <p.Outs, p.Ins32, pattern, opName>;
 
   def _si : VOP1_Real_si <opName, op, p.Outs, p.Ins32, asm>;
 
class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> :
   VOP2 <op.SI, outs, ins, opName#asm, []>,
   SIMCInstr <opName#"_e32", SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> :
   VOP2 <op.VI, outs, ins, opName#asm, []>,
   SIMCInstr <opName#"_e32", SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag> pattern,
                      string revOp> {
 
   def "" : VOP2_Pseudo <p.Outs32, p.Ins32, pattern, opName>,
            VOP2_REV<revOp#"_e32", !eq(revOp, opName)>;
 

 }
 
 class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
                     bit HasMods = 0, bit VOP3Only = 0> :
   VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
   VOP3e <op>,
   SIMCInstr<opName#"_e64", SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
                     bit HasMods = 0, bit VOP3Only = 0> :
   VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
   VOP3e_vi <op>,
   SIMCInstr <opName#"_e64", SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
+}
+
+class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
+                     bit HasMods = 0, bit VOP3Only = 0> :
+  VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
+  VOP3ce <op>,
+  SIMCInstr<opName#"_e64", SISubtarget.SI> {
+  let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
+}
+
+class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
+                      bit HasMods = 0, bit VOP3Only = 0> :
+  VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
+  VOP3ce_vi <op>,
+  SIMCInstr <opName#"_e64", SISubtarget.VI> {
+  let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName,
                      bit HasMods = 0, bit VOP3Only = 0> :
   VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
   VOP3be <op>,
   SIMCInstr<opName#"_e64", SISubtarget.SI> {
   let AssemblerPredicates = [isSICI];
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName,
                      bit HasMods = 0, bit VOP3Only = 0> :
   VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>,
   VOP3be_vi <op>,
   SIMCInstr <opName#"_e64", SISubtarget.VI> {
   let AssemblerPredicates = [isVI];
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
                    string opName, int NumSrcArgs, bit HasMods = 1, bit VOP3Only = 0> {
 
   def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
 
   def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods, VOP3Only>,
multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm,
                      string revOp, list<SchedReadWrite> sched> {
 
   def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>,
            VOP2_REV<revOp#"_e64", !eq(revOp, opName)> {
     let Defs = !if(defExec, [EXEC], []);
     let SchedRW = sched;
   }
 
-  def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
+  def _si : VOP3_C_Real_si <op.SI3, outs, ins, asm, opName, HasMods>,
             VOP3DisableFields<1, 0, HasMods> {
     let Defs = !if(defExec, [EXEC], []);
     let SchedRW = sched;
   }
 
-  def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
+  def _vi : VOP3_C_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>,
             VOP3DisableFields<1, 0, HasMods> {
     let Defs = !if(defExec, [EXEC], []);
     let SchedRW = sched;
   }
 }
 
 // An instruction that is VOP2 on SI and VOP3 on VI, no modifiers.
 multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins,
                          string asm, list<dag> pattern = []> {
   let isPseudo = 1, isCodeGenOnly = 1 in {
     def "" : VOPAnyCommon <outs, ins, "", pattern>,
              SIMCInstr<opName, SISubtarget.NONE>;
   }
 
   def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>,
             SIMCInstr <opName, SISubtarget.SI> {
             let AssemblerPredicates = [isSICI];
+            let DecoderNamespace = "SICI";
+            let DisableDecoder = DisableSIDecoder;
   }
 
   def _vi : VOP3Common <outs, ins, asm, []>,
             VOP3e_vi <op.VI3>,
             VOP3DisableFields <1, 0, 0>,
             SIMCInstr <opName, SISubtarget.VI> {
             let AssemblerPredicates = [isVI];
+            let DecoderNamespace = "VI";
+            let DisableDecoder = DisableVIDecoder;
   }
 }
 
 multiclass VOP1_Helper <vop1 op, string opName, VOPProfile p, list<dag> pat32,
                         list<dag> pat64> {
 
   defm _e32 : VOP1_m <op, opName, p, pat32>;
 
   defm _e64 : VOP3_1_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
                         p.HasModifiers>;
 }
 
 multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
                      SDPatternOperator node = null_frag> : VOP1_Helper <
   op, opName, P, [],
   !if(P.HasModifiers,
-      [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
+      [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
                                 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
-      [(set P.DstVT:$dst, (node P.Src0VT:$src0))])
+      [(set P.DstVT:$vdst, (node P.Src0VT:$src0))])
 >;
 
 multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P,
                        SDPatternOperator node = null_frag> {
 
   defm _e32 : VOP1SI_m <op, opName, P, []>;
 
   defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64,
     !if(P.HasModifiers,
-      [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
+      [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
                                 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
-      [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
+      [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]),
     opName, P.HasModifiers>;
 }
 
 multiclass VOP2_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32,
                         list<dag> pat64, string revOp> {
 
   defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
 
   defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
                         revOp, p.HasModifiers>;
 }
 
 multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
                      SDPatternOperator node = null_frag,
                      string revOp = opName> : VOP2_Helper <
   op, opName, P, [],
   !if(P.HasModifiers,
-      [(set P.DstVT:$dst,
+      [(set P.DstVT:$vdst,
            (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                       i1:$clamp, i32:$omod)),
                  (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
-      [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
+      [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
   revOp
 >;
 
 multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P,
                        SDPatternOperator node = null_frag,
                        string revOp = opName> {
 
   defm _e32 : VOP2SI_m <op, opName, P, [], revOp>;
 
   defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64,
     !if(P.HasModifiers,
-        [(set P.DstVT:$dst,
+        [(set P.DstVT:$vdst,
              (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                         i1:$clamp, i32:$omod)),
                    (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
-        [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
+        [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
     opName, revOp, P.HasModifiers>;
 }
 
 multiclass VOP2b_Helper <vop2 op, string opName, VOPProfile p,
                          list<dag> pat32, list<dag> pat64,
                          string revOp, bit useSGPRInput> {
 
   let SchedRW = [Write32Bit, WriteSALU] in {
     let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
       defm _e32 : VOP2_m <op, opName, p, pat32, revOp>;
     }
 
     defm _e64 : VOP3b_2_3_m <op, p.Outs64, p.Ins64, opName#p.Asm64, pat64,
                              opName, revOp, p.HasModifiers, useSGPRInput>;
   }
 }
 
 multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
                       SDPatternOperator node = null_frag,
                       string revOp = opName> : VOP2b_Helper <
   op, opName, P, [],
   !if(P.HasModifiers,
-      [(set P.DstVT:$dst,
+      [(set P.DstVT:$vdst,
            (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                       i1:$clamp, i32:$omod)),
                  (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
-      [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
+      [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
   revOp, !eq(P.NumSrcArgs, 3)
 >;
 
 // A VOP2 instruction that is VOP3-only on VI.
 multiclass VOP2_VI3_Helper <vop23 op, string opName, VOPProfile p,
                             list<dag> pat32, list<dag> pat64, string revOp> {
 
   defm _e32 : VOP2SI_m <op, opName, p, pat32, revOp>;
 
   defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName,
                         revOp, p.HasModifiers>;
 }
 
 multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
                           SDPatternOperator node = null_frag,
                           string revOp = opName>
                           : VOP2_VI3_Helper <
   op, opName, P, [],
   !if(P.HasModifiers,
-      [(set P.DstVT:$dst,
+      [(set P.DstVT:$vdst,
            (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                       i1:$clamp, i32:$omod)),
                  (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
-      [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
+      [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
   revOp
 >;
 
 multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> {
 
   def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>;
 
 let isCodeGenOnly = 0 in {
   def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
                         !strconcat(opName, VOP_MADK.Asm), []>,
             SIMCInstr <opName#"_e32", SISubtarget.SI>,
             VOP2_MADKe <op.SI> {
             let AssemblerPredicates = [isSICI];
+            let DecoderNamespace = "SICI";
+            let DisableDecoder = DisableSIDecoder;
             }
 
   def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins,
                         !strconcat(opName, VOP_MADK.Asm), []>,
             SIMCInstr <opName#"_e32", SISubtarget.VI>,
             VOP2_MADKe <op.VI> {
             let AssemblerPredicates = [isVI];
+            let DecoderNamespace = "VI";
+            let DisableDecoder = DisableVIDecoder;
             }
 } // End isCodeGenOnly = 0
 }
 
 class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> :
   VOPCCommon <ins, "", pattern>,
   VOP <opName>,
   SIMCInstr<opName#"_e32", SISubtarget.NONE> {
multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern,
   }
 
   let AssemblerPredicates = [isSICI] in {
     def _si : VOPC<op.SI, ins, asm, []>,
               SIMCInstr <opName#"_e32", SISubtarget.SI> {
       let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
       let hasSideEffects = DefExec;
       let SchedRW = sched;
+      let DecoderNamespace = "SICI";
+      let DisableDecoder = DisableSIDecoder;
     }
 
   } // End AssemblerPredicates = [isSICI]
 
   let AssemblerPredicates = [isVI] in {
     def _vi : VOPC<op.VI, ins, asm, []>,
               SIMCInstr <opName#"_e32", SISubtarget.VI> {
       let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
       let hasSideEffects = DefExec;
       let SchedRW = sched;
+      let DecoderNamespace = "VI";
+      let DisableDecoder = DisableVIDecoder;
     }
 
   } // End AssemblerPredicates = [isVI]
 
   defm : SIInstAliasBuilder<alias_asm, p>;
 }
 
 multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32,
                         list<dag> pat64, bit DefExec, string revOp,
                         VOPProfile p, list<SchedReadWrite> sched> {
   defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched,
                       revOp>;
 
-  defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
+  defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
                         opName, p.HasModifiers, DefExec, revOp, sched>;
 }
 
 // Special case for class instructions which only have modifiers on
 // the 1st source operand.
 multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32,
                               list<dag> pat64, bit DefExec, string revOp,
                               VOPProfile p, list<SchedReadWrite> sched> {
   defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>;
 
-  defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64,
+  defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64,
                         opName, p.HasModifiers, DefExec, revOp, sched>,
                         VOP3DisableModFields<1, 0, 0>;
 }
 
 multiclass VOPCInst <vopc op, string opName,
                      VOPProfile P, PatLeaf cond = COND_NULL,
                      string revOp = opName,
                      bit DefExec = 0,
                      list<SchedReadWrite> sched = [Write32Bit]> :
                      VOPC_Helper <
   op, opName, [],
   !if(P.HasModifiers,
-      [(set i1:$dst,
+      [(set i1:$sdst,
           (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                       i1:$clamp, i32:$omod)),
                  (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
                  cond))],
-      [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
+      [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]),
   DefExec, revOp, P, sched
 >;
 
 multiclass VOPCClassInst <vopc op, string opName, VOPProfile P,
                      bit DefExec = 0,
                      list<SchedReadWrite> sched> : VOPC_Class_Helper <
   op, opName, [],
   !if(P.HasModifiers,
-      [(set i1:$dst,
+      [(set i1:$sdst,
           (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))],
-      [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
+      [(set i1:$sdst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]),
   DefExec, opName, P, sched
 >;
 
 
 multiclass VOPC_F32 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
   VOPCInst <op, opName, VOPC_I1_F32_F32, cond, revOp>;
 
 multiclass VOPC_F64 <vopc op, string opName, PatLeaf cond = COND_NULL, string revOp = opName> :
multiclass VOPC_CLASS_F64 <vopc op, string opName> :
   VOPCClassInst <op, opName, VOPC_I1_F64_I32, 0, [WriteDoubleAdd]>;
 
 multiclass VOPCX_CLASS_F64 <vopc op, string opName> :
   VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>;
 
 multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
                      SDPatternOperator node = null_frag, bit VOP3Only = 0> :
   VOP3_Helper <
-  op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64,
+  op, opName, (outs P.DstRC.RegClass:$vdst), P.Ins64, P.Asm64,
   !if(!eq(P.NumSrcArgs, 3),
     !if(P.HasModifiers,
-        [(set P.DstVT:$dst,
+        [(set P.DstVT:$vdst,
             (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                        i1:$clamp, i32:$omod)),
                   (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
                   (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
-        [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
+        [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1,
                                   P.Src2VT:$src2))]),
   !if(!eq(P.NumSrcArgs, 2),
     !if(P.HasModifiers,
-        [(set P.DstVT:$dst,
+        [(set P.DstVT:$vdst,
             (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                        i1:$clamp, i32:$omod)),
                   (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
-        [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
+        [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
   /* P.NumSrcArgs == 1 */,
     !if(P.HasModifiers,
-        [(set P.DstVT:$dst,
+        [(set P.DstVT:$vdst,
             (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                        i1:$clamp, i32:$omod))))],
-        [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
+        [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]))),
   P.NumSrcArgs, P.HasModifiers, VOP3Only
 >;
 
 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
 // only VOP instruction that implicitly reads VCC.
 multiclass VOP3_VCC_Inst <vop3 op, string opName,
                           VOPProfile P,
                           SDPatternOperator node = null_frag> : VOP3_Helper <
   op, opName,
-  (outs P.DstRC.RegClass:$dst),
+  (outs P.DstRC.RegClass:$vdst),
   (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0,
        InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1,
        InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2,
        ClampMod:$clamp,
        omod:$omod),
-  "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
-  [(set P.DstVT:$dst,
+  "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod",
+  [(set P.DstVT:$vdst,
             (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
                                        i1:$clamp, i32:$omod)),
                   (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
                   (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
                   (i1 VCC)))],
   3, 1
 >;
 
class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
                       string asm> :
   VINTRPCommon <outs, ins, asm, []>,
   VINTRPe <op>,
-  SIMCInstr<opName, SISubtarget.SI>;
+  SIMCInstr<opName, SISubtarget.SI> {
+  let DecoderNamespace = "SICI";
+  let DisableDecoder = DisableSIDecoder;
+}
 
 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
                       string asm> :
   VINTRPCommon <outs, ins, asm, []>,
   VINTRPe_vi <op>,
-  SIMCInstr<opName, SISubtarget.VI>;
+  SIMCInstr<opName, SISubtarget.VI> {
+  let DecoderNamespace = "VI";
+  let DisableDecoder = DisableVIDecoder;
+}
 
 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
                      list<dag> pattern = []> {
   def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
 
   def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
 
   def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   let isCodeGenOnly = 1;
 }
 
 class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
   DS <outs, ins, asm, []>,
   DSe <op>,
   SIMCInstr <opName, SISubtarget.SI> {
   let isCodeGenOnly = 0;
+  let DecoderNamespace="SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> :
   DS <outs, ins, asm, []>,
   DSe_vi <op>,
-  SIMCInstr <opName, SISubtarget.VI>;
+  SIMCInstr <opName, SISubtarget.VI> {
+  let DecoderNamespace="VI";
+  let DisableDecoder = DisableVIDecoder;
+}
 
 class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> :
   DS_Real_si <op,opName, outs, ins, asm> {
 
   // Single load interpret the 2 i8imm operands as a single i16 offset.
   bits<16> offset;
   let offset0 = offset{7-0};
   let offset1 = offset{15-8};
class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins,
                     string asm> :
   MTBUF <outs, ins, asm, []>,
   MTBUFe <op>,
-  SIMCInstr<opName, SISubtarget.SI>;
+  SIMCInstr<opName, SISubtarget.SI> {
+  let DecoderNamespace="SICI";
+  let DisableDecoder = DisableSIDecoder;
+}
 
 class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> :
   MTBUF <outs, ins, asm, []>,
   MTBUFe_vi <op>,
-  SIMCInstr <opName, SISubtarget.VI>;
+  SIMCInstr <opName, SISubtarget.VI> {
+  let DecoderNamespace="VI";
+  let DisableDecoder = DisableVIDecoder;
+}
 
 multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm,
                     list<dag> pattern> {
 
   def "" : MTBUF_Pseudo <opName, outs, ins, pattern>;
 
   def _si : MTBUF_Real_si <op, opName, outs, ins, asm>;
 

 }
 
 class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins,
                      string asm> :
   MUBUF <outs, ins, asm, []>,
   MUBUFe <op.SI>,
   SIMCInstr<opName, SISubtarget.SI> {
   let lds = 0;
+  let DecoderNamespace="SICI";
+  let DisableDecoder = DisableSIDecoder;
 }
 
 class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins,
                      string asm> :
   MUBUF <outs, ins, asm, []>,
   MUBUFe_vi <op.VI>,
   SIMCInstr<opName, SISubtarget.VI> {
   let lds = 0;
+  let DecoderNamespace="VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm,
                     list<dag> pattern> {
 
   def "" : MUBUF_Pseudo <opName, outs, ins, pattern>,
            MUBUFAddr64Table <0>;
 
class FLAT_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
 class FLAT_Real_ci <bits<7> op, string opName, dag outs, dag ins, string asm> :
     FLAT <op, outs, ins, asm, []>,
     SIMCInstr<opName, SISubtarget.SI> {
   let AssemblerPredicate = isCIOnly;
+  let DecoderNamespace="CI";
 }
 
 class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string asm> :
     FLAT <op, outs, ins, asm, []>,
     SIMCInstr<opName, SISubtarget.VI> {
   let AssemblerPredicate = VIAssemblerPredicate;
+  let DecoderNamespace="VI";
+  let DisableDecoder = DisableVIDecoder;
 }
 
 multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm,
                    list<dag> pattern> {
   def "" : FLAT_Pseudo <NAME#"_RTN", outs, ins, pattern>,
                AtomicNoRet <NAME, 1>;
 
   def _ci : FLAT_Real_ci <op.CI, NAME#"_RTN", outs, ins, asm>;
multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc,
   }
 }
 
 class MIMG_Mask <string op, int channels> {
   string Op = op;
   int Channels = channels;
 }
 
+class getDMask<int channels> {
+  bits<4> res = !if(!eq(channels,1), 0x1,
+                !if(!eq(channels,2), 0x3,
+                !if(!eq(channels,3), 0x7,
+                !if(!eq(channels,4), 0xF, 0))));
+}
+
+class MIMG_Helper <bits<7> op, dag outs, dag ins, string asm,
+                   int channels,
+                   string dns=""> : MIMG<op, outs, ins, asm,[]> {
+  let mayLoad = 1;
+  let mayStore = 0;
+  let hasPostISelHook = 1;
+  let dmask = getDMask<channels>.res;
+  let DecoderNamespace = dns;
+  let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
+}
+
 class MIMG_NoSampler_Helper <bits<7> op, string asm,
                              RegisterClass dst_rc,
-                             RegisterClass src_rc> : MIMG <
+                             RegisterClass src_rc,
+                             int channels,
+                             string dns=""> : MIMG_Helper <
   op,
   (outs dst_rc:$vdata),
   (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
        SReg_256:$srsrc),
   asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
      #" $tfe, $lwe, $slc, $vaddr, $srsrc",
-  []> {
+  channels, dns> {
   let ssamp = 0;
-  let mayLoad = 1;
-  let mayStore = 0;
-  let hasPostISelHook = 1;
 }
 
 multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm,
                                       RegisterClass dst_rc,
                                       int channels> {
-  def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>,
+  def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, channels, "AMDGPU">,
             MIMG_Mask<asm#"_V1", channels>;
-  def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>,
+  def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64, channels>,
             MIMG_Mask<asm#"_V2", channels>;
-  def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>,
+  def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128, channels>,
             MIMG_Mask<asm#"_V4", channels>;
 }
 
 multiclass MIMG_NoSampler <bits<7> op, string asm> {
   defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
   defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 2>;
   defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 3>;
   defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>;
 }
 
 class MIMG_Sampler_Helper <bits<7> op, string asm,
                            RegisterClass dst_rc,
-                           RegisterClass src_rc, int wqm> : MIMG <
+                           RegisterClass src_rc,
+                           int wqm,
+                           int channels,
+                           string dns=""> : MIMG_Helper <
   op,
   (outs dst_rc:$vdata),
   (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
        SReg_256:$srsrc, SReg_128:$ssamp),
   asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
      #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
-  []> {
-  let mayLoad = 1;
-  let mayStore = 0;
-  let hasPostISelHook = 1;
+  channels, dns> {
   let WQM = wqm;
 }
 
 multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm,
                                     RegisterClass dst_rc,
                                     int channels, int wqm> {
-  def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>,
+  def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm, channels, "AMDGPU">,
             MIMG_Mask<asm#"_V1", channels>;
-  def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
+  def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm, channels>,
             MIMG_Mask<asm#"_V2", channels>;
-  def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
+  def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm, channels>,
             MIMG_Mask<asm#"_V4", channels>;
-  def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
+  def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm, channels>,
             MIMG_Mask<asm#"_V8", channels>;
-  def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
+  def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm, channels>,
             MIMG_Mask<asm#"_V16", channels>;
 }
 
-multiclass MIMG_Sampler <bits<7> op, string asm> {
-  defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>;
-  defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>;
-  defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>;
-  defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>;
+multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> {
+  defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
+  defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>;
+  defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>;
+  defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>;
 }
 
-multiclass MIMG_Sampler_WQM <bits<7> op, string asm> {
-  defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>;
-  defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>;
-  defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>;
-  defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>;
-}
+multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>;
 
 class MIMG_Gather_Helper <bits<7> op, string asm,
                           RegisterClass dst_rc,
                           RegisterClass src_rc, int wqm> : MIMG <
   op,
   (outs dst_rc:$vdata),
   (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
        i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
class MIMG_Gather_Helper <bits<7> op, string asm,
   // the component to fetch. The only useful DMASK values are
   // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
   // (red,red,red,red) etc.) The ISA document doesn't mention
   // this.
   // Therefore, disable all code which updates DMASK by setting these two:
   let MIMG = 0;
   let hasPostISelHook = 0;
   let WQM = wqm;
+
+  let isAsmParserOnly = 1; // TBD: fix it later
 }
 
 multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm,
                                     RegisterClass dst_rc,
                                     int channels, int wqm> {
   def _V1 : MIMG_Gather_Helper <op, asm, dst_rc, VGPR_32, wqm>,
             MIMG_Mask<asm#"_V1", channels>;
   def _V2 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_64, wqm>,
             MIMG_Mask<asm#"_V2", channels>;
   def _V4 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_128, wqm>,
             MIMG_Mask<asm#"_V4", channels>;
   def _V8 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_256, wqm>,
             MIMG_Mask<asm#"_V8", channels>;
   def _V16 : MIMG_Gather_Helper <op, asm, dst_rc, VReg_512, wqm>,
             MIMG_Mask<asm#"_V16", channels>;
 }
 
-multiclass MIMG_Gather <bits<7> op, string asm> {
-  defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>;
-  defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>;
-  defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>;
-  defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>;
+multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> {
+  defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>;
+  defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>;
+  defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>;
+  defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>;
 }
 
-multiclass MIMG_Gather_WQM <bits<7> op, string asm> {
-  defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>;
-  defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>;
-  defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>;
-  defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>;
-}
+multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op, asm, 1>;
 
 //===----------------------------------------------------------------------===//
 // Vector instruction mappings
 //===----------------------------------------------------------------------===//
 
 // Maps an opcode in e32 form to its e64 equivalent
 def getVOPe64 : InstrMapping {
   let FilterClass = "VOP";

lib/Target/AMDGPU/SIInstructions.td

 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", []>;
 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", []>;
 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", []>;
 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", []>;
 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI
 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI
 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI
 
-let SubtargetPredicate = isSI in {
+let SubtargetPredicate = isSI, DisableVIDecoder = 1 in {
 defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI
 }
 
 defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>;
 
 //===----------------------------------------------------------------------===//
 // MTBUF Instructions
 //===----------------------------------------------------------------------===//

 >;
 
 let OtherPredicates = [has32BankLDS] in {
 
 defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m;
 
 } // End OtherPredicates = [has32BankLDS]
 
-let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst" in {
+let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1 in {
 
 defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
 
-} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"
+} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst", isAsmParserOnly=1
 
 let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
 
 defm V_INTERP_P2_F32 : VINTRP_m <
   0x00000001,
   (outs VGPR_32:$dst),
   (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
   "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
defm V_LSHLREV_B32 : VOP2Inst <
   vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag,
     "v_lshl_b32"
 >;
 
 defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>;
 defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>;
 defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>;
 
-let Constraints = "$dst = $src2", DisableEncoding="$src2",
+let Constraints = "$vdst = $src2", DisableEncoding="$src2",
     isConvertibleToThreeAddress = 1 in {
 defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>;
 }
 } // End isCommutable = 1
 
 defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32">;
 
 let isCommutable = 1 in {

 
 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32",
   VOP_I32_I32_I32
 >;
 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32",
   VOP_I32_I32_I32, mulhu
 >;
 
+let DisableVIDecoder=1 in { // removed from VI as identical to V_MUL_LO_U32
 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32",
   VOP_I32_I32_I32
 >;
+}
+
 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32",
   VOP_I32_I32_I32, mulhs
 >;
 
 } // End isCommutable = 1, SchedRW = [WriteQuarterRate32]
 
 let SchedRW = [WriteFloatFMA, WriteSALU] in {
 defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32",

 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>;
 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>;
 
 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32",
   VOP_F32_F32_F32_F32>;
 
 } // End SubtargetPredicate = isSICI
 
-let SubtargetPredicate = isVI in {
+let SubtargetPredicate = isVI, DisableSIDecoder = 1 in {
 
 defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64",
   VOP_I64_I32_I64
 >;
 defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64",
   VOP_I64_I32_I64
 >;
 defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64",
   VOP_I64_I32_I64
 >;
 
 } // End SubtargetPredicate = isVI
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 let isCodeGenOnly = 1, isPseudo = 1 in {
 
 // For use in patterns
-def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$dst),
+def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$vdst),
   (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", []
 >;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in {
 // 64-bit vector move instruction.  This is mainly used by the SIFoldOperands
 // pass to enable folding of inline immediates.
-def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>;
+def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$vdst), (ins VSrc_64:$src0), "", []>;
 } // End let hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 let hasSideEffects = 1, SALU = 1 in {
 def SGPR_USE : InstSI <(outs),(ins), "", []>;
 }
 
 // SI pseudo instructions. These are used by the CFG structurizer pass
 // and should be lowered to ISA instructions prior to codegen.

lib/Target/AMDGPU/SIShrinkInstructions.cpp

for (I = MBB.begin(); I != MBB.end(); I = Next) {
       }
 
       // We can shrink this instruction
       DEBUG(dbgs() << "Shrinking " << MI);
 
       MachineInstrBuilder Inst32 =
           BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
 
-      // Add the dst operand if the 32-bit encoding also has an explicit $dst.
+      // Add the dst operand if the 32-bit encoding also has an explicit $vdst.
       // For VOPC instructions, this is replaced by an implicit def of vcc.
-      int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::dst);
+      int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
       if (Op32DstIdx != -1) {
         // dst
         Inst32.addOperand(MI.getOperand(0));
       } else {
         assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
                "Unexpected case");
       }
 

lib/Target/AMDGPU/VIInstrFormats.td

class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
   let Inst{12-6}  = sdata;
   let Inst{16}    = glc;
   let Inst{17}    = imm;
   let Inst{25-18} = op;
   let Inst{31-26} = 0x30; //encoding
   let Inst{51-32} = offset;
 }
 
-class VOP3e_vi <bits<10> op> : Enc64 {
-  bits<8> vdst;
+class VOP3a_vi <bits<10> op> : Enc64 {
   bits<2> src0_modifiers;
   bits<9> src0;
   bits<2> src1_modifiers;
   bits<9> src1;
   bits<2> src2_modifiers;
   bits<9> src2;
   bits<1> clamp;
   bits<2> omod;
 
-  let Inst{7-0}   = vdst;
   let Inst{8}     = src0_modifiers{1};
   let Inst{9}     = src1_modifiers{1};
   let Inst{10}    = src2_modifiers{1};
   let Inst{15}    = clamp;
   let Inst{25-16} = op;
   let Inst{31-26} = 0x34; //encoding
   let Inst{40-32} = src0;
   let Inst{49-41} = src1;
   let Inst{58-50} = src2;
   let Inst{60-59} = omod;
   let Inst{61} = src0_modifiers{0};
   let Inst{62} = src1_modifiers{0};
   let Inst{63} = src2_modifiers{0};
 }
 
+class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
+  bits<8> vdst;
+
+  let Inst{7-0}   = vdst;
+}
+
+// Encoding used for VOPC instructions encoded as VOP3
+// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
+class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
+  bits<8> sdst;
+
+  let Inst{7-0}   = sdst;
+}
+
 class VOP3be_vi <bits<10> op> : Enc64 {
   bits<8> vdst;
   bits<2> src0_modifiers;
   bits<9> src0;
   bits<2> src1_modifiers;
   bits<9> src1;
   bits<2> src2_modifiers;
   bits<9> src2;

lib/Target/AMDGPU/VIInstructions.td

 //===-- VIInstructions.td - VI Instruction Defintions ---------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 // Instruction definitions for VI and newer.
 //===----------------------------------------------------------------------===//
 
 let SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI in {
 
+let DisableSIDecoder = 1 in {
+
 //===----------------------------------------------------------------------===//
 // VOP1 Instructions
 //===----------------------------------------------------------------------===//
 
 defm V_CVT_F16_U16 : VOP1Inst <vop1<0, 0x39>, "v_cvt_f16_u16", VOP_F16_I16>;
 defm V_CVT_F16_I16 : VOP1Inst <vop1<0, 0x3a>, "v_cvt_f16_i16", VOP_F16_I16>;
 defm V_CVT_U16_F16 : VOP1Inst <vop1<0, 0x3b>, "v_cvt_u16_f16", VOP_I16_F16>;
 defm V_CVT_I16_F16 : VOP1Inst <vop1<0, 0x3c>, "v_cvt_i16_f16", VOP_I16_F16>;

 defm V_MIN_F16 : VOP2Inst <vop2<0,0x2e>, "v_min_f16", VOP_F16_F16_F16>;
 defm V_MAX_U16 : VOP2Inst <vop2<0,0x2f>, "v_max_u16", VOP_I16_I16_I16>;
 defm V_MAX_I16 : VOP2Inst <vop2<0,0x30>, "v_max_i16", VOP_I16_I16_I16>;
 defm V_MIN_U16 : VOP2Inst <vop2<0,0x31>, "v_min_u16", VOP_I16_I16_I16>;
 defm V_MIN_I16 : VOP2Inst <vop2<0,0x32>, "v_min_i16", VOP_I16_I16_I16>;
 } // End isCommutable = 1
 defm V_LDEXP_F16 : VOP2Inst <vop2<0,0x33>, "v_ldexp_f16", VOP_F16_F16_I16>;
 
+} // let DisableSIDecoder = 1
+
 // Aliases to simplify matching of floating-point instructions that
 // are VOP2 on SI and VOP3 on VI.
 
 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
   name#" $dst, $src0, $src1",
   (inst VGPR_32:$dst, 0, VCSrc_32:$src0, 0, VCSrc_32:$src1, 0, 0)
 >, PredicateControl {
   let UseInstAsmMatchConverter = 0;

test/MC/Disassembler/AMDGPU/lit.local.cfg

+if not 'AMDGPU' in config.root.targets:
+    config.unsupported = True

test/MC/Disassembler/AMDGPU/vop1.txt

+# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s
+
+# CHECK: v_nop              ; encoding: [0x00,0x00,0x00,0x7e]
+0x00 0x00 0x00 0x7e
+
+# CHECK: v_clrexcp                       ; encoding: [0x00,0x6a,0x00,0x7e]
+0x00 0x6a 0x00 0x7e
+
+# CHECK: v_mov_b32_e32 v2, v1         ; encoding: [0x01,0x03,0x04,0x7e]
+0x01 0x03 0x04 0x7e
+
+# CHECK: v_mov_b32_e32 v1, 0.5         ; encoding: [0xf0,0x02,0x02,0x7e]
+0xf0 0x02 0x02 0x7e
+
+# CHECK: v_mov_b32_e32 v15, s100         ; encoding: [0x64,0x02,0x1e,0x7e]
+0x64 0x02 0x1e 0x7e
+
+# CHECK: v_mov_b32_e32 v90, flat_scratch_lo         ; encoding: [0x66,0x02,0xb4,0x7e]
+0x66 0x02 0xb4 0x7e
+
+# CHECK: v_mov_b32_e32 v150, vcc_lo         ; encoding: [0x6a,0x02,0x2c,0x7f]
+0x6a 0x02 0x2c 0x7f
+
+# CHECK: v_mov_b32_e32 v199, exec_lo         ; encoding: [0x7e,0x02,0x8e,0x7f]
+0x7e 0x02 0x8e 0x7f
+
+# CHECK: v_mov_b32_e32 v222, m0         ; encoding: [0x7c,0x02,0xbc,0x7f]
+0x7c 0x02 0xbc 0x7f
+
+# CHECK: v_mov_b32_e32 v255, -13         ; encoding: [0xcd,0x02,0xfe,0x7f]
+0xcd 0x02 0xfe 0x7f
+
+# CHECK: v_cvt_f32_i32_e32 v153, s98         ; encoding: [0x62,0x0a,0x32,0x7f]
+0x62 0x0a 0x32 0x7f
+
+# CHECK: v_cvt_f32_u32_e32 v33, -4.0         ; encoding: [0xf7,0x0c,0x42,0x7e]
+0xf7 0x0c 0x42 0x7e
+
+# CHECK: v_cvt_i32_f64_e32 v2, s[0:1]         ; encoding: [0x00,0x06,0x04,0x7e]
+0x00 0x06 0x04 0x7e
+
+# CHECK: v_cvt_u32_f32_e32 v123, vcc_hi  ; encoding: [0x6b,0x0e,0xf6,0x7e]
+0x6b 0x0e 0xf6 0x7e
+
+# CHECK: v_cvt_i32_f32_e32 v123, flat_scratch_lo ; encoding: [0x66,0x10,0xf6,0x7e]
+0x66 0x10 0xf6 0x7e
+
+# CHECK: v_cvt_rpi_i32_f32_e32 v123, s101 ; encoding: [0x65,0x18,0xf6,0x7e]
+0x65 0x18 0xf6 0x7e
+
+# CHECK: v_cvt_flr_i32_f32_e32 v123, -4.0 ; encoding: [0xf7,0x1a,0xf6,0x7e]
+0xf7 0x1a 0xf6 0x7e
+
+# CHECK: v_cvt_f32_f64_e32 v123, vcc      ; encoding: [0x6a,0x1e,0xf6,0x7e]
+0x6a 0x1e 0xf6 0x7e
+
+# CHECK: v_cvt_u32_f64_e32 v123, exec      ; encoding: [0x7e,0x2a,0xf6,0x7e]
+0x7e 0x2a 0xf6 0x7e
+
+# CHECK: v_fract_f32_e32 v123, m0        ; encoding: [0x7c,0x36,0xf6,0x7e]
+0x7c 0x36 0xf6 0x7e
+
+# CHECK: v_trunc_f32_e32 v123, exec_lo   ; encoding: [0x7e,0x38,0xf6,0x7e]
+0x7e 0x38 0xf6 0x7e
+
+# CHECK: v_ceil_f32_e32 v123, exec_hi    ; encoding: [0x7f,0x3a,0xf6,0x7e]
+0x7f 0x3a 0xf6 0x7e
+
+# CHECK: v_rndne_f32_e32 v123, 0         ; encoding: [0x80,0x3c,0xf6,0x7e]
+0x80 0x3c 0xf6 0x7e
+
+# CHECK: v_floor_f32_e32 v123, -0.5      ; encoding: [0xf1,0x3e,0xf6,0x7e]
+0xf1 0x3e 0xf6 0x7e
+
+# CHECK: v_exp_f32_e32 v123, 1.0         ; encoding: [0xf2,0x40,0xf6,0x7e]
+0xf2 0x40 0xf6 0x7e
+
+# CHECK: v_log_f32_e32 v123, -1.0        ; encoding: [0xf3,0x42,0xf6,0x7e]
+0xf3 0x42 0xf6 0x7e
+
+# CHECK: v_rcp_f32_e32 v123, 2.0         ; encoding: [0xf4,0x44,0xf6,0x7e]
+0xf4 0x44 0xf6 0x7e
+
+# CHECK: v_rcp_iflag_f32_e32 v123, -2.0  ; encoding: [0xf5,0x46,0xf6,0x7e]
+0xf5 0x46 0xf6 0x7e
+
+# CHECK: v_rsq_f32_e32 v123, 4.0         ; encoding: [0xf6,0x48,0xf6,0x7e]
+0xf6 0x48 0xf6 0x7e
+
+# CHECK: v_sqrt_f32_e32 v123, v12        ; encoding: [0x0c,0x4f,0xf6,0x7e]
+0x0c 0x4f 0xf6 0x7e
+
+# CHECK: v_sin_f32_e32 v123, v12         ; encoding: [0x0c,0x53,0xf6,0x7e]
+0x0c 0x53 0xf6 0x7e
+
+# CHECK: v_cos_f32_e32 v123, v12         ; encoding: [0x0c,0x55,0xf6,0x7e]
+0x0c 0x55 0xf6 0x7e
+
+# CHECK: v_not_b32_e32 v123, v12         ; encoding: [0x0c,0x57,0xf6,0x7e]
+0x0c 0x57 0xf6 0x7e
+
+# CHECK: v_bfrev_b32_e32 v123, v12       ; encoding: [0x0c,0x59,0xf6,0x7e]
+0x0c 0x59 0xf6 0x7e
+
+# CHECK: v_ffbh_u32_e32 v123, v12        ; encoding: [0x0c,0x5b,0xf6,0x7e]
+0x0c 0x5b 0xf6 0x7e
+
+# CHECK: v_ffbl_b32_e32 v123, v12        ; encoding: [0x0c,0x5d,0xf6,0x7e]
+0x0c 0x5d 0xf6 0x7e
+
+# CHECK: v_ffbh_i32_e32 v123, v12        ; encoding: [0x0c,0x5f,0xf6,0x7e]
+0x0c 0x5f 0xf6 0x7e
+
+# CHECK: v_frexp_exp_i32_f64_e32 v123, 2.0 ; encoding: [0xf4,0x60,0xf6,0x7e]
+0xf4 0x60 0xf6 0x7e
+
+# CHECK: v_frexp_exp_i32_f32_e32 v123, s33 ; encoding: [0x21,0x66,0xf6,0x7e]
+0x21 0x66 0xf6 0x7e
+
+# CHECK: v_frexp_mant_f32_e32 v123, s33  ; encoding: [0x21,0x68,0xf6,0x7e]
+0x21 0x68 0xf6 0x7e
+
+# CHECK: v_movreld_b32_e32 v123, s33     ; encoding: [0x21,0x6c,0xf6,0x7e]
+0x21 0x6c 0xf6 0x7e
+
+# CHECK: v_movrels_b32_e32 v123, s33     ; encoding: [0x21,0x6e,0xf6,0x7e]
+0x21 0x6e 0xf6 0x7e
+
+# CHECK: v_movrelsd_b32_e32 v123, s33    ; encoding: [0x21,0x70,0xf6,0x7e]
+0x21 0x70 0xf6 0x7e
+
+# CHECK: v_cvt_f16_f32_e32 v123, flat_scratch_hi ; encoding: [0x67,0x14,0xf6,0x7e]
+0x67 0x14 0xf6 0x7e
+
+# CHECK: v_cvt_f32_f16_e32 v123, s55     ; encoding: [0x37,0x16,0xf6,0x7e]
+0x37 0x16 0xf6 0x7e
+
+# CHECK: v_cvt_off_f32_i4_e32 v123, v12  ; encoding: [0x0c,0x1d,0xf6,0x7e]
+0x0c 0x1d 0xf6 0x7e
+
+# CHECK: v_cvt_f32_ubyte0_e32 v123, v12  ; encoding: [0x0c,0x23,0xf6,0x7e]
+0x0c 0x23 0xf6 0x7e
+
+# CHECK: v_cvt_f32_ubyte1_e32 v123, v12  ; encoding: [0x0c,0x25,0xf6,0x7e]
+0x0c 0x25 0xf6 0x7e
+
+# CHECK: v_cvt_f32_ubyte2_e32 v123, v12  ; encoding: [0x0c,0x27,0xf6,0x7e]
+0x0c 0x27 0xf6 0x7e
+
+# CHECK: v_cvt_f32_ubyte3_e32 v123, v12  ; encoding: [0x0c,0x29,0xf6,0x7e]
+0x0c 0x29 0xf6 0x7e
+
+# CHECK: v_cvt_f64_i32_e32 v[222:223], 1.0 ; encoding: [0xf2,0x08,0xbc,0x7f]
+0xf2 0x08 0xbc 0x7f
+
+# CHECK: v_cvt_f64_i32_e32 v[222:223], exec_hi ; encoding: [0x7f,0x08,0xbc,0x7f]
+0x7f 0x08 0xbc 0x7f
+
+# CHECK: v_cvt_f64_f32_e32 v[222:223], s33 ; encoding: [0x21,0x20,0xbc,0x7f]
+0x21 0x20 0xbc 0x7f
+
+# CHECK: v_cvt_f64_u32_e32 v[222:223], s33 ; encoding: [0x21,0x2c,0xbc,0x7f]
+0x21 0x2c 0xbc 0x7f
+
+# CHECK: v_rcp_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4a,0xbc,0x7f]
+0x16 0x4a 0xbc 0x7f
+
+# CHECK: v_rsq_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x4c,0xbc,0x7f]
+0x16 0x4c 0xbc 0x7f
+
+# CHECK: v_sqrt_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x50,0xbc,0x7f]
+0x16 0x50 0xbc 0x7f
+
+# CHECK: v_frexp_mant_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x62,0xbc,0x7f]
+0x16 0x62 0xbc 0x7f
+
+# CHECK: v_fract_f64_e32 v[222:223], s[22:23] ; encoding: [0x16,0x64,0xbc,0x7f]
+0x16 0x64 0xbc 0x7f
+
+# CHECK: v_cvt_f16_u16_e32 v123, 23      ; encoding: [0x97,0x72,0xf6,0x7e]
+0x97 0x72 0xf6 0x7e
+
+# CHECK: v_cvt_f16_i16_e32 v123, vcc_hi  ; encoding: [0x6b,0x74,0xf6,0x7e]
+0x6b 0x74 0xf6 0x7e
+
+# CHECK: v_cvt_u16_f16_e32 v123, m0      ; encoding: [0x7c,0x76,0xf6,0x7e]
+0x7c 0x76 0xf6 0x7e
+
+# CHECK: v_cvt_i16_f16_e32 v123, exec_lo ; encoding: [0x7e,0x78,0xf6,0x7e]
+0x7e 0x78 0xf6 0x7e
+
+# CHECK: v_rcp_f16_e32 v123, 1.0         ; encoding: [0xf2,0x7a,0xf6,0x7e]
+0xf2 0x7a 0xf6 0x7e
+
+# CHECK: v_sqrt_f16_e32 v123, 4.0        ; encoding: [0xf6,0x7c,0xf6,0x7e]
+0xf6 0x7c 0xf6 0x7e
+
+# CHECK: v_rsq_f16_e32 v123, -1.0        ; encoding: [0xf3,0x7e,0xf6,0x7e]
+0xf3 0x7e 0xf6 0x7e
+
+# CHECK: v_log_f16_e32 v123, s33         ; encoding: [0x21,0x80,0xf6,0x7e]
+0x21 0x80 0xf6 0x7e
+
+# CHECK: v_exp_f16_e32 v123, v12         ; encoding: [0x0c,0x83,0xf6,0x7e]
+0x0c 0x83 0xf6 0x7e
+
+# CHECK: v_frexp_mant_f16_e32 v123, v12  ; encoding: [0x0c,0x85,0xf6,0x7e]
+0x0c 0x85 0xf6 0x7e
+
+# CHECK: v_frexp_exp_i16_f16_e32 v123, v12 ; encoding: [0x0c,0x87,0xf6,0x7e]
+0x0c 0x87 0xf6 0x7e
+
+# CHECK: v_floor_f16_e32 v123, v12       ; encoding: [0x0c,0x89,0xf6,0x7e]
+0x0c 0x89 0xf6 0x7e
+
+# CHECK: v_ceil_f16_e32 v123, v12        ; encoding: [0x0c,0x8b,0xf6,0x7e]
+0x0c 0x8b 0xf6 0x7e
+
+# CHECK: v_trunc_f16_e32 v123, s33       ; encoding: [0x21,0x8c,0xf6,0x7e]
+0x21 0x8c 0xf6 0x7e
+
+# CHECK: v_rndne_f16_e32 v123, s33       ; encoding: [0x21,0x8e,0xf6,0x7e]
+0x21 0x8e 0xf6 0x7e
+
+# CHECK: v_fract_f16_e32 v123, s33       ; encoding: [0x21,0x90,0xf6,0x7e]
+0x21 0x90 0xf6 0x7e
+
+# CHECK: v_sin_f16_e32 v123, s33         ; encoding: [0x21,0x92,0xf6,0x7e]
+0x21 0x92 0xf6 0x7e
+
+# CHECK: v_cos_f16_e32 v123, s33         ; encoding: [0x21,0x94,0xf6,0x7e]
+0x21 0x94 0xf6 0x7e
+
+# CHECK: v_mov_b32_e32 v2, 0x75bcd15     ; encoding: [0xff,0x02,0x04,0x7e,0x15,0xcd,0x5b,0x07]
+0xff 0x02 0x04 0x7e 0x15 0xcd 0x5b 0x07
+
+# CHECK: v_cvt_f32_u32_e32 v33, 0x4236b732 ; encoding: [0xff,0x0c,0x42,0x7e,0x32,0xb7,0x36,0x42]
+0xff 0x0c 0x42 0x7e 0x32 0xb7 0x36 0x42
+
+# CHECK: v_cvt_i32_f64_e32 v2, 0x4236b732 ; encoding: [0xff,0x06,0x04,0x7e,0x32,0xb7,0x36,0x42]
+0xff 0x06 0x04 0x7e 0x32 0xb7 0x36 0x42
+
+# CHECK: v_cvt_f16_u16_e32 v123, 0x3ade68b1 ; encoding: [0xff,0x72,0xf6,0x7e,0xb1,0x68,0xde,0x3a]
+0xff 0x72 0xf6 0x7e 0xb1 0x68 0xde 0x3a
+
+# CHECK: v_cvt_f16_i16_e32 v123, 0x21c2  ; encoding: [0xff,0x74,0xf6,0x7e,0xc2,0x21,0x00,0x00]
+0xff 0x74 0xf6 0x7e 0xc2 0x21 0x00 0x00
+
+# CHECK: v_cvt_u16_f16_e32 v123, 0x3f200000 ; encoding: [0xff,0x76,0xf6,0x7e,0x00,0x00,0x20,0x3f]
+0xff 0x76 0xf6 0x7e 0x00 0x00 0x20 0x3f
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