[mips] Expansion of BEQL and BNEL with immediate operands

[sdardis]

Summary

Adds support for BEQL and BNEL macros with immediate operands.

Patch by: Srdjan Obucina

[obucina]

Ping

[vkalintiris]

Overall this looks good to me. However, we'll have to add a few more tests before committing this. You can take a look at r239905 in order to get an idea of what we need to change:

test/MC/Mips/branch-pseudos-bad.s
test/MC/Mips/branch-pseudos.s
test/MC/Mips/set-nomacro.s

[obucina]

Can You please be more precise what exactly You are expecting to be changed?

branch-pseudo.s is a set of tests for branch instructions with register operands. I guess You think we need tests for global labels?

branch-pseudo-bad.s also covers branch instructions with register operands. I guess You want to test for AT reg availability here?

set-nomacro.s covers branch instructions, but not branch likely instructions? Do You want to add these two instructions here? For the sake of completeness, what about other branch likely instructions?

Just be more precise, please...

[obucina]

Aditional tests added.

[vkalintiris]

LGTM, with two small comments inline.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

2581

This line is too big, can you split it?

test/MC/Mips/macro-bcc-imm.s

6–37

We don't need the duplicate tests using the bar label.

[obucina]

According to feedback - split long line, redundant tests removed.

[seanbruno]

This patch has aged a bit and doesn't apply cleanly to trunk any longer.

Can this be refreshed to a more recent trunk?

[seanbruno]

Hrm ... I think this one fell off the radar a bit.

[sdardis]

Taking over this patch.

[sdardis]

Updated to trunk, added more tests.

lib/Target/Mips/AsmParser/MipsAsmParser.cpp

case Mips::LWM_MM:
     return expandLoadStoreMultiple(Inst, IDLoc, Instructions) ? MER_Fail
                                                               : MER_Success;
   case Mips::JalOneReg:
   case Mips::JalTwoReg:
     return expandJalWithRegs(Inst, IDLoc, Instructions) ? MER_Fail
                                                         : MER_Success;
   case Mips::BneImm:
   case Mips::BeqImm:
+  case Mips::BEQLImmMacro:
+  case Mips::BNELImmMacro:
     return expandBranchImm(Inst, IDLoc, Instructions) ? MER_Fail : MER_Success;
   case Mips::BLT:
   case Mips::BLE:
   case Mips::BGE:
   case Mips::BGT:
   case Mips::BLTU:
   case Mips::BLEU:
   case Mips::BGEU:
bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc,
                                     SmallVectorImpl<MCInst> &Instructions) {
   const MCOperand &DstRegOp = Inst.getOperand(0);
   assert(DstRegOp.isReg() && "expected register operand kind");
 
   const MCOperand &ImmOp = Inst.getOperand(1);
   assert(ImmOp.isImm() && "expected immediate operand kind");
 
   const MCOperand &MemOffsetOp = Inst.getOperand(2);
-  assert(MemOffsetOp.isImm() && "expected immediate operand kind");
+  assert((MemOffsetOp.isImm() && "expected immediate operand kind") ||
+          (MemOffsetOp.isExpr() && "expected expression operand kind"));
+
+  bool IsLikely = false;
 
   unsigned OpCode = 0;
   switch(Inst.getOpcode()) {
     case Mips::BneImm:
       OpCode = Mips::BNE;
       break;
     case Mips::BeqImm:
       OpCode = Mips::BEQ;
       break;
+    case Mips::BEQLImmMacro:
+      OpCode = Mips::BEQL;
+      IsLikely = true;
+      break;
+    case Mips::BNELImmMacro:
+      OpCode = Mips::BNEL;
+      IsLikely = true;
+      break;
     default:
       llvm_unreachable("Unknown immediate branch pseudo-instruction.");
       break;
   }
 
   int64_t ImmValue = ImmOp.getImm();
-  if (ImmValue == 0)
+  if (ImmValue == 0) {
+    if (IsLikely) {
+      emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
+              MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, Instructions);
+      createNop(false, IDLoc, Instructions);
+    } else
       emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
               Instructions);
-  else {
+  } else {
     warnIfNoMacro(IDLoc);
 
     unsigned ATReg = getATReg(IDLoc);
     if (!ATReg)
       return true;
 
     if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
                       IDLoc, Instructions))
       return true;
 
-    emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, Instructions);
+    if (IsLikely) {
+      emitRRX(OpCode, DstRegOp.getReg(), ATReg, MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc,
+              Instructions);
+      createNop(false, IDLoc, Instructions);
+    } else
+      emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc,
+              Instructions);
   }
   return false;
 }
 
 void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
                                   SmallVectorImpl<MCInst> &Instructions,
                                   bool isLoad, bool isImmOpnd) {
   unsigned ImmOffset, HiOffset, LoOffset;

lib/Target/Mips/MipsInstrInfo.td

 def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
 def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
 def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
 
 class CondBranchImmPseudo<string instr_asm> :
   MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
                     !strconcat(instr_asm, "\t$rs, $imm, $offset")>;
 
+def BEQLImmMacro : CondBranchImmPseudo<"beql">, ISA_MIPS2_NOT_32R6_64R6;
+def BNELImmMacro : CondBranchImmPseudo<"bnel">, ISA_MIPS2_NOT_32R6_64R6;
+
 def BLTImmMacro  : CondBranchImmPseudo<"blt">;
 def BLEImmMacro  : CondBranchImmPseudo<"ble">;
 def BGEImmMacro  : CondBranchImmPseudo<"bge">;
 def BGTImmMacro  : CondBranchImmPseudo<"bgt">;
 def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
 def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
 def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
 def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;

test/MC/Mips/macro-bcc-imm.s

 # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -show-encoding 2>&1 | \
 # RUN:     FileCheck %s --check-prefix=ALL
 
     .text
-foo:                      # ALL-LABEL: foo:
+    beql $a2, 16, foo     # ALL: addiu   $1, $zero, 16
+                          # ALL: beql    $6, $1, foo
+                          # ALL:  # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
+                          # ALL: nop
+    bnel $a2, 16, foo     # ALL: addiu   $1, $zero, 16
+                          # ALL: bnel    $6, $1, foo
+                          # ALL: #   fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
+                          # ALL: nop
+    beql $a2, 32767, foo  # ALL: addiu   $1, $zero, 32767
+                          # ALL: beql    $6, $1, foo
+                          # ALL: #   fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
+                          # ALL: nop
+    bnel $a2, 32768, foo  # ALL: ori     $1, $zero, 32768
+                          # ALL: bnel    $6, $1, foo
+                          # ALL: #   fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
+                          # ALL: nop
     blt $a2, 16, foo      # ALL: addiu $1, $zero, 16
                           # ALL: slt   $1, $6, $1
                           # ALL: bnez  $1, foo
                           # ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
     ble $a2, 16, foo      # ALL: addiu $1, $zero, 16
                           # ALL: slt   $1, $1, $6
                           # ALL: beqz  $1, foo
                           # ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
     bge $a2, 32767, foo   # ALL: addiu $1, $zero, 32767
                           # ALL: slt   $1, $6, $1
                           # ALL: beqz  $1, foo
                           # ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
     bgt $a2, 32768, foo   # ALL: ori   $1, $zero, 32768
                           # ALL: slt   $1, $1, $6
                           # ALL: bnez  $1, foo
                           # ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
     bltu $a2, 16, foo     # ALL: addiu $1, $zero, 16
                           # ALL: sltu  $1, $6, $1
                           # ALL: bnez  $1, foo
                           # ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
     bleu $a2, 16, foo     # ALL: addiu $1, $zero, 16
                           # ALL: sltu  $1, $1, $6
                           # ALL: beqz  $1, foo
                           # ALL: # fixup A - offset: 0, value: foo-4, kind: fixup_Mips_PC16
     bgeu $a2, 32767, foo  # ALL: addiu $1, $zero, 32767