[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions

[zbuljan]

Summary

The patch adds CodeGen support for microMIPSr6 SUBU16, SUB, SUBU, DSUB and DSUBU instructions:

• updated sub.ll with tests for microMIPSr6 SUBU16, SUB, SUBU, DSUB and DSUBU instruction selection
• separated microMIPS64r6 DSUB and DSUBU instructions from equivalent MIPS64 instructions using NotInMicroMips predicate
• added DAG patterns using MipsPat for proper selection of instructions
• implemented DSUB and DSUBU instructions for microMIPS64r6 and added tests for the standard encodings

[sdardis]

Comments inlined.

Can you add invalid tests for dneg(u) with an immediate operand?

In MipsSEDAGToDAGISel::selectNode(SDNode *Node), there is an expansion for the ISD:SUBE node which currently expands to Mips::DSUBu / Mips::SUBu. You will need to extend that to cover micromips.

lib/Target/Mips/MicroMips64r6InstrFormats.td

87–102

Rather than adding this specific class for dsub(u), can you use POOL32SARITH_FM_MMR6 instead of POOL32S_DSUB? They share the same major opcode.

lib/Target/Mips/MicroMips64r6InstrInfo.td

31–32

See my previous comment.

169

One more pattern required, "dnegu $rt".

lib/Target/Mips/Mips64InstrInfo.td

124–129

After you rebase, you can include DSUBu and DSUB in the same block ass DADD and DADDU.

[sdardis]

I've looked farther and you can ignore:

In MipsSEDAGToDAGISel::selectNode(SDNode *Node), there is an expansion for the ISD:SUBE node which currently expands to Mips::DSUBu / Mips::SUBu. You will need to extend that to cover micromips.

We have tables which perform the correct translation to microMIPS(R6).

[zbuljan]

Rebased to work with TOT.
Removed redundant POOL32S_DSUB_FM_MMR6 class and replaced with existing POOL32S_ARITH_FM_MMR6.
Added alias for dnegu $rt.
Added invalid tests for dneg and dnegu with immediate operands.

[sdardis]

LGTM with one very important point.

hvarga has changed the definition of a tablegen class in D19354, so you'll need to make a similar change for SUBU16_MMR6_DESC that was done for ADDU16_MMR6_DESC. Otherwise the instruction selection table is ordered suboptimially and subu16 cannot be chosen.

Thanks.

lib/Target/Mips/MicroMips32r6InstrInfo.td

 //===----------------------------------------------------------------------===//
 //
 // MicroMips arbitrary patterns that map to one or more instructions
 //
 //===----------------------------------------------------------------------===//
 
 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
               (SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
+def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
+              (SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;

lib/Target/Mips/MicroMips64r6InstrFormats.td

class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
 
   let Inst{31-26} = 0b010110;
   let Inst{25-21} = rd;
   let Inst{20-16} = rs;
   let Inst{15-11} = rt;
   let Inst{10-9}  = 0b00;
   let Inst{8-0}  = funct;
 }
+
+class POOL32S_DSUB_FM_MMR6<string instr_asm, bits<9> funct>
+    : MMR6Arch<instr_asm> {
+  bits<5> rd;
+  bits<5> rs;
+  bits<5> rt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010110;
+  let Inst{25-21} = rt;
+  let Inst{20-16} = rs;
+  let Inst{15-11} = rd;
+  let Inst{10-9}  = 0;
+  let Inst{8-0}   = funct;
+}

lib/Target/Mips/MicroMips64r6InstrInfo.td

 class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
 class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
 class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
 class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
 class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
 class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
 class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
 class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
+class DSUB_MM64R6_ENC : POOL32S_DSUB_FM_MMR6<"dsub", 0b110010000>;
+class DSUBU_MM64R6_ENC : POOL32S_DSUB_FM_MMR6<"dsubu", 0b111010000>;
 
 //===----------------------------------------------------------------------===//
 //
 // Instruction Descriptions
 //
 //===----------------------------------------------------------------------===//
 
 class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>

 
 class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>;
 
 class DDIV_MM64R6_DESC : ArithLogicR<"ddiv", GPR32Opnd>;
 class DMOD_MM64R6_DESC : ArithLogicR<"dmod", GPR32Opnd>;
 class DDIVU_MM64R6_DESC : ArithLogicR<"ddivu", GPR32Opnd>;
 class DMODU_MM64R6_DESC : ArithLogicR<"dmodu", GPR32Opnd>;
 
+class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
+                     InstrItinClass Itin = NoItinerary,
+                     SDPatternOperator OpNode = null_frag>
+                     : MipsR6Inst {
+  dag OutOperandList = (outs RO:$rd);
+  dag InOperandList = (ins RO:$rs, RO:$rt);
+  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
+  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
+  InstrItinClass Itinerary = Itin;
+  Format Form = FrmR;
+  string BaseOpcode = instr_asm;
+  let isCommutable = 0;
+  let isReMaterializable = 1;
+  let TwoOperandAliasConstraint = "$rd = $rs";
+}
+class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
+class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
+
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "MicroMipsR6" in {
   def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
let DecoderNamespace = "MicroMipsR6" in {
   def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
                     ISA_MICROMIPS64R6;
   def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
   def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
                      ISA_MICROMIPS64R6;
+  def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
+                    ISA_MICROMIPS64R6;
+  def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
+                     ISA_MICROMIPS64R6;
 }
+
+//===----------------------------------------------------------------------===//
+//
+// Arbitrary patterns that map to one or more instructions
+//
+//===----------------------------------------------------------------------===//
+
+// Carry pattern
+def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
+              (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
+
+//===----------------------------------------------------------------------===//
+//
+// Instruction aliases
+//
+//===----------------------------------------------------------------------===//
+
+def : MipsInstAlias<"dneg $rt, $rs",
+                    (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
+                    ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dneg $rt",
+                    (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
+                    ISA_MICROMIPS64R6;
+def : MipsInstAlias<"dnegu $rt, $rs",
+                    (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
+                    ISA_MICROMIPS64R6;

lib/Target/Mips/MicroMipsInstrInfo.td

def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
               (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>;
 def : MipsPat<(store GPR32:$src, addr:$addr),
               (SW_MM GPR32:$src, addr:$addr)>;
 
 def : MipsPat<(load addrimm4lsl2:$addr),
               (LW16_MM addrimm4lsl2:$addr)>;
 def : MipsPat<(load addr:$addr),
               (LW_MM addr:$addr)>;
+def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
+              (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
 
 //===----------------------------------------------------------------------===//
 // MicroMips instruction aliases
 //===----------------------------------------------------------------------===//
 
 class UncondBranchMMPseudo<string opstr> :
   MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
                     !strconcat(opstr, "\t$offset")>;

lib/Target/Mips/Mips64InstrInfo.td

 def LUi64   : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
 }
 
 /// Arithmetic Instructions (3-Operand, R-Type)
 def DADD   : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
              ISA_MIPS3;
 def DADDu  : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
              ISA_MIPS3;
-def DSUBu  : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
+let AdditionalPredicates = [NotInMicroMips] in {
+  def DSUBu  : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
                ISA_MIPS3;
-def DSUB   : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
+  def DSUB   : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
                ISA_MIPS3;
+}
 
 let isCodeGenOnly = 1 in {
 def SLT64  : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
 def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
 def AND64  : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
 def OR64   : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
 def XOR64  : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;

 // Sign extend in register
 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
               (SLL64_64 GPR64:$src)>;
 
 // bswap MipsPattern
 def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
 
 // Carry pattern
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
                 (DSUBu GPR64:$lhs, GPR64:$rhs)>;
+}
 let AdditionalPredicates = [NotDSP] in {
   def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
                 (DADDu GPR64:$lhs, GPR64:$rhs)>;
   def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
                 (DADDiu GPR64:$lhs, imm:$imm)>;
 }
 
 // Octeon bbit0/bbit1 MipsPattern
def : MipsInstAlias<"daddu $rs, $imm",
                     (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
                     0>, ISA_MIPS3;
 def : MipsInstAlias<"dadd $rs, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsll $rd, $rt, $rs",
                     (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
                     ISA_MIPS3;
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"dneg $rt, $rs",
                       (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
                       ISA_MIPS3;
   def : MipsInstAlias<"dneg $rt",
                       (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
                       ISA_MIPS3;
   def : MipsInstAlias<"dnegu $rt, $rs",
                       (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
                       ISA_MIPS3;
+}
 def : MipsInstAlias<"dsubu $rt, $rs, $imm",
                     (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
                             InvertedImOperand64:$imm), 0>, ISA_MIPS3;
 def : MipsInstAlias<"dsubi $rs, $rt, $imm",
                     (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
                            InvertedImOperand64:$imm),
                     0>, ISA_MIPS3_NOT_32R6_64R6;
 def : MipsInstAlias<"dsubi $rs, $imm",

lib/Target/Mips/MipsInstrInfo.td

 def XORi  : MMRel, StdMMR6Rel,
             ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
             ADDI_FM<0xe>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
 let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu  : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
             ADD_FM<0, 0x21>;
-def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
+def SUBu  : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
             ADD_FM<0, 0x23>;
 }
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
 def ADD   : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
-def SUB   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
+def SUB   : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
 def SLT   : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
 def SLTu  : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
 let AdditionalPredicates = [NotInMicroMips] in {
 def AND   : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
             ADD_FM<0, 0x24>;
 def OR    : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
             ADD_FM<0, 0x25>;
 def XOR   : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,

 def : MipsPat<(i32 immLow16Zero:$in),
               (LUi (HI16 imm:$in))>;
 
 // Arbitrary immediates
 def : MipsPat<(i32 imm:$imm),
           (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
 
 // Carry MipsPatterns
+let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
                 (SUBu GPR32:$lhs, GPR32:$rhs)>;
+}
 let AdditionalPredicates = [NotDSP] in {
   def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
                 (ADDu GPR32:$lhs, GPR32:$rhs)>;
   def : MipsPat<(addc  GPR32:$src, immSExt16:$imm),
                 (ADDiu GPR32:$src, imm:$imm)>;
 }
 
 // Support multiplication for pre-Mips32 targets that don't have

test/CodeGen/Mips/llvm-ir/sub.ll

 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=NOT-R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
+; RUN:    -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=NOT-R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
+; RUN:    -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
+; RUN:    -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
+; RUN:    -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
+; RUN:    -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
+; RUN:    -check-prefix=NOT-MM
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=GP32-MM -check-prefix=GP32 -check-prefix=MM
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=GP32-MM -check-prefix=GP32 -check-prefix=MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN:    -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN:    -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
+; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN:    -check-prefix=GP64 -check-prefix=MM
 
 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
 entry:
 ; ALL-LABEL: sub_i1:
 
-  ; ALL:            subu    $[[T0:[0-9]+]], $4, $5
-  ; ALL:            sll     $[[T0]], $[[T0]], 31
-  ; ALL:            sra     $2, $[[T0]], 31
+  ; NOT-MM:         subu    $[[T0:[0-9]+]], $4, $5
+  ; NOT-MM:         sll     $[[T0]], $[[T0]], 31
+  ; NOT-MM:         sra     $2, $[[T0]], 31
+
+  ; MM:             subu16  $[[T0:[0-9]+]], $4, $5
+  ; MM:             sll     $[[T1:[0-9]+]], $[[T0]], 31
+  ; MM:             sra     $[[T0]], $[[T1]], 31
 
   %r = sub i1 %a, %b
   ret i1 %r
 }
 
 define signext i8 @sub_i8(i8 signext %a, i8 signext %b) {
 entry:
 ; ALL-LABEL: sub_i8:
 
   ; NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
   ; NOT-R2-R6:      sll     $[[T0]], $[[T0]], 24
   ; NOT-R2-R6:      sra     $2, $[[T0]], 24
 
   ; R2-R6:          subu    $[[T0:[0-9]+]], $4, $5
   ; R2-R6:          seb     $2, $[[T0:[0-9]+]]
 
+  ; MM:             subu16  $[[T0:[0-9]+]], $4, $5
+  ; MM:             seb     $[[T0]], $[[T0]]
+
   %r = sub i8 %a, %b
   ret i8 %r
 }
 
 define signext i16 @sub_i16(i16 signext %a, i16 signext %b) {
 entry:
 ; ALL-LABEL: sub_i16:
 
   ; NOT-R2-R6:      subu    $[[T0:[0-9]+]], $4, $5
   ; NOT-R2-R6:      sll     $[[T0]], $[[T0]], 16
   ; NOT-R2-R6:      sra     $2, $[[T0]], 16
 
   ; R2-R6:          subu    $[[T0:[0-9]+]], $4, $5
   ; R2-R6:          seh     $2, $[[T0:[0-9]+]]
 
+  ; MM:             subu16  $[[T0:[0-9]+]], $4, $5
+  ; MM:             seh     $[[T0]], $[[T0]]
+
   %r = sub i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: sub_i32:
 
-  ; ALL:            subu    $2, $4, $5
+  ; NOT-MM:         subu    $2, $4, $5
+
+  ; MM:             subu16  $2, $4, $5
 
   %r = sub i32 %a, %b
   ret i32 %r
 }
 
 define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
 entry:
 ; ALL-LABEL: sub_i64:
 
   ; GP32:           subu    $3, $5, $7
   ; GP32:           sltu    $[[T0:[0-9]+]], $5, $7
   ; GP32:           addu    $[[T1:[0-9]+]], $[[T0]], $6
   ; GP32:           subu    $2, $4, $[[T1]]
 
   ; GP64:           dsubu   $2, $4, $5
 
   %r = sub i64 %a, %b
   ret i64 %r
 }
 
 define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
 entry:
 ; ALL-LABEL: sub_i128:
 
-  ; GP32:       lw        $[[T0:[0-9]+]], 20($sp)
-  ; GP32:       sltu      $[[T1:[0-9]+]], $5, $[[T0]]
-  ; GP32:       lw        $[[T2:[0-9]+]], 16($sp)
-  ; GP32:       addu      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
-  ; GP32:       lw        $[[T4:[0-9]+]], 24($sp)
-  ; GP32:       lw        $[[T5:[0-9]+]], 28($sp)
-  ; GP32:       subu      $[[T6:[0-9]+]], $7, $[[T5]]
-  ; GP32:       subu      $2, $4, $[[T3]]
-  ; GP32:       sltu      $[[T8:[0-9]+]], $6, $[[T4]]
-  ; GP32:       addu      $[[T9:[0-9]+]], $[[T8]], $[[T0]]
-  ; GP32:       subu      $3, $5, $[[T9]]
-  ; GP32:       sltu      $[[T10:[0-9]+]], $7, $[[T5]]
-  ; GP32:       addu      $[[T11:[0-9]+]], $[[T10]], $[[T4]]
-  ; GP32:       subu      $4, $6, $[[T11]]
-  ; GP32:       move      $5, $[[T6]]
+  ; GP32-NOT-MM:    lw        $[[T0:[0-9]+]], 20($sp)
+  ; GP32-NOT-MM:    sltu      $[[T1:[0-9]+]], $5, $[[T0]]
+  ; GP32-NOT-MM:    lw        $[[T2:[0-9]+]], 16($sp)
+  ; GP32-NOT-MM:    addu      $[[T3:[0-9]+]], $[[T1]], $[[T2]]
+  ; GP32-NOT-MM:    lw        $[[T4:[0-9]+]], 24($sp)
+  ; GP32-NOT-MM:    lw        $[[T5:[0-9]+]], 28($sp)
+  ; GP32-NOT-MM:    subu      $[[T6:[0-9]+]], $7, $[[T5]]
+  ; GP32-NOT-MM:    subu      $2, $4, $[[T3]]
+  ; GP32-NOT-MM:    sltu      $[[T8:[0-9]+]], $6, $[[T4]]
+  ; GP32-NOT-MM:    addu      $[[T9:[0-9]+]], $[[T8]], $[[T0]]
+  ; GP32-NOT-MM:    subu      $3, $5, $[[T9]]
+  ; GP32-NOT-MM:    sltu      $[[T10:[0-9]+]], $7, $[[T5]]
+  ; GP32-NOT-MM:    addu      $[[T11:[0-9]+]], $[[T10]], $[[T4]]
+  ; GP32-NOT-MM:    subu      $4, $6, $[[T11]]
+  ; GP32-NOT-MM:    move      $5, $[[T6]]
+
+  ; GP32-MM:        lw        $[[T0:[0-9]+]], 20($sp)
+  ; GP32-MM:        sltu      $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
+  ; GP32-MM:        lw        $[[T3:[0-9]+]], 16($sp)
+  ; GP32-MM:        addu      $[[T3]], $[[T1]], $[[T3]]
+  ; GP32-MM:        lw        $[[T4:[0-9]+]], 28($sp)
+  ; GP32-MM:        subu      $[[T1]], $7, $[[T4]]
+  ; GP32-MM:        subu      $[[T3]], $[[T5:[0-9]+]], $[[T3]]
+  ; GP32-MM:        lw        $[[T5]], 24($sp)
+  ; GP32-MM:        sltu      $[[T6:[0-9]+]], $6, $[[T5]]
+  ; GP32-MM:        addu      $[[T0]], $[[T6]], $[[T0]]
+  ; GP32-MM:        subu      $[[T0]], $5, $[[T0]]
+  ; GP32-MM:        sltu      $[[T2]], $7, $[[T4]]
+  ; GP32-MM:        addu      $[[T5]], $[[T2]], $[[T5]]
+  ; GP32-MM:        subu      $[[T5]], $6, $[[T5]]
+  ; GP32-MM:        move      $[[T2]], $[[T1]]
 
-  ; GP64:       dsubu     $3, $5, $7
-  ; GP64:       sltu      $[[T0:[0-9]+]], $5, $7
-  ; GP64:       daddu     $[[T1:[0-9]+]], $[[T0]], $6
-  ; GP64:       dsubu     $2, $4, $[[T1]]
+  ; GP64:           dsubu     $3, $5, $7
+  ; GP64:           sltu      $[[T0:[0-9]+]], $5, $7
+  ; GP64:           daddu     $[[T1:[0-9]+]], $[[T0]], $6
+  ; GP64:           dsubu     $2, $4, $[[T1]]
 
   %r = sub i128 %a, %b
   ret i128 %r
 }

test/MC/Disassembler/Mips/micromips64r6/valid.txt

 0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
 0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
 0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
 0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
 0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
 0x00 0x00 0xe3 0x7c # CHECK: deret
 0x00 0x00 0x47 0x7c # CHECK: di
 0x00 0x0f 0x47 0x7c # CHECK: di $15
+0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
+0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
+0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
+0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
+0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11

test/MC/Mips/micromips64r6/valid.s

a:
         selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3  # encoding: [0x54,0x62,0x08,0x78]
         selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8  # encoding: [0x55,0x04,0x12,0x78]
         class.s $f2, $f3         # CHECK: class.s $f2, $f3        # encoding: [0x54,0x62,0x00,0x60]
         class.d $f2, $f4         # CHECK: class.d $f2, $f4        # encoding: [0x54,0x82,0x02,0x60]
         deret                    # CHECK: deret                   # encoding: [0x00,0x00,0xe3,0x7c]
         di                       # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $0                    # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
         di $15                   # CHECK: di $15                  # encoding: [0x00,0x0f,0x47,0x7c]
+        dsub $1, $2, $3          # CHECK: dsub $1, $2, $3         # encoding: [0x58,0x62,0x09,0x90]
+        dsubu $3, $7, $15        # CHECK: dsubu $3, $7, $15       # encoding: [0x59,0xe7,0x19,0xd0]
+        dneg $7, $15             # CHECK: dneg $7, $15            # encoding: [0x59,0xe0,0x39,0x90]
+        dneg $10                 # CHECK: dneg $10, $10           # encoding: [0x59,0x40,0x51,0x90]
+        dnegu $1, $11            # CHECK: dnegu $1, $11           # encoding: [0x59,0x60,0x09,0xd0]
 
 1: