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Differential D16659

AMDGPU: Implement known bits functions for min3/max3/med3
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Authored by arsenm on Jan 27 2016, 4:22 PM.

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• tstellarAMD

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arsenm updated this revision to Diff 46198.Jan 27 2016, 4:22 PM
arsenm retitled this revision from to AMDGPU: Implement known bits functions for min3/max3/med3.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptJan 27 2016, 4:22 PM
arsenm added a parent revision: D16658: AMDGPU: Add med3 intrinsics.Jan 27 2016, 4:23 PM
• tstellarAMD added inline comments.Jan 27 2016, 6:55 PM
test/CodeGen/AMDGPU/llvm.amdgcn.smed3.ll
14–17

What exactly are these testing? Is it just checking for crashes?

arsenm added inline comments.Jan 27 2016, 7:00 PM
test/CodeGen/AMDGPU/llvm.amdgcn.smed3.ll
14–17

No, it's making sure the instructions after the med3 node are deleted

• tstellarAMD accepted this revision.Jan 28 2016, 7:15 AM
• tstellarAMD edited edge metadata.

Ok, thanks. LGTM.

This revision is now accepted and ready to land.Jan 28 2016, 7:15 AM
Eugene.Zelenko added a subscriber: Eugene.Zelenko.Sep 26 2016, 2:23 PM

Looks like patch was not committed. Dependency was abandoned.

arsenm closed this revision.Jun 10 2023, 7:59 AM

abff7668aba505a97895eab2476afa4fb1611720 with globalisel port and the intrinsics dropped

lib/Target/AMDGPU/AMDGPUISelLowering.cpp
3151

Typo

Herald added a project: Restricted Project. · View Herald TranscriptJun 10 2023, 7:59 AM
Herald added subscribers: kerbowa, tpr, dstuttard and 4 others. · View Herald Transcript

Revision Contents

PathSize
lib/
Target/
AMDGPU/
38 lines
test/
CodeGen/
AMDGPU/
22 lines
86 lines

Diff 46198

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 3,079 Lines • ▼ Show 20 Lines case AMDGPUISD::BFE_U32: {
unsigned BitWidth = 32; unsigned BitWidth = 32;
uint32_t Width = CWidth->getZExtValue() & 0x1f; uint32_t Width = CWidth->getZExtValue() & 0x1f;
if (Opc == AMDGPUISD::BFE_U32) if (Opc == AMDGPUISD::BFE_U32)
KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width); KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
break; break;
} }
case AMDGPUISD::SMIN3:
case AMDGPUISD::SMAX3:
case AMDGPUISD::SMED3:
case AMDGPUISD::UMIN3:
case AMDGPUISD::UMAX3:
case AMDGPUISD::UMED3: {
APInt Op0Zero, Op0One;
APInt Op1Zero, Op1One;
APInt Op2Zero, Op2One;
DAG.computeKnownBits(Op.getOperand(0), Op0Zero, Op0One, Depth + 1);
DAG.computeKnownBits(Op.getOperand(1), Op1Zero, Op1One, Depth + 1);
DAG.computeKnownBits(Op.getOperand(2), Op2Zero, Op2One, Depth + 1);
KnownZero = Op0Zero & Op1Zero & Op2Zero;
KnownOne = Op0One & Op1One & Op2One;
break;
}
} }
} }
unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode( unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
SDValue Op, SDValue Op,
const SelectionDAG &DAG, const SelectionDAG &DAG,
unsigned Depth) const { unsigned Depth) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
Show All 15 Lines case AMDGPUISD::BFE_U32: {
ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2)); ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1; return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
} }
case AMDGPUISD::CARRY: case AMDGPUISD::CARRY:
case AMDGPUISD::BORROW: case AMDGPUISD::BORROW:
return 31; return 31;
case AMDGPUISD::SMIN3:
case AMDGPUISD::SMAX3:
case AMDGPUISD::SMED3:
case AMDGPUISD::UMIN3:
case AMDGPUISD::UMAX3:
case AMDGPUISD::UMED3: {
unsigned Tmp0 = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
if (Tmp0 == 1)
return 1; // Early out.
unsigned Tmp1 = DAG.ComputeNumSignBits(Op.getOperand(1), Depth + 1);
if (Tmp1 == 1)
return 1; // Early out.
unsigned Tmp2 = DAG.ComputeNumSignBits(Op.getOperand(2), Depth + 1);
if (Tmp1 == 2)
arsenmAuthorUnsubmitted
Done
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Typo

arsenm: Typo
return 1; // Early out.
return std::min(Tmp0, std::min(Tmp1, Tmp2));
}
default: default:
return 1; return 1;
} }
} }

test/CodeGen/AMDGPU/llvm.amdgcn.smed3.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.smed3(i32, i32, i32) #0 declare i32 @llvm.amdgcn.smed3(i32, i32, i32) #0
; GCN-LABEL: {{^}}test_smed3: ; GCN-LABEL: {{^}}test_smed3:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @test_smed3(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #1 { define void @test_smed3(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #1 {
%med3 = call i32 @llvm.amdgcn.smed3(i32 %src0, i32 %src1, i32 %src2) %med3 = call i32 @llvm.amdgcn.smed3(i32 %src0, i32 %src1, i32 %src2)
store i32 %med3, i32 addrspace(1)* %out store i32 %med3, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_smed3_num_sign_bits:
; GCN: v_med3_i32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NEXT: buffer_store_dword [[RESULT]]
define void @test_smed3_num_sign_bits(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 zeroext %src2) #1 {
tstellarAMDUnsubmitted
Not Done
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What exactly are these testing? Is it just checking for crashes?

tstellarAMD: What exactly are these testing? Is it just checking for crashes?
arsenmAuthorUnsubmitted
Not Done
ReplyInline Actions

No, it's making sure the instructions after the med3 node are deleted

arsenm: No, it's making sure the instructions after the med3 node are deleted
%shl0 = shl i32 %src0, 16
%src0.new = ashr i32 %shl0, 16
%shl1 = shl i32 %src1, 17
%src1.new = ashr i32 %shl1, 17
%shl2 = shl i32 %src2, 18
%src2.new = ashr i32 %shl2, 18
%med3 = call i32 @llvm.amdgcn.smed3(i32 %src0.new, i32 %src1.new, i32 %src2.new)
%shl = shl i32 %med3, 16
%sra = ashr i32 %shl, 16
store i32 %sra, i32 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/llvm.amdgcn.umed3.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i32 @llvm.amdgcn.umed3(i32, i32, i32) #0 declare i32 @llvm.amdgcn.umed3(i32, i32, i32) #0
; GCN-LABEL: {{^}}test_umed3: ; GCN-LABEL: {{^}}test_umed3:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define void @test_umed3(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #1 { define void @test_umed3(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #1 {
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0, i32 %src1, i32 %src2) %med3 = call i32 @llvm.amdgcn.umed3(i32 %src0, i32 %src1, i32 %src2)
store i32 %med3, i32 addrspace(1)* %out store i32 %med3, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_umed3_known_bits_zext:
; GCN: v_med3_u32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NEXT: buffer_store_dword [[RESULT]]
define void @test_umed3_known_bits_zext(i32 addrspace(1)* %out, i16 zeroext %src0, i16 zeroext %src1, i16 zeroext %src2) #1 {
%src0.ext = zext i16 %src0 to i32
%src1.ext = zext i16 %src1 to i32
%src2.ext = zext i16 %src2 to i32
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0.ext, i32 %src1.ext, i32 %src2.ext)
%trunc = and i32 %med3, 65535
store i32 %trunc, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}test_umed3_known_sign_bits_sext_in_reg:
; GCN: v_med3_u32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NEXT: buffer_store_dword [[RESULT]]
define void @test_umed3_known_sign_bits_sext_in_reg(i32 addrspace(1)* %out, i16 signext %src0, i16 signext %src1, i16 signext %src2) #1 {
%src0.ext = sext i16 %src0 to i32
%src1.ext = sext i16 %src1 to i32
%src2.ext = sext i16 %src2 to i32
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0.ext, i32 %src1.ext, i32 %src2.ext)
%shl = shl i32 %med3, 16
%sext.in.reg = ashr i32 %shl, 16
store i32 %sext.in.reg, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}test_umed3_known_2_bits:
; GCN: v_med3_u32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NEXT: buffer_store_dword [[RESULT]]
define void @test_umed3_known_2_bits(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 zeroext %src2) #1 {
%shl0 = shl i32 %src0, 30
%src0.new = lshr i32 %shl0, 30
%shl1 = shl i32 %src1, 30
%src1.new = lshr i32 %shl1, 30
%shl2 = shl i32 %src2, 30
%src2.new = lshr i32 %shl2, 30
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0.new, i32 %src1.new, i32 %src2.new)
%trunc = and i32 %med3, 3
store i32 %trunc, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}test_umed3_known_bits_zext_unknown_src0:
; GCN: v_med3_u32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 [[RESULT:v[0-9]+]], 0xffff, [[MED3]]
; GCN: buffer_store_dword [[RESULT]]
define void @test_umed3_known_bits_zext_unknown_src0(i32 addrspace(1)* %out, i32 %src0, i16 zeroext %src1, i16 zeroext %src2) #0 {
%src1.ext = zext i16 %src1 to i32
%src2.ext = zext i16 %src2 to i32
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0, i32 %src1.ext, i32 %src2.ext)
%trunc = and i32 %med3, 65535
store i32 %trunc, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}test_umed3_known_bits_zext_unknown_src1:
; GCN: v_med3_u32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 [[RESULT:v[0-9]+]], 0xffff, [[MED3]]
; GCN: buffer_store_dword [[RESULT]]
define void @test_umed3_known_bits_zext_unknown_src1(i32 addrspace(1)* %out, i16 zeroext %src0, i32 %src1, i16 zeroext %src2) #1 {
%src0.ext = zext i16 %src0 to i32
%src2.ext = zext i16 %src2 to i32
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0.ext, i32 %src1, i32 %src2.ext)
%trunc = and i32 %med3, 65535
store i32 %trunc, i32 addrspace(1)* %out
ret void
}
; GCN-LABEL: {{^}}test_umed3_known_bits_zext_unknown_src2:
; GCN: v_med3_u32 [[MED3:v[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 [[RESULT:v[0-9]+]], 0xffff, [[MED3]]
; GCN: buffer_store_dword [[RESULT]]
define void @test_umed3_known_bits_zext_unknown_src2(i32 addrspace(1)* %out, i16 zeroext %src0, i16 zeroext %src1, i32 %src2) #1 {
%src0.ext = zext i16 %src0 to i32
%src1.ext = zext i16 %src1 to i32
%med3 = call i32 @llvm.amdgcn.umed3(i32 %src0.ext, i32 %src1.ext, i32 %src2)
%trunc = and i32 %med3, 65535
store i32 %trunc, i32 addrspace(1)* %out
ret void
}
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }