[TTI] Add getCacheLineSize

[anemet]

Summary

And use it in PPCLoopDataPrefetch.cpp.

@hfinkel, please let me know if your preference would be to preserve the
ppc-loop-prefetch-cache-line option in order to be able to override the
value of TTI::getCacheLineSize for PPC.

[• hulx2000]

include/llvm/Analysis/TargetTransformInfoImpl.h

267

Return 64 by default is not good, it would be better if assert or return unsupported message by default, and only return 64 for PPC.

[anemet]

include/llvm/Analysis/TargetTransformInfoImpl.h

267

I don't see a precedent for doing such invasive things in the TTI layer itself.

I could return 0 (invalid). That way clients can do the assert or disable any action based on this parameter.

[• hulx2000]

include/llvm/Analysis/TargetTransformInfoImpl.h

267

My concern is :

Now only PPC use this API, which is fine no matter what you do.

However if you return 64 by default, some day other cpu/architecture will start to use it, if people are not careful enough, it will return possibly wrong value for them, give some warning/assert is better than silently return a wrong value, return 0 is ok too.

[anemet]

include/llvm/Analysis/TargetTransformInfoImpl.h

267

OK, 0 sounds like a good compromise. Adding it.

[anemet]

Address hulx2000's comment

[mssimpso]

Adam, this looks good to me, assuming Hal is OK with the flag being removed. I think we'll be able to use this hook in some of the loop optimizations (e.g., interchange).

[anemet]

Now that we have a PPC hook for this, it's actually trivial to retain the the
flag ppc-loop-prefetch-cache-line. This makes the patch NFC, so you ignore my question Hal.

I'll commit this shortly per Geoff's approval. Thanks guys!

[anemet]

In D16306#332450, @anemet wrote:

Now that we have a PPC hook for this, it's actually trivial to retain the the
flag ppc-loop-prefetch-cache-line. This makes the patch NFC, so you ignore my question Hal.

I'll commit this shortly per Geoff's approval. Thanks guys!

Sorry, per Matt, of course.

[mcrosier]

Per Matt (and I agree as well).

include/llvm/Analysis/TargetTransformInfo.h

public:
   /// \return The number of scalar or vector registers that the target has.
   /// If 'Vectors' is true, it returns the number of vector registers. If it is
   /// set to false, it returns the number of scalar registers.
   unsigned getNumberOfRegisters(bool Vector) const;
 
   /// \return The width of the largest scalar or vector register type.
   unsigned getRegisterBitWidth(bool Vector) const;
 
+  /// \return The size of a cache line in bytes.
+  unsigned getCacheLineSize() const;
+
   /// \return The maximum interleave factor that any transform should try to
   /// perform for this target. This number depends on the level of parallelism
   /// and the number of execution units in the CPU.
   unsigned getMaxInterleaveFactor(unsigned VF) const;
 
   /// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
   int getArithmeticInstrCost(
       unsigned Opcode, Type *Ty, OperandValueKind Opd1Info = OK_AnyValue,
public:
   virtual int getFPOpCost(Type *Ty) = 0;
   virtual int getIntImmCost(const APInt &Imm, Type *Ty) = 0;
   virtual int getIntImmCost(unsigned Opc, unsigned Idx, const APInt &Imm,
                             Type *Ty) = 0;
   virtual int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
                             Type *Ty) = 0;
   virtual unsigned getNumberOfRegisters(bool Vector) = 0;
   virtual unsigned getRegisterBitWidth(bool Vector) = 0;
+  virtual unsigned getCacheLineSize() = 0;
   virtual unsigned getMaxInterleaveFactor(unsigned VF) = 0;
   virtual unsigned
   getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
                          OperandValueKind Opd2Info,
                          OperandValueProperties Opd1PropInfo,
                          OperandValueProperties Opd2PropInfo) = 0;
   virtual int getShuffleCost(ShuffleKind Kind, Type *Tp, int Index,
                              Type *SubTp) = 0;
int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
     return Impl.getIntImmCost(IID, Idx, Imm, Ty);
   }
   unsigned getNumberOfRegisters(bool Vector) override {
     return Impl.getNumberOfRegisters(Vector);
   }
   unsigned getRegisterBitWidth(bool Vector) override {
     return Impl.getRegisterBitWidth(Vector);
   }
+  unsigned getCacheLineSize() override {
+    return Impl.getCacheLineSize();
+  }
   unsigned getMaxInterleaveFactor(unsigned VF) override {
     return Impl.getMaxInterleaveFactor(VF);
   }
   unsigned
   getArithmeticInstrCost(unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
                          OperandValueKind Opd2Info,
                          OperandValueProperties Opd1PropInfo,
                          OperandValueProperties Opd2PropInfo) override {

include/llvm/Analysis/TargetTransformInfoImpl.h

unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
                          Type *Ty) {
     return TTI::TCC_Free;
   }
 
   unsigned getNumberOfRegisters(bool Vector) { return 8; }
 
   unsigned getRegisterBitWidth(bool Vector) { return 32; }
 
+  unsigned getCacheLineSize() { return 0; }
+
   unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
 
   unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
                                   TTI::OperandValueKind Opd1Info,
                                   TTI::OperandValueKind Opd2Info,
                                   TTI::OperandValueProperties Opd1PropInfo,
                                   TTI::OperandValueProperties Opd2PropInfo) {
     return 1;

lib/Analysis/TargetTransformInfo.cpp

 unsigned TargetTransformInfo::getNumberOfRegisters(bool Vector) const {
   return TTIImpl->getNumberOfRegisters(Vector);
 }
 
 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
   return TTIImpl->getRegisterBitWidth(Vector);
 }
 
+unsigned TargetTransformInfo::getCacheLineSize() const {
+  return TTIImpl->getCacheLineSize();
+}
+
 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
   return TTIImpl->getMaxInterleaveFactor(VF);
 }
 
 int TargetTransformInfo::getArithmeticInstrCost(
     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
     OperandValueProperties Opd2PropInfo) const {

lib/Target/PowerPC/PPCLoopDataPrefetch.cpp

PrefetchWrites("ppc-loop-prefetch-writes", cl::Hidden, cl::init(false),
                cl::desc("Prefetch write addresses"));
 
 // This seems like a reasonable default for the BG/Q (this pass is enabled, by
 // default, only on the BG/Q).
 static cl::opt<unsigned>
 PrefDist("ppc-loop-prefetch-distance", cl::Hidden, cl::init(300),
          cl::desc("The loop prefetch distance"));
 
-static cl::opt<unsigned>
-CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
-              cl::desc("The loop prefetch cache line size"));
-
 namespace llvm {
   void initializePPCLoopDataPrefetchPass(PassRegistry&);
 }
 
 namespace {
 
   class PPCLoopDataPrefetch : public FunctionPass {
   public:

 
 bool PPCLoopDataPrefetch::runOnFunction(Function &F) {
   LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
   SE = &getAnalysis<ScalarEvolutionWrapperPass>().getSE();
   DL = &F.getParent()->getDataLayout();
   AC = &getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
   TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
 
+  assert(TTI->getCacheLineSize() && "Cache line size is not set for target");
+
   bool MadeChange = false;
 
   for (auto I = LI->begin(), IE = LI->end(); I != IE; ++I)
     for (auto L = df_begin(*I), LE = df_end(*I); L != LE; ++L)
       MadeChange |= runOnLoop(*L);
 
   return MadeChange;
 }
for (BasicBlock::iterator J = (*I)->begin(), JE = (*I)->end();
       bool DupPref = false;
       for (SmallVector<std::pair<Instruction *, const SCEVAddRecExpr *>,
              16>::iterator K = PrefLoads.begin(), KE = PrefLoads.end();
            K != KE; ++K) {
         const SCEV *PtrDiff = SE->getMinusSCEV(LSCEVAddRec, K->second);
         if (const SCEVConstant *ConstPtrDiff =
             dyn_cast<SCEVConstant>(PtrDiff)) {
           int64_t PD = std::abs(ConstPtrDiff->getValue()->getSExtValue());
-          if (PD < (int64_t) CacheLineSize) {
+          if (PD < (int64_t) TTI->getCacheLineSize()) {
             DupPref = true;
             break;
           }
         }
       }
       if (DupPref)
         continue;
 

lib/Target/PowerPC/PPCTargetTransformInfo.h

public:
 
   /// \name Vector TTI Implementations
   /// @{
 
   bool enableAggressiveInterleaving(bool LoopHasReductions);
   bool enableInterleavedAccessVectorization();
   unsigned getNumberOfRegisters(bool Vector);
   unsigned getRegisterBitWidth(bool Vector);
+  unsigned getCacheLineSize();
   unsigned getMaxInterleaveFactor(unsigned VF);
   int getArithmeticInstrCost(
       unsigned Opcode, Type *Ty,
       TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
       TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
   int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);

lib/Target/PowerPC/PPCTargetTransformInfo.cpp

unsigned PPCTTIImpl::getRegisterBitWidth(bool Vector) {
   }
 
   if (ST->isPPC64())
     return 64;
   return 32;
 
 }
 
+unsigned PPCTTIImpl::getCacheLineSize() {
+  // This is currently only used for the data prefetch pass which is only
+  // enabled for BG/Q by default.
+  return 64;
+}
+
 unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) {
   unsigned Directive = ST->getDarwinDirective();
   // The 440 has no SIMD support, but floating-point instructions
   // have a 5-cycle latency, so unroll by 5x for latency hiding.
   if (Directive == PPC::DIR_440)
     return 5;
 
   // The A2 has no SIMD support, but floating-point instructions