[AArch64] Fix schedmodel zero latency moves for Neoverse V2

[rjj]

Summary

Model some register-to-register move operations and move immediate
operations as "zero latency moves", as described in the Software
Optimisation Guide (SOG), §4.12:

https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2/

NB I've assumed there's a mistake in the SOG on p. 63 in the following
instructions:

mov  h1, wzr
mov  h1, xzr
mov  s1, wzr
mov  d1, xzr

(The mov should be an fmov.)

[SjoerdMeijer]

I agree with these observations, wrote a couple of micro-benchmarks, and think that on Grace I can confirm:

These instructions do not utilize the scheduling and execution resources of the machine.

(taken from the SWOG).

I am assuming that fixing this helps LLVM-MCA? I don't expect this to make a difference for performance of the codegen, but what I can offer is to check that with a couple of performance runs on hardware as I am assuming you haven't been able to verify that.

I added one question inline, and am also curious what Dave thinks about this.

llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s

2535–2538

This MOV seems to be affected, but doesn't seem to right?

[rjj]

In D159443#4638215, @SjoerdMeijer wrote:

I agree with these observations, wrote a couple of micro-benchmarks, and think that on Grace I can confirm:

These instructions do not utilize the scheduling and execution resources of the machine.

(taken from the SWOG).

I am assuming that fixing this helps LLVM-MCA? I don't expect this to make a difference for performance of the codegen, but what I can offer is to check that with a couple of performance runs on hardware as I am assuming you haven't been able to verify that.

I added one question inline, and am also curious what Dave thinks about this.

Yep, the main aim of this is to make MCA a bit more accurate. If you could check performance on hardware that would be great!

Cheers,
Ricardo

llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s

2535–2538

That should be the last MOV listed on §4.12, MOV Xd, Xn.

[SjoerdMeijer]

llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s

2535–2538

Ah sorry, missed that. I thought they were only zeroing moves, overlooked the last two moves in that list.

[SjoerdMeijer]

I have ran SPEC FP and INT and this patch didn't change anything, which is what we were hoping for.
So I am okay with this patch and think it makes sense, but allow a few days for the Arm folks to comment before committing.

[dmgreen]

The patch sounds good, if the results look OK. Thanks.

[rjj]

In D159443#4639581, @SjoerdMeijer wrote:

I have ran SPEC FP and INT and this patch didn't change anything, which is what we were hoping for.
So I am okay with this patch and think it makes sense, but allow a few days for the Arm folks to comment before committing.

In D159443#4640116, @dmgreen wrote:

The patch sounds good, if the results look OK. Thanks.

Grand, thanks very much!

llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td

 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
 
 //===----------------------------------------------------------------------===//
 // Define customized scheduler read/write types specific to the Neoverse V2.
 
 //===----------------------------------------------------------------------===//
+
+// Define generic 0 micro-op types
+def V2Write_0cyc : SchedWriteRes<[]> { let Latency = 0; }
+
 // Define generic 1 micro-op types
 
 def V2Write_1cyc_1B    : SchedWriteRes<[V2UnitB]>   { let Latency = 1; }
 def V2Write_1cyc_1F    : SchedWriteRes<[V2UnitF]>   { let Latency = 1; }
 def V2Write_1cyc_1I    : SchedWriteRes<[V2UnitI]>   { let Latency = 1; }
 def V2Write_1cyc_1M    : SchedWriteRes<[V2UnitM]>   { let Latency = 1; }
 def V2Write_1cyc_1M0   : SchedWriteRes<[V2UnitM0]>  { let Latency = 1; }
 def V2Write_1cyc_1L01  : SchedWriteRes<[V2UnitL01]> { let Latency = 1; }

 def V2Write_LdrHQ : SchedWriteVariant<[
                       SchedVar<NeoverseHQForm,  [V2Write_7cyc_1I_1L]>,
                       SchedVar<NoSchedPred,     [V2Write_6cyc_1L]>]>;
 
 def V2Write_StrHQ : SchedWriteVariant<[
                       SchedVar<NeoverseHQForm,  [V2Write_2cyc_1L01_1V01_1I]>,
                       SchedVar<NoSchedPred,     [V2Write_2cyc_1L01_1V01]>]>;
 
+def V2Write_0or1cyc_1I : SchedWriteVariant<[
+                      SchedVar<NeoverseZeroMove, [V2Write_0cyc]>,
+                      SchedVar<NoSchedPred,      [V2Write_1cyc_1I]>]>;
+
+def V2Write_0or2cyc_1V : SchedWriteVariant<[
+                      SchedVar<NeoverseZeroMove, [V2Write_0cyc]>,
+                      SchedVar<NoSchedPred,      [V2Write_2cyc_1V]>]>;
+
+def V2Write_0or3cyc_1M0 : SchedWriteVariant<[
+                      SchedVar<NeoverseZeroMove, [V2Write_0cyc]>,
+                      SchedVar<NoSchedPred,      [V2Write_3cyc_1M0]>]>;
+
 def V2Write_2or3cyc_1M : SchedWriteVariant<[
                       SchedVar<NeoversePdIsPg,  [V2Write_3cyc_1M]>,
                       SchedVar<NoSchedPred,     [V2Write_2cyc_1M]>]>;
 
 def V2Write_3or4cyc_2M : SchedWriteVariant<[
                       SchedVar<NeoversePdIsPg,  [V2Write_4cyc_2M]>,
                       SchedVar<NoSchedPred,     [V2Write_3cyc_2M]>]>;
 

 // Branch and link, register
 def : InstRW<[V2Write_1cyc_1B_1R], (instrs BL, BLR)>;
 
 // §3.4 Arithmetic and Logical Instructions
 // -----------------------------------------------------------------------------
 
 // ALU, basic
 // ALU, basic, flagset
-def : SchedAlias<WriteI,     V2Write_1cyc_1I>;
-def : InstRW<[V2Write_1cyc_1F],
-             (instregex "^(ADC|SBC)S[WX]r$")>;
+def : SchedAlias<WriteI, V2Write_1cyc_1I>;
+def : InstRW<[V2Write_1cyc_1F], (instregex "^(ADC|SBC)S[WX]r$")>;
+def : InstRW<[V2Write_0or1cyc_1I], (instregex "^MOVZ[WX]i$")>;
 
 // ALU, extend and shift
 def : SchedAlias<WriteIEReg, V2Write_2cyc_1M>;
 
 // Arithmetic, LSL shift, shift <= 4
 // Arithmetic, flagset, LSL shift, shift <= 4
 // Arithmetic, LSR/ASR/ROR shift or LSL shift > 4
 def : SchedAlias<WriteISReg, V2Write_ArithI>;

 def : InstRW<[V2Write_2cyc_1M], (instrs IRG, IRGstack)>;
 
 // Insert Tag Mask
 // Subtract Pointer
 // Subtract Pointer, flagset
 def : InstRW<[V2Write_1cyc_1I], (instrs GMI, SUBP, SUBPS)>;
 
 // Logical, shift, no flagset
-def : InstRW<[V2Write_1cyc_1I],
-             (instregex "^(AND|BIC|EON|EOR|ORN|ORR)[WX]rs$")>;
+def : InstRW<[V2Write_1cyc_1I],    (instregex "^(AND|BIC|EON|EOR|ORN)[WX]rs$")>;
+def : InstRW<[V2Write_0or1cyc_1I], (instregex "^ORR[WX]rs$")>;
 
 // Logical, shift, flagset
 def : InstRW<[V2Write_Logical], (instregex "^(AND|BIC)S[WX]rs$")>;
 
 // Move and shift instructions
 // -----------------------------------------------------------------------------
 
 def : SchedAlias<WriteImm, V2Write_1cyc_1I>;

 def : InstRW<[V2Write_3cyc_1V02], (instrs FCVTSHr, FCVTDHr, FCVTHSr, FCVTDSr,
                                           FCVTHDr, FCVTSDr, FCVTXNv1i64)>;
 
 // FP move, immed
 // FP move, register
 def : SchedAlias<WriteFImm, V2Write_2cyc_1V>;
 
 // FP transfer, from gen to low half of vec reg
-def : InstRW<[V2Write_3cyc_1M0], (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
+def : InstRW<[V2Write_0or3cyc_1M0],
+             (instrs FMOVWHr, FMOVXHr, FMOVWSr, FMOVXDr)>;
 
 // FP transfer, from gen to high half of vec reg
 def : InstRW<[V2Write_5cyc_1M0_1V], (instrs FMOVXDHighr)>;
 
 // FP transfer, from vec to gen reg
 def : SchedAlias<WriteFCopy, V2Write_2cyc_2V01>;
 
 // FP load instructions

 // ASIMD insert, element to element
 // ASIMD move, FP immed
 // ASIMD move, integer immed
 // ASIMD reverse
 // ASIMD table lookup extension, 1 table reg
 // ASIMD transpose
 // ASIMD unzip/zip
 // Handled by SchedAlias<WriteV[dq], ...>
+def : InstRW<[V2Write_0or2cyc_1V], (instrs MOVID, MOVIv2d_ns)>;
 
 // ASIMD duplicate, gen reg
 def : InstRW<[V2Write_3cyc_1M0], (instregex "^DUPv.+gpr")>;
 
 // ASIMD extract narrow, saturating
 def : InstRW<[V2Write_4cyc_1V13], (instregex "^[SU]QXTNv", "^SQXTUNv")>;
 
 // ASIMD reciprocal and square root estimate, D-form U32

llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td

 // Identify "[SU]?(MADD|MSUB)L?" as the alias for "[SU]?(MUL|MNEG)L?".
 def NeoverseMULIdiomPred : MCSchedPredicate< // <op> Rd, Rs, Rv, ZR
                              CheckAll<[CheckOpcode<
                                          [MADDWrrr, MADDXrrr,
                                           MSUBWrrr, MSUBXrrr,
                                           SMADDLrrr, UMADDLrrr,
                                           SMSUBLrrr, UMSUBLrrr]>,
                                        CheckIsReg3Zero]>>;
+
+def NeoverseZeroMove : MCSchedPredicate<
+                         CheckAny<[
+                           // MOV Wd, #0
+                           // MOV Xd, #0
+                           CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>,
+                                     CheckAll<[CheckImmOperand<1, 0>,
+                                               CheckImmOperand<2, 0>]>]>,
+                           // MOV Wd, WZR
+                           // MOV Xd, XZR
+                           // MOV Wd, Wn
+                           // MOV Xd, Xn
+                           CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>,
+                                     CheckAll<[CheckIsReg1Zero,
+                                               CheckImmOperand<3, 0>]>]>,
+                           // FMOV Hd, WZR
+                           // FMOV Hd, XZR
+                           // FMOV Sd, WZR
+                           // FMOV Dd, XZR
+                           CheckAll<[CheckOpcode<[FMOVWHr, FMOVXHr,
+                                                  FMOVWSr, FMOVXDr]>,
+                                     CheckIsReg1Zero]>,
+                           // MOVI Dd, #0
+                           // MOVI Vd.2D, #0
+                           CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>,
+                                     CheckImmOperand<1, 0>]>
+                         ]>>;

llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s

 # CHECK-NEXT:  1      1     0.17                        orn x3, x5, x7, asr #2
 # CHECK-NEXT:  1      1     0.17                        orn w2, w5, w29
 # CHECK-NEXT:  1      2     0.50                        ands  w7, wzr, w9, lsl #1
 # CHECK-NEXT:  1      2     0.50                        ands  x3, x5, x20, ror #63
 # CHECK-NEXT:  1      1     0.25                        bics  w3, w5, w7
 # CHECK-NEXT:  1      2     0.50                        bics  x3, xzr, x3, lsl #1
 # CHECK-NEXT:  1      2     0.50                        tst w3, w7, lsl #31
 # CHECK-NEXT:  1      2     0.50                        tst x2, x20, asr #2
-# CHECK-NEXT:  1      1     0.17                        mov x3, x6
-# CHECK-NEXT:  1      1     0.17                        mov x3, xzr
-# CHECK-NEXT:  1      1     0.17                        mov wzr, w2
-# CHECK-NEXT:  1      1     0.17                        mov w3, w5
+# CHECK-NEXT:  1      0     0.06                        mov x3, x6
+# CHECK-NEXT:  1      0     0.06                        mov x3, xzr
+# CHECK-NEXT:  1      0     0.06                        mov wzr, w2
+# CHECK-NEXT:  1      0     0.06                        mov w3, w5
 # CHECK-NEXT:  1      1     0.17                        movz  w2, #0, lsl #16
 # CHECK-NEXT:  1      1     0.17                        mov w2, #-1235
 # CHECK-NEXT:  1      1     0.17                        mov x2, #5299989643264
-# CHECK-NEXT:  1      1     0.17                        mov x2, #0
+# CHECK-NEXT:  1      0     0.06                        mov x2, #0
 # CHECK-NEXT:  1      1     0.17                        movk  w3, #0
 # CHECK-NEXT:  1      1     0.17                        movz  x4, #0, lsl #16
 # CHECK-NEXT:  1      1     0.17                        movk  w5, #0, lsl #16
 # CHECK-NEXT:  1      1     0.17                        movz  x6, #0, lsl #32
 # CHECK-NEXT:  1      1     0.17                        movk  x7, #0, lsl #32
 # CHECK-NEXT:  1      1     0.17                        movz  x8, #0, lsl #48
 # CHECK-NEXT:  1      1     0.17                        movk  x9, #0, lsl #48
 # CHECK-NEXT:  1      1     0.25                        adr x2, #1600

 # CHECK-NEXT: [9]   - V2UnitS3
 # CHECK-NEXT: [10]  - V2UnitV0
 # CHECK-NEXT: [11]  - V2UnitV1
 # CHECK-NEXT: [12]  - V2UnitV2
 # CHECK-NEXT: [13]  - V2UnitV3
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0.0]  [0.1]  [1.0]  [1.1]  [2]    [3.0]  [3.1]  [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
-# CHECK-NEXT: 11.00  11.00  33.00  33.00  99.00  165.00 165.00 327.42 182.42 110.42 110.42 92.67  92.67  190.00 146.00 30.00  10.00
+# CHECK-NEXT: 11.00  11.00  33.00  33.00  99.00  165.00 165.00 326.58 181.58 109.58 109.58 91.83  91.83  190.00 146.00 30.00  10.00
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1.0]  [1.1]  [2]    [3.0]  [3.1]  [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     add  w2, w3, #4095
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     add  w30, w29, #1, lsl #12
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     add  w13, w5, #4095, lsl #12
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     add  x5, x7, #1638
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     add  w20, wsp, #801

 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     orn  x3, x5, x7, asr #2
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     orn  w2, w5, w29
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -     ands w7, wzr, w9, lsl #1
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -     ands x3, x5, x20, ror #63
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.25   0.25   0.25   0.25    -      -      -      -      -      -     bics w3, w5, w7
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -     bics x3, xzr, x3, lsl #1
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -     tst  w3, w7, lsl #31
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -     tst  x2, x20, asr #2
-# CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  x3, x6
-# CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  x3, xzr
-# CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  wzr, w2
-# CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  w3, w5
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  x3, x6
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  x3, xzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  wzr, w2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  w3, w5
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movz w2, #0, lsl #16
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  w2, #-1235
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  x2, #5299989643264
-# CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     mov  x2, #0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  x2, #0
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movk w3, #0
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movz x4, #0, lsl #16
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movk w5, #0, lsl #16
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movz x6, #0, lsl #32
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movk x7, #0, lsl #32
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movz x8, #0, lsl #48
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -      -     movk x9, #0, lsl #48
 # CHECK-NEXT:  -      -      -      -      -      -      -     0.25   0.25   0.25   0.25    -      -      -      -      -      -     adr  x2, #1600

llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-zero-lat-movs.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %s | FileCheck %s
+
+mov  x1, #0
+mov  x1, xzr
+mov  w1, #0
+mov  w1, wzr
+fmov h1, wzr
+fmov h1, xzr
+fmov s1, wzr
+fmov d1, xzr
+movi d1, #0
+movi v1.2d, #0
+mov  w1, w2
+mov  x1, x2
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      0     0.06                        mov x1, #0
+# CHECK-NEXT:  1      0     0.06                        mov x1, xzr
+# CHECK-NEXT:  1      0     0.06                        mov w1, #0
+# CHECK-NEXT:  1      0     0.06                        mov w1, wzr
+# CHECK-NEXT:  1      0     0.06                        fmov  h1, wzr
+# CHECK-NEXT:  1      0     0.06                        fmov  h1, xzr
+# CHECK-NEXT:  1      0     0.06                        fmov  s1, wzr
+# CHECK-NEXT:  1      0     0.06                        fmov  d1, xzr
+# CHECK-NEXT:  1      0     0.06                        movi  d1, #0000000000000000
+# CHECK-NEXT:  1      0     0.06                        movi  v1.2d, #0000000000000000
+# CHECK-NEXT:  1      0     0.06                        mov w1, w2
+# CHECK-NEXT:  1      0     0.06                        mov x1, x2
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0.0] - V2UnitB
+# CHECK-NEXT: [0.1] - V2UnitB
+# CHECK-NEXT: [1.0] - V2UnitD
+# CHECK-NEXT: [1.1] - V2UnitD
+# CHECK-NEXT: [2]   - V2UnitL2
+# CHECK-NEXT: [3.0] - V2UnitL01
+# CHECK-NEXT: [3.1] - V2UnitL01
+# CHECK-NEXT: [4]   - V2UnitM0
+# CHECK-NEXT: [5]   - V2UnitM1
+# CHECK-NEXT: [6]   - V2UnitS0
+# CHECK-NEXT: [7]   - V2UnitS1
+# CHECK-NEXT: [8]   - V2UnitS2
+# CHECK-NEXT: [9]   - V2UnitS3
+# CHECK-NEXT: [10]  - V2UnitV0
+# CHECK-NEXT: [11]  - V2UnitV1
+# CHECK-NEXT: [12]  - V2UnitV2
+# CHECK-NEXT: [13]  - V2UnitV3
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0.0]  [0.1]  [1.0]  [1.1]  [2]    [3.0]  [3.1]  [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0.0]  [0.1]  [1.0]  [1.1]  [2]    [3.0]  [3.1]  [4]    [5]    [6]    [7]    [8]    [9]    [10]   [11]   [12]   [13]   Instructions:
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  x1, #0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  x1, xzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  w1, #0
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  w1, wzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     fmov h1, wzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     fmov h1, xzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     fmov s1, wzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     fmov d1, xzr
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movi d1, #0000000000000000
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movi v1.2d, #0000000000000000
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  w1, w2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     mov  x1, x2