[mlir][spirv] Fix description formatting in BitOps. NFC.

[kuhar]

Summary

Issue: https://github.com/llvm/llvm-project/issues/64765

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td

 }
 
 // -----
 
 def SPIRV_BitCountOp : SPIRV_BitUnaryOp<"BitCount", []> {
   let summary = "Count the number of set bits in an object.";
 
   let description = [{
-     Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.  The components
     must be wide enough to hold the unsigned Width of Base as an unsigned
     value. That is, no sign bit is needed or counted when checking for a
     wide enough result width.
 
     Base must be a scalar or vector of integer type.  It must have the same
     number of components as Result Type.

 def SPIRV_BitFieldInsertOp : SPIRV_Op<"BitFieldInsert",
     [Pure, AllTypesMatch<["base", "insert", "result"]>]> {
   let summary = [{
     Make a copy of an object, with a modified bit field that comes from
     another object.
   }];
 
   let description = [{
-     Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.
 
-     The type of Base and Insert must be the same as Result Type.
 
     Any result bits numbered outside [Offset, Offset + Count -  1]
     (inclusive) will come from the corresponding bits in Base.
 
     Any result bits numbered in [Offset, Offset + Count -  1] come, in
     order, from the bits numbered [0, Count - 1] of Insert.
 
     Count  must be an integer type scalar. Count is the number of bits taken

 
 // -----
 
 def SPIRV_BitFieldSExtractOp : SPIRV_BitFieldExtractOp<"BitFieldSExtract",
                                                    [SignedOp]> {
   let summary = "Extract a bit field from an object, with sign extension.";
 
   let description = [{
-     Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.
 
-     The type of Base must be the same as Result Type.
 
     If Count is greater than 0: The bits of Base numbered in [Offset, Offset
     + Count -  1] (inclusive) become the bits numbered [0, Count - 1] of the
     result. The remaining bits of the result will all be the same as bit
     Offset + Count -  1 of Base.
 
     Count  must be an integer type scalar. Count is the number of bits
     extracted from Base. It will be consumed as an unsigned value. Count can

 }
 
 // -----
 
 def SPIRV_BitReverseOp : SPIRV_BitUnaryOp<"BitReverse", []> {
   let summary = "Reverse the bits in an object.";
 
   let description = [{
-     Results are computed per component.
 
     Result Type must be a scalar or vector of integer type.
 
-     The type of Base must be the same as Result Type.
 
     The bit-number n of the result will be taken from bit-number Width - 1 -
     n of Base, where Width is the OpTypeInt operand of the Result Type.
 
     <!-- End of AutoGen section -->
 
     ```
     integer-scalar-vector-type ::= integer-type |

 def SPIRV_BitwiseAndOp : SPIRV_BitBinaryOp<"BitwiseAnd",
                                        [Commutative, UsableInSpecConstantOp]> {
   let summary = [{
     Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
     Operand 1 or Operand 2 are 0.
   }];
 
   let description = [{
-     Results are computed per component, and within each component, per bit.
 
     Result Type must be a scalar or vector of integer type.  The type of
     Operand 1 and Operand 2  must be a scalar or vector of integer type.
     They must have the same number of components as Result Type. They must
     have the same component width as Result Type.
 
     <!-- End of AutoGen section -->
 

 def SPIRV_BitwiseXorOp : SPIRV_BitBinaryOp<"BitwiseXor",
                                        [Commutative, UsableInSpecConstantOp]> {
   let summary = [{
     Result is 1 if exactly one of Operand 1 or Operand 2 is 1. Result is 0
     if Operand 1 and Operand 2 have the same value.
   }];
 
   let description = [{
-     Results are computed per component, and within each component, per bit.
 
     Result Type must be a scalar or vector of integer type.  The type of
     Operand 1 and Operand 2  must be a scalar or vector of integer type.
     They must have the same number of components as Result Type. They must
     have the same component width as Result Type.
 
     <!-- End of AutoGen section -->
 
def SPIRV_ShiftLeftLogicalOp : SPIRV_ShiftOp<"ShiftLeftLogical",
   let summary = [{
     Shift the bits in Base left by the number of bits specified in Shift.
     The least-significant bits are zero filled.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
-     The type of each Base and Shift must be a scalar or vector of integer
     type. Base and Shift must have the same number of components.  The
     number of components and bit width of the type of Base must be the same
     as in Result Type.
 
     Shift is treated as unsigned. The result is undefined if Shift is
     greater than or equal to the bit width of the components of Base.
 
     The number of components and bit width of Result Type must match those
def SPIRV_ShiftRightArithmeticOp : SPIRV_ShiftOp<"ShiftRightArithmetic",
   let summary = [{
     Shift the bits in Base right by the number of bits specified in Shift.
     The most-significant bits are filled with the sign bit from Base.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
-     The type of each Base and Shift must be a scalar or vector of integer
     type. Base and Shift must have the same number of components.  The
     number of components and bit width of the type of Base must be the same
     as in Result Type.
 
     Shift is treated as unsigned. The result is undefined if Shift is
     greater than or equal to the bit width of the components of Base.
 
-     Results are computed per component.
 
     <!-- End of AutoGen section -->
 
     ```
     integer-scalar-vector-type ::= integer-type |
                                   `vector<` integer-literal `x` integer-type `>`
     shift-right-arithmetic-op ::= ssa-id `=` `spirv.ShiftRightArithmetic`
                                               ssa-use `,` ssa-use `:`
def SPIRV_ShiftRightLogicalOp : SPIRV_ShiftOp<"ShiftRightLogical",
   let summary = [{
     Shift the bits in Base right by the number of bits specified in Shift.
     The most-significant bits are zero filled.
   }];
 
   let description = [{
     Result Type must be a scalar or vector of integer type.
 
-     The type of each Base and Shift must be a scalar or vector of integer
     type. Base and Shift must have the same number of components.  The
     number of components and bit width of the type of Base must be the same
     as in Result Type.
 
     Shift is consumed as an unsigned integer. The result is undefined if
     Shift is greater than or equal to the bit width of the components of
     Base.
 
-     Results are computed per component.
 
     <!-- End of AutoGen section -->
 
     ```
     integer-scalar-vector-type ::= integer-type |
                                   `vector<` integer-literal `x` integer-type `>`
     shift-right-logical-op ::= ssa-id `=` `spirv.ShiftRightLogical`
                                            ssa-use `,` ssa-use `:`

 }
 
 // -----
 
 def SPIRV_NotOp : SPIRV_BitUnaryOp<"Not", [UsableInSpecConstantOp]> {
   let summary = "Complement the bits of Operand.";
 
   let description = [{
-     Results are computed per component, and within each component, per bit.
 
     Result Type must be a scalar or vector of integer type.
 
     Operand's type  must be a scalar or vector of integer type.  It must
     have the same number of components as Result Type.  The component width
     must equal the component width in Result Type.
 
     <!-- End of AutoGen section -->