[PowerPC] Merge rotate and clear into single instruction.

[stefanp]

Summary

This patch tries to catch a codegen opportunity where the rotate and
mask can be merged into a single RLDCL instruction.

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5102

Why does this need to be constant?

llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll

1

Please pre-commit the test case so this patch only shows the differences in code generation.

[stefanp]

Comitted the test case first.
Rebased the change to top of main.

[stefanp]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5102

I'm trying to avoid matching the following kind of pattern:

%2 = tail call i64 @llvm.fshl.i64(i64 %word, i64 %word, i64 23)
%and1 = and i64 %2, 9223372036854775807

The reason for this is that in the above case we can't use RLDCL but we have to use RLDICL instead. See the function tworotates in the test case.

Now, I spent a bit of time and I realize that this condition won't trigger because the above test case is caught earlier by the check in tryBitPermutation. However, I still want to have this here just in case the above changes or the ordering changes in the future. It's just for safety to make sure that we don't try to use an immediate in a place where we shouldn't be using one.

[lei]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5097

nit: maybe move MB and dl def down to right before it's used on line 5106?

5638–5639

nit: indentation

[amyk]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

5102

Can we add that documentation in the code as to why want it to be a constant?

5105

Maybe we can save Val.getOperand(1) separately since we're using it twice in this function.

[stefanp]

Added a comment.
Moved a couple of defs closer to where they are used.
Mostly just address remaining nits.

[lei]

LGTM

[amyk]

LGTM. Thanks for addressing my comment.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 // Include the pieces autogenerated from the target description.
 #include "PPCGenDAGISel.inc"
 
 private:
     bool trySETCC(SDNode *N);
     bool tryFoldSWTestBRCC(SDNode *N);
     bool trySelectLoopCountIntrinsic(SDNode *N);
     bool tryAsSingleRLDICL(SDNode *N);
+    bool tryAsSingleRLDCL(SDNode *N);
     bool tryAsSingleRLDICR(SDNode *N);
     bool tryAsSingleRLWINM(SDNode *N);
     bool tryAsSingleRLWINM8(SDNode *N);
     bool tryAsSingleRLWIMI(SDNode *N);
     bool tryAsPairOfRLDICL(SDNode *N);
     bool tryAsSingleRLDIMI(SDNode *N);
 
     void PeepholePPC64();
SDValue Ops[] = {Val.getOperand(0), Val.getOperand(1), getI32Imm(0, dl),
                      getI32Imm(MB, dl), getI32Imm(ME, dl)};
     ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
     return true;
   }
 
   return false;
 }
 
+bool PPCDAGToDAGISel::tryAsSingleRLDCL(SDNode *N) {
+  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
+
+  uint64_t Imm64;
+  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) || !isMask_64(Imm64))
+    return false;
+
+  SDValue Val = N->getOperand(0);
+
+  if (Val.getOpcode() != ISD::ROTL)
+    return false;
+
+  // Looking to try to avoid a situation like this one:
+  //   %2 = tail call i64 @llvm.fshl.i64(i64 %word, i64 %word, i64 23)
+  //   %and1 = and i64 %2, 9223372036854775807
+  // In this function we are looking to try to match RLDCL. However, the above
+  // DAG would better match RLDICL instead which is not what we are looking
+  // for here.
+  SDValue RotateAmt = Val.getOperand(1);
+  if (RotateAmt.getOpcode() == ISD::Constant)
+    return false;
+
+  unsigned MB = 64 - llvm::countr_one(Imm64);
+  SDLoc dl(N);
+  SDValue Ops[] = {Val.getOperand(0), RotateAmt, getI32Imm(MB, dl)};
+  CurDAG->SelectNodeTo(N, PPC::RLDCL, MVT::i64, Ops);
+  return true;
+}
+
 bool PPCDAGToDAGISel::tryAsSingleRLDICL(SDNode *N) {
   assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
   uint64_t Imm64;
   if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) || !isMask_64(Imm64))
     return false;
 
   // If this is a 64-bit zero-extension mask, emit rldicl.
   unsigned MB = 64 - llvm::countr_one(Imm64);
if (Offset.getOpcode() == ISD::TargetConstant ||
       transferMemOperands(N, MN);
       ReplaceNode(N, MN);
       return;
     }
   }
 
   case ISD::AND:
     // If this is an 'and' with a mask, try to emit rlwinm/rldicl/rldicr
-    if (tryAsSingleRLWINM(N) || tryAsSingleRLWIMI(N) || tryAsSingleRLDICL(N) ||
-        tryAsSingleRLDICR(N) || tryAsSingleRLWINM8(N) || tryAsPairOfRLDICL(N))
+    if (tryAsSingleRLWINM(N) || tryAsSingleRLWIMI(N) || tryAsSingleRLDCL(N) ||
+        tryAsSingleRLDICL(N) || tryAsSingleRLDICR(N) || tryAsSingleRLWINM8(N) ||
+        tryAsPairOfRLDICL(N))
       return;
 
     // Other cases are autogenerated.
     break;
   case ISD::OR: {
     if (N->getValueType(0) == MVT::i32)
       if (tryBitfieldInsert(N))
         return;

llvm/test/CodeGen/PowerPC/ppc-rotate-clear.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
 ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefixes=AIX32
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefixes=AIX64
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefixes=LINUX64BE
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux -mcpu=pwr8 \
 ; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s --check-prefixes=LINUX64LE

 ; AIX32-NEXT:    or r5, r8, r4
 ; AIX32-NEXT:    or r4, r3, r6
 ; AIX32-NEXT:    clrlwi r3, r5, 1
 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: rotatemask64:
 ; AIX64:       # %bb.0: # %entry
 ; AIX64-NEXT:    cntlzd r4, r3
-; AIX64-NEXT:    rotld r3, r3, r4
-; AIX64-NEXT:    clrldi r3, r3, 1
+; AIX64-NEXT:    rldcl r3, r3, r4, 1
 ; AIX64-NEXT:    blr
 ;
 ; LINUX64BE-LABEL: rotatemask64:
 ; LINUX64BE:       # %bb.0: # %entry
 ; LINUX64BE-NEXT:    cntlzd r4, r3
-; LINUX64BE-NEXT:    rotld r3, r3, r4
-; LINUX64BE-NEXT:    clrldi r3, r3, 1
+; LINUX64BE-NEXT:    rldcl r3, r3, r4, 1
 ; LINUX64BE-NEXT:    blr
 ;
 ; LINUX64LE-LABEL: rotatemask64:
 ; LINUX64LE:       # %bb.0: # %entry
 ; LINUX64LE-NEXT:    cntlzd r4, r3
-; LINUX64LE-NEXT:    rotld r3, r3, r4
-; LINUX64LE-NEXT:    clrldi r3, r3, 1
+; LINUX64LE-NEXT:    rldcl r3, r3, r4, 1
 ; LINUX64LE-NEXT:    blr
 entry:
   %0 = tail call i64 @llvm.ctlz.i64(i64 %word, i1 false)
   %1 = tail call i64 @llvm.fshl.i64(i64 %word, i64 %word, i64 %0)
   %and = and i64 %1, 9223372036854775807
   ret i64 %and
 }
 

 ; AIX32-NEXT:    or r5, r8, r4
 ; AIX32-NEXT:    or r4, r3, r6
 ; AIX32-NEXT:    clrlwi r3, r5, 1
 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: rotatemask64_2:
 ; AIX64:       # %bb.0: # %entry
 ; AIX64-NEXT:    cntlzd r4, r3
-; AIX64-NEXT:    rotld r3, r3, r4
-; AIX64-NEXT:    clrldi r3, r3, 1
+; AIX64-NEXT:    rldcl r3, r3, r4, 1
 ; AIX64-NEXT:    blr
 ;
 ; LINUX64BE-LABEL: rotatemask64_2:
 ; LINUX64BE:       # %bb.0: # %entry
 ; LINUX64BE-NEXT:    cntlzd r4, r3
-; LINUX64BE-NEXT:    rotld r3, r3, r4
-; LINUX64BE-NEXT:    clrldi r3, r3, 1
+; LINUX64BE-NEXT:    rldcl r3, r3, r4, 1
 ; LINUX64BE-NEXT:    blr
 ;
 ; LINUX64LE-LABEL: rotatemask64_2:
 ; LINUX64LE:       # %bb.0: # %entry
 ; LINUX64LE-NEXT:    cntlzd r4, r3
-; LINUX64LE-NEXT:    rotld r3, r3, r4
-; LINUX64LE-NEXT:    clrldi r3, r3, 1
+; LINUX64LE-NEXT:    rldcl r3, r3, r4, 1
 ; LINUX64LE-NEXT:    blr
 entry:
   %0 = tail call i64 @llvm.ctlz.i64(i64 %word, i1 false)
   %1 = tail call i64 @llvm.fshl.i64(i64 %word, i64 %word, i64 %0)
   %and = and i64 %1, 9223372036854775807
   ret i64 %and
 }
 

 ; AIX32-NEXT:    slw r3, r3, r5
 ; AIX32-NEXT:    or r5, r8, r4
 ; AIX32-NEXT:    or r4, r3, r6
 ; AIX32-NEXT:    clrlwi r3, r5, 8
 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: rotatemask64_nocount:
 ; AIX64:       # %bb.0: # %entry
-; AIX64-NEXT:    rotld r3, r3, r4
-; AIX64-NEXT:    clrldi r3, r3, 8
+; AIX64-NEXT:    rldcl r3, r3, r4, 8
 ; AIX64-NEXT:    blr
 ;
 ; LINUX64BE-LABEL: rotatemask64_nocount:
 ; LINUX64BE:       # %bb.0: # %entry
-; LINUX64BE-NEXT:    rotld r3, r3, r4
-; LINUX64BE-NEXT:    clrldi r3, r3, 8
+; LINUX64BE-NEXT:    rldcl r3, r3, r4, 8
 ; LINUX64BE-NEXT:    blr
 ;
 ; LINUX64LE-LABEL: rotatemask64_nocount:
 ; LINUX64LE:       # %bb.0: # %entry
-; LINUX64LE-NEXT:    rotld r3, r3, r4
-; LINUX64LE-NEXT:    clrldi r3, r3, 8
+; LINUX64LE-NEXT:    rldcl r3, r3, r4, 8
 ; LINUX64LE-NEXT:    blr
 entry:
   %0 = tail call i64 @llvm.fshl.i64(i64 %word, i64 %word, i64 %clz)
   %and = and i64 %0, 72057594037927935
   ret i64 %and
 }
 
 define dso_local i64 @builtincheck(i64 noundef %word, i64 noundef %shift) local_unnamed_addr #0 {

 ; AIX32-NEXT:    slw r3, r3, r5
 ; AIX32-NEXT:    or r5, r8, r4
 ; AIX32-NEXT:    or r4, r3, r6
 ; AIX32-NEXT:    clrlwi r3, r5, 1
 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: builtincheck:
 ; AIX64:       # %bb.0: # %entry
-; AIX64-NEXT:    rotld r3, r3, r4
-; AIX64-NEXT:    clrldi r3, r3, 1
+; AIX64-NEXT:    rldcl r3, r3, r4, 1
 ; AIX64-NEXT:    blr
 ;
 ; LINUX64BE-LABEL: builtincheck:
 ; LINUX64BE:       # %bb.0: # %entry
-; LINUX64BE-NEXT:    rotld r3, r3, r4
-; LINUX64BE-NEXT:    clrldi r3, r3, 1
+; LINUX64BE-NEXT:    rldcl r3, r3, r4, 1
 ; LINUX64BE-NEXT:    blr
 ;
 ; LINUX64LE-LABEL: builtincheck:
 ; LINUX64LE:       # %bb.0: # %entry
-; LINUX64LE-NEXT:    rotld r3, r3, r4
-; LINUX64LE-NEXT:    clrldi r3, r3, 1
+; LINUX64LE-NEXT:    rldcl r3, r3, r4, 1
 ; LINUX64LE-NEXT:    blr
 entry:
   %0 = tail call i64 @llvm.fshl.i64(i64 %word, i64 %word, i64 %shift)
   %1 = and i64 %0, 9223372036854775807
   ret i64 %1
 }
 
 define dso_local i64 @immshift(i64 noundef %word) local_unnamed_addr #0 {

 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: twomasks:
 ; AIX64:       # %bb.0: # %entry
 ; AIX64-NEXT:    mflr r0
 ; AIX64-NEXT:    stdu r1, -112(r1)
 ; AIX64-NEXT:    cntlzd r4, r3
 ; AIX64-NEXT:    std r0, 128(r1)
-; AIX64-NEXT:    rotld r4, r3, r4
-; AIX64-NEXT:    clrldi r3, r4, 1
-; AIX64-NEXT:    clrldi r4, r4, 16
+; AIX64-NEXT:    rldcl r5, r3, r4, 1
+; AIX64-NEXT:    rldcl r4, r3, r4, 16
+; AIX64-NEXT:    mr r3, r5
 ; AIX64-NEXT:    bl .callee[PR]
 ; AIX64-NEXT:    nop
 ; AIX64-NEXT:    addi r1, r1, 112
 ; AIX64-NEXT:    ld r0, 16(r1)
 ; AIX64-NEXT:    mtlr r0
 ; AIX64-NEXT:    blr
 ;
 ; LINUX64BE-LABEL: twomasks:
 ; LINUX64BE:       # %bb.0: # %entry
 ; LINUX64BE-NEXT:    mflr r0
 ; LINUX64BE-NEXT:    stdu r1, -112(r1)
 ; LINUX64BE-NEXT:    cntlzd r4, r3
 ; LINUX64BE-NEXT:    std r0, 128(r1)
-; LINUX64BE-NEXT:    rotld r4, r3, r4
-; LINUX64BE-NEXT:    clrldi r3, r4, 1
-; LINUX64BE-NEXT:    clrldi r4, r4, 16
+; LINUX64BE-NEXT:    rldcl r5, r3, r4, 1
+; LINUX64BE-NEXT:    rldcl r4, r3, r4, 16
+; LINUX64BE-NEXT:    mr r3, r5
 ; LINUX64BE-NEXT:    bl callee
 ; LINUX64BE-NEXT:    nop
 ; LINUX64BE-NEXT:    addi r1, r1, 112
 ; LINUX64BE-NEXT:    ld r0, 16(r1)
 ; LINUX64BE-NEXT:    mtlr r0
 ; LINUX64BE-NEXT:    blr
 ;
 ; LINUX64LE-LABEL: twomasks:
 ; LINUX64LE:       # %bb.0: # %entry
 ; LINUX64LE-NEXT:    mflr r0
 ; LINUX64LE-NEXT:    stdu r1, -32(r1)
 ; LINUX64LE-NEXT:    cntlzd r4, r3
 ; LINUX64LE-NEXT:    std r0, 48(r1)
-; LINUX64LE-NEXT:    rotld r4, r3, r4
-; LINUX64LE-NEXT:    clrldi r3, r4, 1
-; LINUX64LE-NEXT:    clrldi r4, r4, 16
+; LINUX64LE-NEXT:    rldcl r5, r3, r4, 1
+; LINUX64LE-NEXT:    rldcl r4, r3, r4, 16
+; LINUX64LE-NEXT:    mr r3, r5
 ; LINUX64LE-NEXT:    bl callee
 ; LINUX64LE-NEXT:    nop
 ; LINUX64LE-NEXT:    addi r1, r1, 32
 ; LINUX64LE-NEXT:    ld r0, 16(r1)
 ; LINUX64LE-NEXT:    mtlr r0
 ; LINUX64LE-NEXT:    blr
 entry:
   %0 = tail call i64 @llvm.ctlz.i64(i64 %word, i1 false)

 ; AIX32-NEXT:    blr
 ;
 ; AIX64-LABEL: tworotates:
 ; AIX64:       # %bb.0: # %entry
 ; AIX64-NEXT:    mflr r0
 ; AIX64-NEXT:    stdu r1, -112(r1)
 ; AIX64-NEXT:    cntlzd r4, r3
 ; AIX64-NEXT:    std r0, 128(r1)
-; AIX64-NEXT:    rotld r4, r3, r4
-; AIX64-NEXT:    clrldi r5, r4, 1
+; AIX64-NEXT:    rldcl r5, r3, r4, 1
 ; AIX64-NEXT:    rldicl r4, r3, 23, 1
 ; AIX64-NEXT:    mr r3, r5
 ; AIX64-NEXT:    bl .callee[PR]
 ; AIX64-NEXT:    nop
 ; AIX64-NEXT:    addi r1, r1, 112
 ; AIX64-NEXT:    ld r0, 16(r1)
 ; AIX64-NEXT:    mtlr r0
 ; AIX64-NEXT:    blr
 ;
 ; LINUX64BE-LABEL: tworotates:
 ; LINUX64BE:       # %bb.0: # %entry
 ; LINUX64BE-NEXT:    mflr r0
 ; LINUX64BE-NEXT:    stdu r1, -112(r1)
 ; LINUX64BE-NEXT:    cntlzd r4, r3
 ; LINUX64BE-NEXT:    std r0, 128(r1)
-; LINUX64BE-NEXT:    rotld r4, r3, r4
-; LINUX64BE-NEXT:    clrldi r5, r4, 1
+; LINUX64BE-NEXT:    rldcl r5, r3, r4, 1
 ; LINUX64BE-NEXT:    rldicl r4, r3, 23, 1
 ; LINUX64BE-NEXT:    mr r3, r5
 ; LINUX64BE-NEXT:    bl callee
 ; LINUX64BE-NEXT:    nop
 ; LINUX64BE-NEXT:    addi r1, r1, 112
 ; LINUX64BE-NEXT:    ld r0, 16(r1)
 ; LINUX64BE-NEXT:    mtlr r0
 ; LINUX64BE-NEXT:    blr
 ;
 ; LINUX64LE-LABEL: tworotates:
 ; LINUX64LE:       # %bb.0: # %entry
 ; LINUX64LE-NEXT:    mflr r0
 ; LINUX64LE-NEXT:    stdu r1, -32(r1)
 ; LINUX64LE-NEXT:    cntlzd r4, r3
 ; LINUX64LE-NEXT:    std r0, 48(r1)
-; LINUX64LE-NEXT:    rotld r4, r3, r4
-; LINUX64LE-NEXT:    clrldi r5, r4, 1
+; LINUX64LE-NEXT:    rldcl r5, r3, r4, 1
 ; LINUX64LE-NEXT:    rldicl r4, r3, 23, 1
 ; LINUX64LE-NEXT:    mr r3, r5
 ; LINUX64LE-NEXT:    bl callee
 ; LINUX64LE-NEXT:    nop
 ; LINUX64LE-NEXT:    addi r1, r1, 32
 ; LINUX64LE-NEXT:    ld r0, 16(r1)
 ; LINUX64LE-NEXT:    mtlr r0
 ; LINUX64LE-NEXT:    blr