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Differential D158173

AMDGPU: Select f64 fmul by negative power of 2 to ldexp
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Authored by arsenm on Aug 17 2023, 4:45 AM.

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foad
rampitec
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Restricted Project
Summary

Select fmul x, -K -> ldexp(-x, log2(fabsK))
Select fmul fabs(x), -K -> ldexp(-|x|, log2(fabsK))

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arsenm created this revision.Aug 17 2023, 4:45 AM
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arsenm requested review of this revision.Aug 17 2023, 4:45 AM
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arsenm added a parent revision: D158102: APFloat: Add getExactLog2Abs.Aug 17 2023, 4:45 AM
Harbormaster completed remote builds in B253187: Diff 551090.Aug 17 2023, 4:46 AM
arsenm added a comment.Aug 23 2023, 4:31 PM

ping

arsenm added a reviewer: rampitec.Aug 23 2023, 4:31 PM
rampitec accepted this revision.Aug 23 2023, 5:16 PM

LGTM. JFYI, Jay is on vacation.

This revision is now accepted and ready to land.Aug 23 2023, 5:16 PM
arsenm mentioned this in rG16bc07ac9105: AMDGPU: Select f64 fmul by negative power of 2 to ldexp.Aug 23 2023, 5:39 PM
arsenm closed this revision.Aug 23 2023, 5:39 PM

16bc07ac9105dd87745e0335b057c217efadd4dc

Revision Contents

Diff 551090

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 5,125 Lines • ▼ Show 20 Linesvoid AMDGPUInstructionSelector::renderFrameIndex(MachineInstrBuilder &MIB,
int OpIdx) const { int OpIdx) const {
MIB.addFrameIndex(MI.getOperand(1).getIndex()); MIB.addFrameIndex(MI.getOperand(1).getIndex());
} }
void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB, void AMDGPUInstructionSelector::renderFPPow2ToExponent(MachineInstrBuilder &MIB,
const MachineInstr &MI, const MachineInstr &MI,
int OpIdx) const { int OpIdx) const {
const APFloat &APF = MI.getOperand(1).getFPImm()->getValueAPF(); const APFloat &APF = MI.getOperand(1).getFPImm()->getValueAPF();
int ExpVal = APF.getExactLog2(); int ExpVal = APF.getExactLog2Abs();
assert(ExpVal != INT_MIN); assert(ExpVal != INT_MIN);
MIB.addImm(ExpVal); MIB.addImm(ExpVal);
} }
bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const { bool AMDGPUInstructionSelector::isInlineImmediate16(int64_t Imm) const {
return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm()); return AMDGPU::isInlinableLiteral16(Imm, STI.hasInv2PiInlineImm());
} }
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llvm/lib/Target/AMDGPU/SIInstructions.td

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defm : Int16Med3Pat<V_MED3_I16_e64, smin, smax>; defm : Int16Med3Pat<V_MED3_I16_e64, smin, smax>;
defm : Int16Med3Pat<V_MED3_U16_e64, umin, umax>; defm : Int16Med3Pat<V_MED3_U16_e64, umin, umax>;
} // End Predicates = [isGFX9Plus] } // End Predicates = [isGFX9Plus]
// Convert a floating-point power of 2 to the integer exponent. // Convert a floating-point power of 2 to the integer exponent.
def FPPow2ToExponentXForm : SDNodeXForm<fpimm, [{ def FPPow2ToExponentXForm : SDNodeXForm<fpimm, [{
const auto &APF = N->getValueAPF(); const auto &APF = N->getValueAPF();
int Log2 = APF.getExactLog2(); int Log2 = APF.getExactLog2Abs();
assert(Log2 != INT_MIN); assert(Log2 != INT_MIN);
return CurDAG->getTargetConstant(Log2, SDLoc(N), MVT::i32); return CurDAG->getTargetConstant(Log2, SDLoc(N), MVT::i32);
}]>; }]>;
// Check if a floating point value is a power of 2 floating-point // Check if a floating point value is a power of 2 floating-point
// immediate where it's preferable to emit a multiply by as an // immediate where it's preferable to emit a multiply by as an
// ldexp. We skip over 0.5 to 4.0 as those are inline immediates // ldexp. We skip over 0.5 to 4.0 as those are inline immediates
// anyway. // anyway.
def fpimm_pow2_prefer_ldexp_f64 : FPImmLeaf<f64, [{ def fpimm_pos_pow2_prefer_ldexp_f64 : FPImmLeaf<f64, [{
int Exp = Imm.getExactLog2(); if (Imm.isNegative())
return false;
int Exp = Imm.getExactLog2Abs();
// Prefer leaving the FP inline immediates as they are.
// 0.5, 1.0, 2.0, 4.0
// For f64 ldexp is always better than materializing a 64-bit
// constant.
return Exp != INT_MIN && (Exp < -1 || Exp > 2);
}], FPPow2ToExponentXForm
>;
def fpimm_neg_pow2_prefer_ldexp_f64 : FPImmLeaf<f64, [{
if (!Imm.isNegative())
return false;
int Exp = Imm.getExactLog2Abs();
// Prefer leaving the FP inline immediates as they are. // Prefer leaving the FP inline immediates as they are.
// 0.5, 1.0, 2.0, 4.0 // 0.5, 1.0, 2.0, 4.0
// For f64 ldexp is always better than materializing a 64-bit // For f64 ldexp is always better than materializing a 64-bit
// constant. // constant.
return Exp != INT_MIN && (Exp < -1 || Exp > 2); return Exp != INT_MIN && (Exp < -1 || Exp > 2);
}], FPPow2ToExponentXForm }], FPPow2ToExponentXForm
>; >;
// f64 is different because we also want to handle cases that may // f64 is different because we also want to handle cases that may
// require materialization of the exponent. // require materialization of the exponent.
// TODO: If we know f64 ops are fast, prefer add (ldexp x, N), y over fma // TODO: If we know f64 ops are fast, prefer add (ldexp x, N), y over fma
// TODO: fmul x, -2^n -> ldexp(-x, n)
// TODO: For f32/f16, it's not a clear win on code size to use ldexp // TODO: For f32/f16, it's not a clear win on code size to use ldexp
// in place of mul since we have to use the vop3 form. Are there power // in place of mul since we have to use the vop3 form. Are there power
// savings or some other reason to prefer ldexp over mul? // savings or some other reason to prefer ldexp over mul?
def : GCNPat< def : GCNPat<
(any_fmul (f64 (VOP3Mods f64:$src0, i32:$src0_mods)), (any_fmul (f64 (VOP3Mods f64:$src0, i32:$src0_mods)),
fpimm_pow2_prefer_ldexp_f64:$src1), fpimm_pos_pow2_prefer_ldexp_f64:$src1),
(V_LDEXP_F64_e64 i32:$src0_mods, VSrc_b64:$src0, (V_LDEXP_F64_e64 i32:$src0_mods, VSrc_b64:$src0,
0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1)))) 0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1))))
>; >;
def : GCNPat<
(any_fmul f64:$src0, fpimm_neg_pow2_prefer_ldexp_f64:$src1),
(V_LDEXP_F64_e64 SRCMODS.NEG, VSrc_b64:$src0,
0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1))))
>;
// We want to avoid using VOP3Mods which could pull in another fneg
// which we would need tobe re-negated (which should never happen in
// practice). I don't see a way to apply an SDNodeXForm that accounts
// for a second operand.
def : GCNPat<
(any_fmul (fabs f64:$src0), fpimm_neg_pow2_prefer_ldexp_f64:$src1),
(V_LDEXP_F64_e64 SRCMODS.NEG_ABS, VSrc_b64:$src0,
0, (S_MOV_B32 (i32 (FPPow2ToExponentXForm $src1))))
>;
class AMDGPUGenericInstruction : GenericInstruction { class AMDGPUGenericInstruction : GenericInstruction {
let Namespace = "AMDGPU"; let Namespace = "AMDGPU";
} }
// Convert a wave address to a swizzled vector address (i.e. this is // Convert a wave address to a swizzled vector address (i.e. this is
// for copying the stack pointer to a vector address appropriate to // for copying the stack pointer to a vector address appropriate to
// use in the offset field of mubuf instructions). // use in the offset field of mubuf instructions).
def G_AMDGPU_WAVE_ADDRESS : AMDGPUGenericInstruction { def G_AMDGPU_WAVE_ADDRESS : AMDGPUGenericInstruction {
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llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

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body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GCN-LABEL: name: fmul_to_ldexp_f64_2 ; GCN-LABEL: name: fmul_to_ldexp_f64_2
; GCN: liveins: $vgpr0_vgpr1 ; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1070596096, implicit $exec ; GCN-NEXT: [[V_LDEXP_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_LDEXP_F64_e64 1, [[COPY]], 0, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_LDEXP_F64_e64_]]
; GCN-NEXT: [[V_MUL_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MUL_F64_e64 0, [[COPY]], 0, [[REG_SEQUENCE]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_MUL_F64_e64_]]
; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1 ; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FCONSTANT double -16.0 %1:vgpr(s64) = G_FCONSTANT double -16.0
%2:vgpr(s64) = G_FMUL %0, %1 %2:vgpr(s64) = G_FMUL %0, %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
SI_RETURN implicit $vgpr0_vgpr1 SI_RETURN implicit $vgpr0_vgpr1
... ...
--- ---
name: fmul_to_ldexp_f64_3 name: fmul_to_ldexp_f64_3
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GCN-LABEL: name: fmul_to_ldexp_f64_3 ; GCN-LABEL: name: fmul_to_ldexp_f64_3
; GCN: liveins: $vgpr0_vgpr1 ; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1070596096, implicit $exec ; GCN-NEXT: [[V_LDEXP_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_LDEXP_F64_e64 3, [[COPY]], 0, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 ; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_LDEXP_F64_e64_]]
; GCN-NEXT: [[V_MUL_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MUL_F64_e64 2, [[COPY]], 0, [[REG_SEQUENCE]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_MUL_F64_e64_]]
; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1 ; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FABS %0 %1:vgpr(s64) = G_FABS %0
%2:vgpr(s64) = G_FCONSTANT double -16.0 %2:vgpr(s64) = G_FCONSTANT double -16.0
%3:vgpr(s64) = G_FMUL %1, %2 %3:vgpr(s64) = G_FMUL %1, %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
SI_RETURN implicit $vgpr0_vgpr1 SI_RETURN implicit $vgpr0_vgpr1
... ...
--- ---
name: fmul_to_ldexp_f64_4 name: fmul_to_ldexp_f64_4
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; GCN-LABEL: name: fmul_to_ldexp_f64_4 ; GCN-LABEL: name: fmul_to_ldexp_f64_4
; GCN: liveins: $vgpr0_vgpr1 ; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}} ; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1 ; GCN-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 -1070596096, implicit $exec ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1 ; GCN-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
; GCN-NEXT: [[V_MUL_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_MUL_F64_e64 3, [[COPY]], 0, [[REG_SEQUENCE]], 0, 0, implicit $mode, implicit $exec ; GCN-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_MUL_F64_e64_]] ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_OR_B32_e64_]], %subreg.sub1
; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 4
; GCN-NEXT: [[V_LDEXP_F64_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_LDEXP_F64_e64 1, [[REG_SEQUENCE]], 0, [[S_MOV_B32_1]], 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[V_LDEXP_F64_e64_]]
; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1 ; GCN-NEXT: SI_RETURN implicit $vgpr0_vgpr1
%0:vgpr(s64) = COPY $vgpr0_vgpr1 %0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = G_FABS %0 %1:vgpr(s64) = G_FABS %0
%2:vgpr(s64) = G_FNEG %1 %2:vgpr(s64) = G_FNEG %1
%3:vgpr(s64) = G_FCONSTANT double -16.0 %3:vgpr(s64) = G_FCONSTANT double -16.0
%4:vgpr(s64) = G_FMUL %2, %3 %4:vgpr(s64) = G_FMUL %2, %3
$vgpr0_vgpr1 = COPY %4 $vgpr0_vgpr1 = COPY %4
SI_RETURN implicit $vgpr0_vgpr1 SI_RETURN implicit $vgpr0_vgpr1
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llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,043 Lines • ▼ Show 20 Lines
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0.5 ; GFX11-GISEL-NEXT: s_mov_b32 s1, 0.5
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, 0.000030517578125 %mul = fmul double %x, 0.000030517578125
ret double %mul ret double %mul
} }
define double @v_mul_neg256_f64(double %x) { define double @v_mul_neg256_f64(double %x) {
; GFX9-LABEL: v_mul_neg256_f64: ; GFX9-SDAG-LABEL: v_mul_neg256_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 8
; GFX9-NEXT: s_mov_b32 s5, 0xc0700000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg256_f64: ; GFX9-GISEL-LABEL: v_mul_neg256_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0700000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0700000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg256_f64: ; GFX10-SDAG-LABEL: v_mul_neg256_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 8
; GFX11-NEXT: s_mov_b32 s1, 0xc0700000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg256_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0700000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg256_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 8
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg256_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0700000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -256.0 %mul = fmul double %x, -256.0
ret double %mul ret double %mul
} }
define double @v_mul_neg128_f64(double %x) { define double @v_mul_neg128_f64(double %x) {
; GFX9-LABEL: v_mul_neg128_f64: ; GFX9-SDAG-LABEL: v_mul_neg128_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 7
; GFX9-NEXT: s_mov_b32 s5, 0xc0600000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg128_f64: ; GFX9-GISEL-LABEL: v_mul_neg128_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0600000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0600000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg128_f64: ; GFX10-SDAG-LABEL: v_mul_neg128_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 7
; GFX11-NEXT: s_mov_b32 s1, 0xc0600000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg128_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0600000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg128_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 7
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg128_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0600000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -128.0 %mul = fmul double %x, -128.0
ret double %mul ret double %mul
} }
define double @v_mul_neg64_f64(double %x) { define double @v_mul_neg64_f64(double %x) {
; GFX9-LABEL: v_mul_neg64_f64: ; GFX9-SDAG-LABEL: v_mul_neg64_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 6
; GFX9-NEXT: s_mov_b32 s5, 0xc0500000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg64_f64: ; GFX9-GISEL-LABEL: v_mul_neg64_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0500000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0500000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg64_f64: ; GFX10-SDAG-LABEL: v_mul_neg64_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 6
; GFX11-NEXT: s_mov_b32 s1, 0xc0500000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg64_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0500000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg64_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 6
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg64_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0500000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -64.0 %mul = fmul double %x, -64.0
ret double %mul ret double %mul
} }
define double @v_mul_neg32_f64(double %x) { define double @v_mul_neg32_f64(double %x) {
; GFX9-LABEL: v_mul_neg32_f64: ; GFX9-SDAG-LABEL: v_mul_neg32_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 5
; GFX9-NEXT: s_mov_b32 s5, 0xc0400000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg32_f64: ; GFX9-GISEL-LABEL: v_mul_neg32_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0400000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0400000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg32_f64: ; GFX10-SDAG-LABEL: v_mul_neg32_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 5
; GFX11-NEXT: s_mov_b32 s1, 0xc0400000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg32_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0400000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg32_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 5
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg32_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0400000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -32.0 %mul = fmul double %x, -32.0
ret double %mul ret double %mul
} }
define double @v_mul_neg16_f64(double %x) { define double @v_mul_neg16_f64(double %x) {
; GFX9-LABEL: v_mul_neg16_f64: ; GFX9-SDAG-LABEL: v_mul_neg16_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 4
; GFX9-NEXT: s_mov_b32 s5, 0xc0300000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg16_f64: ; GFX9-GISEL-LABEL: v_mul_neg16_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0300000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0300000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg16_f64: ; GFX10-SDAG-LABEL: v_mul_neg16_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 4
; GFX11-NEXT: s_mov_b32 s1, 0xc0300000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg16_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0300000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg16_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 4
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg16_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0300000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -16.0 %mul = fmul double %x, -16.0
ret double %mul ret double %mul
} }
define double @v_mul_neg8_f64(double %x) { define double @v_mul_neg8_f64(double %x) {
; GFX9-LABEL: v_mul_neg8_f64: ; GFX9-SDAG-LABEL: v_mul_neg8_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 3
; GFX9-NEXT: s_mov_b32 s5, 0xc0200000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg8_f64: ; GFX9-GISEL-LABEL: v_mul_neg8_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0200000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0200000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg8_f64: ; GFX10-SDAG-LABEL: v_mul_neg8_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 3
; GFX11-NEXT: s_mov_b32 s1, 0xc0200000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg8_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0200000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg8_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 3
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg8_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0200000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -8.0 %mul = fmul double %x, -8.0
ret double %mul ret double %mul
} }
define double @v_mul_neg4_f64(double %x) { define double @v_mul_neg4_f64(double %x) {
; GCN-LABEL: v_mul_neg4_f64: ; GCN-LABEL: v_mul_neg4_f64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], -0.5 ; GCN-NEXT: v_mul_f64 v[0:1], v[0:1], -0.5
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -0.5 %mul = fmul double %x, -0.5
ret double %mul ret double %mul
} }
define double @v_mul_neg_quarter_f64(double %x) { define double @v_mul_neg_quarter_f64(double %x) {
; GFX9-LABEL: v_mul_neg_quarter_f64: ; GFX9-SDAG-LABEL: v_mul_neg_quarter_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], -2
; GFX9-NEXT: s_mov_b32 s5, 0xbfd00000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg_quarter_f64: ; GFX9-GISEL-LABEL: v_mul_neg_quarter_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xbfd00000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xbfd00000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg_quarter_f64: ; GFX10-SDAG-LABEL: v_mul_neg_quarter_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], -2
; GFX11-NEXT: s_mov_b32 s1, 0xbfd00000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg_quarter_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xbfd00000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg_quarter_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], -2
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg_quarter_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xbfd00000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul double %x, -0.25 %mul = fmul double %x, -0.25
ret double %mul ret double %mul
} }
define double @v_mul_quarter_f64(double %x) { define double @v_mul_quarter_f64(double %x) {
; GFX9-SDAG-LABEL: v_mul_quarter_f64: ; GFX9-SDAG-LABEL: v_mul_quarter_f64:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: v_mul_f64 v[2:3], v[2:3], s[0:1] ; GFX11-GISEL-NEXT: v_mul_f64 v[2:3], v[2:3], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul <2 x double> %x, <double 16.0, double 16.0> %mul = fmul <2 x double> %x, <double 16.0, double 16.0>
ret <2 x double> %mul ret <2 x double> %mul
} }
define <2 x double> @v_mul_neg16_v2f64(<2 x double> %x) { define <2 x double> @v_mul_neg16_v2f64(<2 x double> %x) {
; GFX9-LABEL: v_mul_neg16_v2f64: ; GFX9-SDAG-LABEL: v_mul_neg16_v2f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 4
; GFX9-NEXT: s_mov_b32 s5, 0xc0300000 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[2:3], -v[2:3], 4
; GFX9-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[2:3], v[2:3], s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_neg16_v2f64: ; GFX9-GISEL-LABEL: v_mul_neg16_v2f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0300000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0300000
; GFX10-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-NEXT: v_mul_f64 v[2:3], v[2:3], s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[2:3], v[2:3], s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_neg16_v2f64: ; GFX10-SDAG-LABEL: v_mul_neg16_v2f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 4
; GFX11-NEXT: s_mov_b32 s1, 0xc0300000 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[2:3], -v[2:3], 4
; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1] ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[2:3], v[2:3], s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_neg16_v2f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0300000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[4:5]
; GFX10-GISEL-NEXT: v_mul_f64 v[2:3], v[2:3], s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_neg16_v2f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -v[0:1], 4
; GFX11-SDAG-NEXT: v_ldexp_f64 v[2:3], -v[2:3], 4
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_neg16_v2f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0300000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], v[0:1], s[0:1]
; GFX11-GISEL-NEXT: v_mul_f64 v[2:3], v[2:3], s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%mul = fmul <2 x double> %x, <double -16.0, double -16.0> %mul = fmul <2 x double> %x, <double -16.0, double -16.0>
ret <2 x double> %mul ret <2 x double> %mul
} }
define <2 x double> @v_mul_fabs_16_v2f64(<2 x double> %x) { define <2 x double> @v_mul_fabs_16_v2f64(<2 x double> %x) {
; GFX9-SDAG-LABEL: v_mul_fabs_16_v2f64: ; GFX9-SDAG-LABEL: v_mul_fabs_16_v2f64:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1] ; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] ; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call double @llvm.fabs.f64(double %x) %fabs.x = call double @llvm.fabs.f64(double %x)
%mul = fmul double %fabs.x, 4.34584737989687770135e-311 %mul = fmul double %fabs.x, 4.34584737989687770135e-311
ret double %mul ret double %mul
} }
define double @v_mul_fabs_neg256_f64(double %x) { define double @v_mul_fabs_neg256_f64(double %x) {
; GFX9-LABEL: v_mul_fabs_neg256_f64: ; GFX9-SDAG-LABEL: v_mul_fabs_neg256_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, 8
; GFX9-NEXT: s_mov_b32 s5, 0xc0700000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_fabs_neg256_f64: ; GFX9-GISEL-LABEL: v_mul_fabs_neg256_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0700000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0700000
; GFX10-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_fabs_neg256_f64: ; GFX10-SDAG-LABEL: v_mul_fabs_neg256_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, 8
; GFX11-NEXT: s_mov_b32 s1, 0xc0700000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_fabs_neg256_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0700000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_fabs_neg256_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, 8
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_fabs_neg256_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0700000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call double @llvm.fabs.f64(double %x) %fabs.x = call double @llvm.fabs.f64(double %x)
%mul = fmul double %fabs.x, -256.0 %mul = fmul double %fabs.x, -256.0
ret double %mul ret double %mul
} }
define double @v_mul_fabs_neg8_f64(double %x) { define double @v_mul_fabs_neg8_f64(double %x) {
; GFX9-LABEL: v_mul_fabs_neg8_f64: ; GFX9-SDAG-LABEL: v_mul_fabs_neg8_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, 3
; GFX9-NEXT: s_mov_b32 s5, 0xc0200000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_fabs_neg8_f64: ; GFX9-GISEL-LABEL: v_mul_fabs_neg8_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xc0200000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xc0200000
; GFX10-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_fabs_neg8_f64: ; GFX10-SDAG-LABEL: v_mul_fabs_neg8_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, 3
; GFX11-NEXT: s_mov_b32 s1, 0xc0200000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_fabs_neg8_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xc0200000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_fabs_neg8_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, 3
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_fabs_neg8_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xc0200000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call double @llvm.fabs.f64(double %x) %fabs.x = call double @llvm.fabs.f64(double %x)
%mul = fmul double %fabs.x, -8.0 %mul = fmul double %fabs.x, -8.0
ret double %mul ret double %mul
} }
define double @v_mul_fabs_neg4_f64(double %x) { define double @v_mul_fabs_neg4_f64(double %x) {
; GCN-LABEL: v_mul_fabs_neg4_f64: ; GCN-LABEL: v_mul_fabs_neg4_f64:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
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; GCN-NEXT: v_mul_f64 v[0:1], |v[0:1]|, -0.5 ; GCN-NEXT: v_mul_f64 v[0:1], |v[0:1]|, -0.5
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call double @llvm.fabs.f64(double %x) %fabs.x = call double @llvm.fabs.f64(double %x)
%mul = fmul double %fabs.x, -0.5 %mul = fmul double %fabs.x, -0.5
ret double %mul ret double %mul
} }
define double @v_mul_fabs_negquarter_f64(double %x) { define double @v_mul_fabs_negquarter_f64(double %x) {
; GFX9-LABEL: v_mul_fabs_negquarter_f64: ; GFX9-SDAG-LABEL: v_mul_fabs_negquarter_f64:
; GFX9: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 0 ; GFX9-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, -2
; GFX9-NEXT: s_mov_b32 s5, 0xbfd00000 ; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX9-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_mul_fabs_negquarter_f64: ; GFX9-GISEL-LABEL: v_mul_fabs_negquarter_f64:
; GFX10: ; %bb.0: ; GFX9-GISEL: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, 0 ; GFX9-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-NEXT: s_mov_b32 s5, 0xbfd00000 ; GFX9-GISEL-NEXT: s_mov_b32 s5, 0xbfd00000
; GFX10-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5] ; GFX9-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_mul_fabs_negquarter_f64: ; GFX10-SDAG-LABEL: v_mul_fabs_negquarter_f64:
; GFX11: ; %bb.0: ; GFX10-SDAG: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s0, 0 ; GFX10-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, -2
; GFX11-NEXT: s_mov_b32 s1, 0xbfd00000 ; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1] ;
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX10-GISEL-LABEL: v_mul_fabs_negquarter_f64:
; GFX10-GISEL: ; %bb.0:
; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-GISEL-NEXT: s_mov_b32 s4, 0
; GFX10-GISEL-NEXT: s_mov_b32 s5, 0xbfd00000
; GFX10-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[4:5]
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-LABEL: v_mul_fabs_negquarter_f64:
; GFX11-SDAG: ; %bb.0:
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-SDAG-NEXT: v_ldexp_f64 v[0:1], -|v[0:1]|, -2
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-LABEL: v_mul_fabs_negquarter_f64:
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-GISEL-NEXT: s_mov_b32 s0, 0
; GFX11-GISEL-NEXT: s_mov_b32 s1, 0xbfd00000
; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], |v[0:1]|, s[0:1]
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
%fabs.x = call double @llvm.fabs.f64(double %x) %fabs.x = call double @llvm.fabs.f64(double %x)
%mul = fmul double %fabs.x, -0.25 %mul = fmul double %fabs.x, -0.25
ret double %mul ret double %mul
} }
define double @v_mul_fabs_quarter_f64(double %x) { define double @v_mul_fabs_quarter_f64(double %x) {
; GFX9-SDAG-LABEL: v_mul_fabs_quarter_f64: ; GFX9-SDAG-LABEL: v_mul_fabs_quarter_f64:
; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG: ; %bb.0:
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