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Differential D157867

AMDGPU: Handle unsafe exp.f32 with denormal handling
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Authored by arsenm on Aug 14 2023, 6:54 AM.

Details

Reviewers
foad
rampitec
Pierre-vh
Group Reviewers
Restricted Project
Summary

I somehow missed this path when adding the new expansions. Saves a lot
of instructions for afn + IEEE.

Diff Detail

Event Timeline

arsenm created this revision.Aug 14 2023, 6:54 AM
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arsenm requested review of this revision.Aug 14 2023, 6:54 AM
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Harbormaster completed remote builds in B252336: Diff 549914.Aug 14 2023, 8:28 AM
rampitec accepted this revision.Aug 14 2023, 10:30 AM
This revision is now accepted and ready to land.Aug 14 2023, 10:30 AM
arsenm closed this revision.Aug 14 2023, 3:36 PM

1faa4797ca7cfef0b38e8404ae316e4728c2e67a

arsenm mentioned this in rG1faa4797ca7c: AMDGPU: Handle unsafe exp.f32 with denormal handling.Aug 14 2023, 3:36 PM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
40 lines
40 lines
test/
CodeGen/
AMDGPU/
1320 lines

Diff 549914

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 2,754 Lines • ▼ Show 20 LinesSDValue AMDGPUTargetLowering::lowerFEXP2(SDValue Op, SelectionDAG &DAG) const {
SDValue TwoExpNeg64 = DAG.getConstantFP(0x1.0p-64f, SL, VT); SDValue TwoExpNeg64 = DAG.getConstantFP(0x1.0p-64f, SL, VT);
SDValue One = DAG.getConstantFP(1.0, SL, VT); SDValue One = DAG.getConstantFP(1.0, SL, VT);
SDValue ResultScale = SDValue ResultScale =
DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, TwoExpNeg64, One); DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, TwoExpNeg64, One);
return DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScale, Flags); return DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScale, Flags);
} }
SDValue AMDGPUTargetLowering::lowerFEXPUnsafe(SDValue Op, const SDLoc &SL, SDValue AMDGPUTargetLowering::lowerFEXPUnsafe(SDValue X, const SDLoc &SL,
SelectionDAG &DAG, SelectionDAG &DAG,
SDNodeFlags Flags) const { SDNodeFlags Flags) const {
EVT VT = X.getValueType();
const SDValue Log2E = DAG.getConstantFP(numbers::log2e, SL, VT);
if (VT != MVT::f32 || !needsDenormHandlingF32(DAG, X, Flags)) {
// exp2(M_LOG2E_F * f); // exp2(M_LOG2E_F * f);
EVT VT = Op.getValueType(); SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, X, Log2E, Flags);
const SDValue K = DAG.getConstantFP(numbers::log2e, SL, VT); return DAG.getNode(VT == MVT::f32 ? AMDGPUISD::EXP : ISD::FEXP2, SL, VT,
SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Op, K, Flags); Mul, Flags);
return DAG.getNode(VT == MVT::f32 ? AMDGPUISD::EXP : ISD::FEXP2, SL, VT, Mul, }
EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
SDValue Threshold = DAG.getConstantFP(-0x1.5d58a0p+6f, SL, VT);
SDValue NeedsScaling = DAG.getSetCC(SL, SetCCVT, X, Threshold, ISD::SETOLT);
SDValue ScaleOffset = DAG.getConstantFP(0x1.0p+6f, SL, VT);
SDValue ScaledX = DAG.getNode(ISD::FADD, SL, VT, X, ScaleOffset, Flags);
SDValue AdjustedX =
DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, ScaledX, X);
SDValue ExpInput = DAG.getNode(ISD::FMUL, SL, VT, AdjustedX, Log2E, Flags);
SDValue Exp2 = DAG.getNode(AMDGPUISD::EXP, SL, VT, ExpInput, Flags);
SDValue ResultScaleFactor = DAG.getConstantFP(0x1.969d48p-93f, SL, VT);
SDValue AdjustedResult =
DAG.getNode(ISD::FMUL, SL, VT, Exp2, ResultScaleFactor, Flags);
return DAG.getNode(ISD::SELECT, SL, VT, NeedsScaling, AdjustedResult, Exp2,
Flags); Flags);
} }
SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const { SDValue AMDGPUTargetLowering::lowerFEXP(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDLoc SL(Op); SDLoc SL(Op);
SDValue X = Op.getOperand(0); SDValue X = Op.getOperand(0);
SDNodeFlags Flags = Op->getFlags(); SDNodeFlags Flags = Op->getFlags();
Show All 16 Lines if (VT.getScalarType() == MVT::f16) {
return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered, return DAG.getNode(ISD::FP_ROUND, SL, VT, Lowered,
DAG.getTargetConstant(0, SL, MVT::i32), Flags); DAG.getTargetConstant(0, SL, MVT::i32), Flags);
} }
assert(VT == MVT::f32); assert(VT == MVT::f32);
// TODO: Interpret allowApproxFunc as ignoring DAZ. This is currently copying // TODO: Interpret allowApproxFunc as ignoring DAZ. This is currently copying
// library behavior. Also, is known-not-daz source sufficient? // library behavior. Also, is known-not-daz source sufficient?
if (allowApproxFunc(DAG, Flags) && !needsDenormHandlingF32(DAG, X, Flags)) { if (allowApproxFunc(DAG, Flags)) {
assert(!IsExp10 && "todo exp10 support"); assert(!IsExp10 && "todo exp10 support");
return lowerFEXPUnsafe(X, SL, DAG, Flags); return lowerFEXPUnsafe(X, SL, DAG, Flags);
} }
// Algorithm: // Algorithm:
// //
// e^x = 2^(x/ln(2)) = 2^(x*(64/ln(2))/64) // e^x = 2^(x/ln(2)) = 2^(x*(64/ln(2))/64)
// //
▲ Show 20 Lines • Show All 2,928 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 3,298 Lines • ▼ Show 20 Linesbool AMDGPULegalizerInfo::legalizeFExp2(MachineInstr &MI,
auto One = B.buildFConstant(Ty, 1.0); auto One = B.buildFConstant(Ty, 1.0);
auto ResultScale = B.buildSelect(F32, NeedsScaling, TwoExpNeg64, One, Flags); auto ResultScale = B.buildSelect(F32, NeedsScaling, TwoExpNeg64, One, Flags);
B.buildFMul(Dst, Exp2, ResultScale, Flags); B.buildFMul(Dst, Exp2, ResultScale, Flags);
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
bool AMDGPULegalizerInfo::legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst, bool AMDGPULegalizerInfo::legalizeFExpUnsafe(MachineIRBuilder &B, Register Dst,
Register Src, Register X, unsigned Flags) const {
unsigned Flags) const {
LLT Ty = B.getMRI()->getType(Dst); LLT Ty = B.getMRI()->getType(Dst);
auto K = B.buildFConstant(Ty, numbers::log2e); LLT F32 = LLT::scalar(32);
auto Mul = B.buildFMul(Ty, Src, K, Flags);
if (Ty != F32 || !needsDenormHandlingF32(B.getMF(), X, Flags)) {
auto Log2E = B.buildFConstant(Ty, numbers::log2e);
auto Mul = B.buildFMul(Ty, X, Log2E, Flags);
if (Ty == LLT::scalar(32)) { if (Ty == F32) {
B.buildIntrinsic(Intrinsic::amdgcn_exp2, ArrayRef<Register>{Dst}) B.buildIntrinsic(Intrinsic::amdgcn_exp2, ArrayRef<Register>{Dst})
.addUse(Mul.getReg(0)) .addUse(Mul.getReg(0))
.setMIFlags(Flags); .setMIFlags(Flags);
} else { } else {
B.buildFExp2(Dst, Mul.getReg(0), Flags); B.buildFExp2(Dst, Mul.getReg(0), Flags);
} }
return true; return true;
} }
auto Threshold = B.buildFConstant(Ty, -0x1.5d58a0p+6f);
auto NeedsScaling =
B.buildFCmp(CmpInst::FCMP_OLT, LLT::scalar(1), X, Threshold, Flags);
auto ScaleOffset = B.buildFConstant(Ty, 0x1.0p+6f);
auto ScaledX = B.buildFAdd(Ty, X, ScaleOffset, Flags);
auto AdjustedX = B.buildSelect(Ty, NeedsScaling, ScaledX, X, Flags);
auto Log2E = B.buildFConstant(Ty, numbers::log2e);
auto ExpInput = B.buildFMul(Ty, AdjustedX, Log2E, Flags);
auto Exp2 = B.buildIntrinsic(Intrinsic::amdgcn_exp2, {Ty})
.addUse(ExpInput.getReg(0))
.setMIFlags(Flags);
auto ResultScaleFactor = B.buildFConstant(Ty, 0x1.969d48p-93f);
auto AdjustedResult = B.buildFMul(Ty, Exp2, ResultScaleFactor, Flags);
B.buildSelect(Dst, NeedsScaling, AdjustedResult, Exp2, Flags);
return true;
}
bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI, bool AMDGPULegalizerInfo::legalizeFExp(MachineInstr &MI,
MachineIRBuilder &B) const { MachineIRBuilder &B) const {
Register Dst = MI.getOperand(0).getReg(); Register Dst = MI.getOperand(0).getReg();
Register X = MI.getOperand(1).getReg(); Register X = MI.getOperand(1).getReg();
const unsigned Flags = MI.getFlags(); const unsigned Flags = MI.getFlags();
MachineFunction &MF = B.getMF(); MachineFunction &MF = B.getMF();
MachineRegisterInfo &MRI = *B.getMRI(); MachineRegisterInfo &MRI = *B.getMRI();
LLT Ty = MRI.getType(Dst); LLT Ty = MRI.getType(Dst);
Show All 21 Lines if (Ty == F16) {
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
assert(Ty == F32); assert(Ty == F32);
// TODO: Interpret allowApproxFunc as ignoring DAZ. This is currently copying // TODO: Interpret allowApproxFunc as ignoring DAZ. This is currently copying
// library behavior. Also, is known-not-daz source sufficient? // library behavior. Also, is known-not-daz source sufficient?
if (allowApproxFunc(MF, Flags) && !needsDenormHandlingF32(MF, X, Flags)) { if (allowApproxFunc(MF, Flags)) {
legalizeFExpUnsafe(B, Dst, X, Flags); legalizeFExpUnsafe(B, Dst, X, Flags);
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
// Algorithm: // Algorithm:
// //
// e^x = 2^(x/ln(2)) = 2^(x*(64/ln(2))/64) // e^x = 2^(x/ln(2)) = 2^(x*(64/ln(2))/64)
▲ Show 20 Lines • Show All 3,468 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.exp.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,206 Lines • ▼ Show 20 Lines
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%fneg = fneg float %in %fneg = fneg float %in
%result = call float @llvm.exp.f32(float %fneg) %result = call float @llvm.exp.f32(float %fneg)
ret float %result ret float %result
} }
define float @v_exp_f32_fast(float %in) { define float @v_exp_f32_fast(float %in) {
; VI-SDAG-LABEL: v_exp_f32_fast: ; GCN-SDAG-LABEL: v_exp_f32_fast:
; VI-SDAG: ; %bb.0: ; GCN-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 ; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 ; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_fast:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_fast:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_fast: ; GCN-GISEL-LABEL: v_exp_f32_fast:
; GFX900-GISEL: ; %bb.0: ; GCN-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_fast: ; SI-SDAG-LABEL: v_exp_f32_fast:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_fast: ; SI-GISEL-LABEL: v_exp_f32_fast:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_fast: ; R600-LABEL: v_exp_f32_fast:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_exp_f32_fast: ; CM-LABEL: v_exp_f32_fast:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call fast float @llvm.exp.f32(float %in) %result = call fast float @llvm.exp.f32(float %in)
ret float %result ret float %result
} }
define float @v_exp_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" { define float @v_exp_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
; VI-SDAG-LABEL: v_exp_f32_unsafe_math_attr: ; GCN-SDAG-LABEL: v_exp_f32_unsafe_math_attr:
; VI-SDAG: ; %bb.0: ; GCN-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 ; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 ; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_unsafe_math_attr:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_unsafe_math_attr:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2
; GFX900-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v2, v3, v2
; GFX900-SDAG-NEXT: v_exp_f32_e32 v2, v2
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v2, v1
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_unsafe_math_attr: ; GCN-GISEL-LABEL: v_exp_f32_unsafe_math_attr:
; GFX900-GISEL: ; %bb.0: ; GCN-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v1, v1 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX900-GISEL-NEXT: v_exp_f32_e32 v2, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v2, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_unsafe_math_attr: ; SI-SDAG-LABEL: v_exp_f32_unsafe_math_attr:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s5, 0x32a5705f ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s5, v2 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_exp_f32_e32 v2, v2
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v2, v1
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_unsafe_math_attr: ; SI-GISEL-LABEL: v_exp_f32_unsafe_math_attr:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: v_rndne_f32_e32 v1, v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_fma_f32 v3, v0, s4, -v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-GISEL-NEXT: v_add_f32_e32 v2, v3, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v1
; SI-GISEL-NEXT: v_exp_f32_e32 v2, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v2, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_unsafe_math_attr: ; R600-LABEL: v_exp_f32_unsafe_math_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_exp_f32_unsafe_math_attr: ; CM-LABEL: v_exp_f32_unsafe_math_attr:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call float @llvm.exp.f32(float %in) %result = call float @llvm.exp.f32(float %in)
ret float %result ret float %result
} }
define float @v_exp_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" { define float @v_exp_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
; VI-SDAG-LABEL: v_exp_f32_approx_fn_attr: ; GCN-SDAG-LABEL: v_exp_f32_approx_fn_attr:
; VI-SDAG: ; %bb.0: ; GCN-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 ; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 ; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_approx_fn_attr:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_approx_fn_attr:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_approx_fn_attr: ; GCN-GISEL-LABEL: v_exp_f32_approx_fn_attr:
; GFX900-GISEL: ; %bb.0: ; GCN-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_approx_fn_attr: ; SI-SDAG-LABEL: v_exp_f32_approx_fn_attr:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_approx_fn_attr: ; SI-GISEL-LABEL: v_exp_f32_approx_fn_attr:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_approx_fn_attr: ; R600-LABEL: v_exp_f32_approx_fn_attr:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_exp_f32_approx_fn_attr: ; CM-LABEL: v_exp_f32_approx_fn_attr:
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Lines
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call ninf float @llvm.exp.f32(float %in) %result = call ninf float @llvm.exp.f32(float %in)
ret float %result ret float %result
} }
define float @v_exp_f32_afn(float %in) { define float @v_exp_f32_afn(float %in) {
; VI-SDAG-LABEL: v_exp_f32_afn: ; GCN-SDAG-LABEL: v_exp_f32_afn:
; VI-SDAG: ; %bb.0: ; GCN-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 ; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 ; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_afn:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_afn: ; GCN-GISEL-LABEL: v_exp_f32_afn:
; GFX900-GISEL: ; %bb.0: ; GCN-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_afn: ; SI-SDAG-LABEL: v_exp_f32_afn:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_afn: ; SI-GISEL-LABEL: v_exp_f32_afn:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_afn: ; R600-LABEL: v_exp_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_exp_f32_afn: ; CM-LABEL: v_exp_f32_afn:
Show All 28 Lines
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.exp.f32(float %in) %result = call afn float @llvm.exp.f32(float %in)
ret float %result ret float %result
} }
define float @v_exp_f32_afn_dynamic(float %in) #1 { define float @v_exp_f32_afn_dynamic(float %in) #1 {
; VI-SDAG-LABEL: v_exp_f32_afn_dynamic: ; GCN-SDAG-LABEL: v_exp_f32_afn_dynamic:
; VI-SDAG: ; %bb.0: ; GCN-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v0 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; VI-SDAG-NEXT: v_sub_f32_e32 v4, v0, v1 ; GCN-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1 ; GCN-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 ; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_afn_dynamic:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v0
; VI-GISEL-NEXT: v_sub_f32_e32 v2, v0, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_afn_dynamic:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_exp_f32_afn_dynamic: ; GCN-GISEL-LABEL: v_exp_f32_afn_dynamic:
; GFX900-GISEL: ; %bb.0: ; GCN-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; GCN-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; GCN-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_afn_dynamic: ; SI-SDAG-LABEL: v_exp_f32_afn_dynamic:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, -v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_fma_f32 v1, v0, s4, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_nlt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_afn_dynamic: ; SI-GISEL-LABEL: v_exp_f32_afn_dynamic:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-GISEL-NEXT: v_add_f32_e32 v2, 0x42800000, v0
; SI-GISEL-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: v_fma_f32 v2, v0, v3, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, v0, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_exp_f32_afn_dynamic: ; R600-LABEL: v_exp_f32_afn_dynamic:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_exp_f32_afn_dynamic: ; CM-LABEL: v_exp_f32_afn_dynamic:
; CM: ; %bb.0: ; CM: ; %bb.0:
; CM-NEXT: CF_END ; CM-NEXT: CF_END
; CM-NEXT: PAD ; CM-NEXT: PAD
%result = call afn float @llvm.exp.f32(float %in) %result = call afn float @llvm.exp.f32(float %in)
ret float %result ret float %result
} }
define float @v_fabs_exp_f32_afn(float %in) { define float @v_fabs_exp_f32_afn(float %in) {
; VI-SDAG-LABEL: v_fabs_exp_f32_afn: ; GCN-SDAG-LABEL: v_fabs_exp_f32_afn:
; VI-SDAG: ; %bb.0: ; GCN-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0 ; GCN-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; VI-SDAG-NEXT: v_and_b32_e32 v1, 0xfffff000, v1 ; GCN-SDAG-NEXT: s_mov_b32 s5, 0x42800000
; VI-SDAG-NEXT: v_sub_f32_e64 v4, |v0|, v1 ; GCN-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5
; VI-SDAG-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v1 ; GCN-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; VI-SDAG-NEXT: v_mul_f32_e32 v5, 0x39a3b295, v4 ; GCN-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
; VI-SDAG-NEXT: v_mul_f32_e32 v4, 0x3fb8a000, v4 ; GCN-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; VI-SDAG-NEXT: v_rndne_f32_e32 v3, v2 ; GCN-SDAG-NEXT: v_exp_f32_e32 v0, v0
; VI-SDAG-NEXT: v_add_f32_e32 v4, v4, v5 ; GCN-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; VI-SDAG-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1 ; GCN-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; VI-SDAG-NEXT: v_sub_f32_e32 v2, v2, v3 ; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
; VI-SDAG-NEXT: v_add_f32_e32 v1, v1, v4
; VI-SDAG-NEXT: v_add_f32_e32 v1, v2, v1
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; VI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
; VI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; VI-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
; VI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_fabs_exp_f32_afn:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xfffff000, v1
; VI-GISEL-NEXT: v_sub_f32_e64 v2, |v0|, v1
; VI-GISEL-NEXT: v_mul_f32_e32 v4, 0x39a3b295, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0x3fb8a000, v2
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3fb8a000, v1
; VI-GISEL-NEXT: v_add_f32_e32 v2, v2, v4
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0x39a3b295, v1
; VI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v3
; VI-GISEL-NEXT: v_sub_f32_e32 v3, v3, v2
; VI-GISEL-NEXT: v_add_f32_e32 v1, v3, v1
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; VI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_fabs_exp_f32_afn:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2
; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v1
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v1, v3, v1
; GFX900-SDAG-NEXT: v_exp_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; GFX900-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; GFX900-SDAG-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-GISEL-LABEL: v_fabs_exp_f32_afn: ; GCN-GISEL-LABEL: v_fabs_exp_f32_afn:
; GFX900-GISEL: ; %bb.0: ; GCN-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; GCN-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; GFX900-GISEL-NEXT: v_mul_f32_e64 v1, |v0|, s4 ; GCN-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
; GFX900-GISEL-NEXT: v_fma_f32 v2, |v0|, s4, -v1 ; GCN-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; GCN-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; GFX900-GISEL-NEXT: v_fma_f32 v2, |v0|, v3, v2 ; GCN-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; GCN-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; GCN-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; GCN-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 ; GCN-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX900-GISEL-NEXT: v_exp_f32_e32 v1, v1 ; GCN-GISEL-NEXT: s_setpc_b64 s[30:31]
; GFX900-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v1, v1, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_fabs_exp_f32_afn: ; SI-SDAG-LABEL: v_fabs_exp_f32_afn:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: v_mul_f32_e64 v1, |v0|, s4 ; SI-SDAG-NEXT: s_mov_b32 s5, 0x42800000
; SI-SDAG-NEXT: v_rndne_f32_e32 v2, v1 ; SI-SDAG-NEXT: v_add_f32_e64 v1, |v0|, s5
; SI-SDAG-NEXT: v_sub_f32_e32 v3, v1, v2 ; SI-SDAG-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, -v1 ; SI-SDAG-NEXT: v_cndmask_b32_e64 v0, |v0|, v1, vcc
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v1, |v0|, s4, v1 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_add_f32_e32 v1, v3, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v2
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_nlt_f32_e64 vcc, |v0|, s4
; SI-SDAG-NEXT: s_mov_b32 s4, 0x42b17218
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-SDAG-NEXT: v_cmp_ngt_f32_e64 vcc, |v0|, s4
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_fabs_exp_f32_afn: ; SI-GISEL-LABEL: v_fabs_exp_f32_afn:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2aeac50
; SI-GISEL-NEXT: v_mul_f32_e64 v1, |v0|, s4 ; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
; SI-GISEL-NEXT: v_fma_f32 v2, |v0|, s4, -v1 ; SI-GISEL-NEXT: v_add_f32_e64 v2, |v0|, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x32a5705f ; SI-GISEL-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, v1
; SI-GISEL-NEXT: v_fma_f32 v2, |v0|, v3, v2 ; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, |v0|, v2, vcc
; SI-GISEL-NEXT: v_rndne_f32_e32 v3, v1 ; SI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v3 ; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_add_f32_e32 v1, v1, v2 ; SI-GISEL-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v2, v3 ; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-GISEL-NEXT: v_exp_f32_e32 v1, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v3, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, v2
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5]
; SI-GISEL-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, v2
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31] ; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; R600-LABEL: v_fabs_exp_f32_afn: ; R600-LABEL: v_fabs_exp_f32_afn:
; R600: ; %bb.0: ; R600: ; %bb.0:
; R600-NEXT: CF_END ; R600-NEXT: CF_END
; R600-NEXT: PAD ; R600-NEXT: PAD
; ;
; CM-LABEL: v_fabs_exp_f32_afn: ; CM-LABEL: v_fabs_exp_f32_afn:
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; GCN-NEXT: v_exp_f32_e32 v0, v0 ; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_fast: ; SI-SDAG-LABEL: v_exp_f32_from_fpext_math_f16_fast:
; SI-SDAG: ; %bb.0: ; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-SDAG-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-SDAG-NEXT: s_mov_b32 s4, 0x3fb8aa3b ; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2aeac50
; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1 ; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v1
; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x3fb8aa3b, v0 ; SI-SDAG-NEXT: v_add_f32_e32 v1, 0x42800000, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, -v1 ; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: s_mov_b32 s4, 0x32a5705f ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_rndne_f32_e32 v3, v1 ; SI-SDAG-NEXT: v_mul_f32_e32 v0, 0x3fb8aa3b, v0
; SI-SDAG-NEXT: v_fma_f32 v2, v0, s4, v2 ; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_sub_f32_e32 v1, v1, v3 ; SI-SDAG-NEXT: v_mul_f32_e32 v1, 0x114b4ea4, v0
; SI-SDAG-NEXT: v_add_f32_e32 v1, v1, v2 ; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; SI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v2, v3
; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2ce8ed0
; SI-SDAG-NEXT: v_cmp_ngt_f32_e32 vcc, s4, v0
; SI-SDAG-NEXT: v_ldexp_f32_e32 v1, v1, v2
; SI-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; SI-SDAG-NEXT: s_setpc_b64 s[30:31] ; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; ;
; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_fast: ; SI-GISEL-LABEL: v_exp_f32_from_fpext_math_f16_fast:
; SI-GISEL: ; %bb.0: ; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-GISEL-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1 ; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
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