[lldb][AArch64] Add tests for SME's SVE register state to TestArm64DynamicRegsets

[DavidSpickett]

Summary

SME reuses SVE's register state but adds new modes to it. Therefore
we can't check all those in the same test as the existing SVE
checks.

SME's ZA, SVG and SVCR register checks will be added to this test
in later patches.

Prior to this we didn't have any testing of writing streaming mode
SVE registers from lldb, only writing SVE registers in normal
(non-streaming) SVE mode.

[DavidSpickett]

ping!

[omjavaid]

Can you add more description to this patch. at the moment reading it without SME context in mind does not provide enough information to figure out what we are doing.

[DavidSpickett]

Rebase

[DavidSpickett]

Did my best to update the commit message.

[DavidSpickett]

Rebase

[omjavaid]

In this test can we figure out whether SVE was read from Streaming mode or normal SVE mode?? and if yes may be add a check for that.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

156

can we use self.thread().GetSelectedFrame().GetRegisters() ?? or are you going to use target process thread and current frame variables in later patches?

[DavidSpickett]

In this test can we figure out whether SVE was read from Streaming mode or normal SVE mode?? and if yes may be add a check for that.

Not sure what you mean.

If you mean:

• write non-streaming SVE with one set of values
• write streaming SVE with another
• assert that lldb read the correct one

There are a couple of issues there:

• If lldb read the inactive mode, it would fail with unavailable register due to a failure down in lldb-sever. These tests would already catch that.
• The kernel and the architecture say that the values of the registers for the mode you are coming from are wiped out on mode switch. So we wouldn't be able to truly read those values even if we were able to make the ptrace call and get some data.

So it's covered, but does not/ can not be covered by checking values. It'll be correct values, or a complete failure to read.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

156

No I just copied this from the original test, in fact later I wrap this all into a function.

[DavidSpickett]

Use the simpler way to get the register sets.

[omjavaid]

In D157846#4644241, @DavidSpickett wrote:

In this test can we figure out whether SVE was read from Streaming mode or normal SVE mode?? and if yes may be add a check for that.

Not sure what you mean.

If you mean:

• write non-streaming SVE with one set of values
• write streaming SVE with another
• assert that lldb read the correct one

There are a couple of issues there:

• If lldb read the inactive mode, it would fail with unavailable register due to a failure down in lldb-sever. These tests would already catch that.
• The kernel and the architecture say that the values of the registers for the mode you are coming from are wiped out on mode switch. So we wouldn't be able to truly read those values even if we were able to make the ptrace call and get some data.

So it's covered, but does not/ can not be covered by checking values. It'll be correct values, or a complete failure to read.

Thanks for the detailed clarification.

I was actually curious if LLDB user can distinguish whether we are reading SVE registers from streaming mode or normal SVE mode. But yes only config registers like vg can tell that registers are read in non-SVE(FPSIMD), normal SVE, or streaming modes.

[DavidSpickett]

I was actually curious if LLDB user can distinguish whether we are reading SVE registers from streaming mode or normal SVE mode. But yes only config registers like vg can tell that registers are read in non-SVE(FPSIMD), normal SVE, or streaming modes.

Right, good point and yes they can but not until https://reviews.llvm.org/D154927. In that I also update the tests to check that svcr has the correct value for the expected mode the test is running in.

They'll be able to check SVCR.SM (bit 0) to know if they are in streaming mode (which will eventually be nicely printed M = 1 but that's unrelated to this series).

They can also see if SVG and VG match, but vector lengths can overlap so this won't always work, so SVCR is the official way to do it.

lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py

def test_aarch64_dynamic_regset_config(self):
                 )
             if "Pointer Authentication Registers" in registerSet.GetName():
                 self.assertTrue(
                     self.isAArch64PAuth(),
                     "LLDB enabled AArch64 Pointer Authentication register set when it was disabled by target.",
                 )
                 self.expect("register read data_mask", substrs=["data_mask = 0x"])
                 self.expect("register read code_mask", substrs=["code_mask = 0x"])
+
+    @no_debug_info_test
+    @skipIf(archs=no_match(["aarch64"]))
+    @skipIf(oslist=no_match(["linux"]))
+    def test_aarch64_dynamic_regset_config_sme(self):
+        """Test AArch64 Dynamic Register sets configuration, but only SME
+           registers."""
+        if not self.isAArch64SME():
+            self.skipTest("SME must be present.")
+
+        self.build()
+        self.line = line_number("main.c", "// Set a break point here.")
+
+        exe = self.getBuildArtifact("a.out")
+        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+        lldbutil.run_break_set_by_file_and_line(
+            self, "main.c", self.line, num_expected_locations=1
+        )
+        self.runCmd("settings set target.run-args sme")
+        self.runCmd("run", RUN_SUCCEEDED)
+
+        self.expect(
+            "thread backtrace",
+            STOPPED_DUE_TO_BREAKPOINT,
+            substrs=["stop reason = breakpoint 1."],
+        )
+
+        target = self.dbg.GetSelectedTarget()
+        process = target.GetProcess()
+        thread = process.GetThreadAtIndex(0)
+        currentFrame = thread.GetFrameAtIndex(0)
+
+        register_sets = currentFrame.GetRegisters()
+
+        ssve_registers = register_sets.GetFirstValueByName(
+            "Scalable Vector Extension Registers")
+        self.assertTrue(ssve_registers.IsValid())
+        self.sve_regs_read_dynamic(ssve_registers)

lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c

 #include <sys/auxv.h>
 
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
 void set_sve_registers() {
   // AArch64 SVE extension ISA adds a new set of vector and predicate registers:
   // 32 Z registers, 16 P registers, and 1 FFR register.
   // Code below populates SVE registers to be read back by the debugger via
   // ptrace interface at runtime.
   // The P registers are predicate registers and hold one bit for each byte
   // available in a Z vector register. For example, an SVE implementation with
   // 1024-bit Z registers has 128-bit predicate registers.
void set_sve_registers() {
   asm volatile("cpy  z26.b, p10/z, #27\n\t");
   asm volatile("cpy  z27.b, p15/z, #28\n\t");
   asm volatile("cpy  z28.b, p0/z, #29\n\t");
   asm volatile("cpy  z29.b, p5/z, #30\n\t");
   asm volatile("cpy  z30.b, p10/z, #31\n\t");
   asm volatile("cpy  z31.b, p15/z, #32\n\t");
 }
 
-int main() {
-  if (getauxval(AT_HWCAP) & HWCAP_SVE) // check if SVE is present
+int main(int argc, char *argv[]) {
+  if (argc > 1) {
+    // Enable streaming mode SVE and the ZA array storage.
+    asm volatile("msr  s0_3_c4_c7_3, xzr" /*smstart*/);
+  }
+
+  // If we have SVE or SME, set the SVE registers.
+  if ((getauxval(AT_HWCAP) & HWCAP_SVE) || (getauxval(AT_HWCAP2) & HWCAP2_SME))
     set_sve_registers();
 
   return 0; // Set a break point here.
 }