This is an archive of the discontinued LLVM Phabricator instance.

Differential D157677

[RISCV][GISel] Narrow G_SEXT_INREG to XLenLLT before lowering.
ClosedPublic

Authored by craig.topper on Aug 10 2023, 10:41 PM.

Details

Reviewers
nitinjohnraj
arsenm
Commits
rG9cf375b3101f: [RISCV][GISel] Narrow G_SEXT_INREG to XLenLLT before lowering.
Summary

If we lower, we need to legalize the wide shifts which
is costly.

This will improve the tests from https://reviews.llvm.org/D157415 too

Diff Detail

Event Timeline

craig.topper created this revision.Aug 10 2023, 10:41 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2023, 10:41 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
craig.topper requested review of this revision.Aug 10 2023, 10:42 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2023, 10:42 PM
Herald added subscribers: wangpc, eopXD, MaskRay, wdng. · View Herald Transcript
craig.topper edited the summary of this revision. (Show Details)Aug 10 2023, 10:42 PM
Harbormaster completed remote builds in B251848: Diff 549248.Aug 11 2023, 1:04 AM
arsenm accepted this revision.Aug 14 2023, 2:25 PM
This revision is now accepted and ready to land.Aug 14 2023, 2:25 PM
Closed by commit rG9cf375b3101f: [RISCV][GISel] Narrow G_SEXT_INREG to XLenLLT before lowering. (authored by craig.topper). · Explain WhyAug 14 2023, 2:56 PM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG9cf375b3101f: [RISCV][GISel] Narrow G_SEXT_INREG to XLenLLT before lowering..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
GISel/
5 lines
test/
CodeGen/
RISCV/
GlobalISel/
legalizer/
rv32/
152 lines
rv64/
152 lines

Diff 550100

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Show First 20 Lines • Show All 62 Lines • ▼ Show 20 Lines if (SrcSize < 8 || !isPowerOf2_32(SrcSize))
return false; return false;
return true; return true;
}; };
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
.legalIf(ExtLegalFunc) .legalIf(ExtLegalFunc)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder(G_SEXT_INREG).legalFor({XLenLLT}).lower(); getActionDefinitionsBuilder(G_SEXT_INREG)
.legalFor({XLenLLT})
.maxScalar(0, XLenLLT)
.lower();
// Merge/Unmerge // Merge/Unmerge
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) { for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1; unsigned BigTyIdx = Op == G_MERGE_VALUES ? 0 : 1;
unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0; unsigned LitTyIdx = Op == G_MERGE_VALUES ? 1 : 0;
getActionDefinitionsBuilder(Op) getActionDefinitionsBuilder(Op)
.widenScalarToNextPow2(LitTyIdx, XLen) .widenScalarToNextPow2(LitTyIdx, XLen)
.widenScalarToNextPow2(BigTyIdx, XLen) .widenScalarToNextPow2(BigTyIdx, XLen)
Show All 32 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-icmp.mir

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
name: cmp_sgt_i48 name: cmp_sgt_i48
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sgt_i48 ; CHECK-LABEL: name: cmp_sgt_i48
; CHECK: %xhi:_(s32) = COPY $x10 ; CHECK: %xhi:_(s32) = COPY $x10
; CHECK-NEXT: %xlo:_(s32) = COPY $x11 ; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12 ; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13 ; CHECK-NEXT: %ylo:_(s32) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), %xhi(s32), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[OR1]](s32), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10 %xhi:_(s32) = COPY $x10
%xlo:_(s32) = COPY $x11 %xlo:_(s32) = COPY $x11
%yhi:_(s32) = COPY $x12 %yhi:_(s32) = COPY $x12
%ylo:_(s32) = COPY $x13 %ylo:_(s32) = COPY $x13
%x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32)
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
name: cmp_slt_i48 name: cmp_slt_i48
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_slt_i48 ; CHECK-LABEL: name: cmp_slt_i48
; CHECK: %xhi:_(s32) = COPY $x10 ; CHECK: %xhi:_(s32) = COPY $x10
; CHECK-NEXT: %xlo:_(s32) = COPY $x11 ; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12 ; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13 ; CHECK-NEXT: %ylo:_(s32) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), %xhi(s32), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[OR1]](s32), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10 %xhi:_(s32) = COPY $x10
%xlo:_(s32) = COPY $x11 %xlo:_(s32) = COPY $x11
%yhi:_(s32) = COPY $x12 %yhi:_(s32) = COPY $x12
%ylo:_(s32) = COPY $x13 %ylo:_(s32) = COPY $x13
%x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32)
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
name: cmp_sge_i48 name: cmp_sge_i48
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sge_i48 ; CHECK-LABEL: name: cmp_sge_i48
; CHECK: %xhi:_(s32) = COPY $x10 ; CHECK: %xhi:_(s32) = COPY $x10
; CHECK-NEXT: %xlo:_(s32) = COPY $x11 ; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12 ; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13 ; CHECK-NEXT: %ylo:_(s32) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), %xhi(s32), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sge), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(uge), [[OR1]](s32), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10 %xhi:_(s32) = COPY $x10
%xlo:_(s32) = COPY $x11 %xlo:_(s32) = COPY $x11
%yhi:_(s32) = COPY $x12 %yhi:_(s32) = COPY $x12
%ylo:_(s32) = COPY $x13 %ylo:_(s32) = COPY $x13
%x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32)
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
name: cmp_sle_i48 name: cmp_sle_i48
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sle_i48 ; CHECK-LABEL: name: cmp_sle_i48
; CHECK: %xhi:_(s32) = COPY $x10 ; CHECK: %xhi:_(s32) = COPY $x10
; CHECK-NEXT: %xlo:_(s32) = COPY $x11 ; CHECK-NEXT: %xlo:_(s32) = COPY $x11
; CHECK-NEXT: %yhi:_(s32) = COPY $x12 ; CHECK-NEXT: %yhi:_(s32) = COPY $x12
; CHECK-NEXT: %ylo:_(s32) = COPY $x13 ; CHECK-NEXT: %ylo:_(s32) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG %xlo, 16
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL %xhi, [[C]](s32) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG %ylo, 16
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL %xlo, [[C1]](s32) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), %xhi(s32), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR %xhi, [[C2]](s32) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[SHL]], [[C3]](s32)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C4]](s32)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[OR]], [[C3]](s32)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s32) = G_SHL %yhi, [[C5]](s32)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s32) = G_SHL %ylo, [[C6]](s32)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR %yhi, [[C7]](s32)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[SHL3]], [[C8]](s32)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[OR2]], [[C9]](s32)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s32) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[OR2]], [[C8]](s32)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sle), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ASHR]](s32), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(ule), [[OR1]](s32), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s32) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s32) = COPY $x10 %xhi:_(s32) = COPY $x10
%xlo:_(s32) = COPY $x11 %xlo:_(s32) = COPY $x11
%yhi:_(s32) = COPY $x12 %yhi:_(s32) = COPY $x12
%ylo:_(s32) = COPY $x13 %ylo:_(s32) = COPY $x13
%x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32) %x0:_(s64) = G_MERGE_VALUES %xhi(s32), %xlo(s32)
▲ Show 20 Lines • Show All 982 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-icmp.mir

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
name: cmp_sgt_i72 name: cmp_sgt_i72
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sgt_i72 ; CHECK-LABEL: name: cmp_sgt_i72
; CHECK: %xhi:_(s64) = COPY $x10 ; CHECK: %xhi:_(s64) = COPY $x10
; CHECK-NEXT: %xlo:_(s64) = COPY $x11 ; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12 ; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13 ; CHECK-NEXT: %ylo:_(s64) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %xlo, 8
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %ylo, 8
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C1]](s64) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), %xhi(s64), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %xhi, [[C2]](s64) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[C3]](s64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C4]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C3]](s64)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C5]](s64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C6]](s64)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %yhi, [[C7]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[SHL3]], [[C8]](s64)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C9]](s64)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[OR2]], [[C8]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sgt), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ugt), [[OR1]](s64), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10 %xhi:_(s64) = COPY $x10
%xlo:_(s64) = COPY $x11 %xlo:_(s64) = COPY $x11
%yhi:_(s64) = COPY $x12 %yhi:_(s64) = COPY $x12
%ylo:_(s64) = COPY $x13 %ylo:_(s64) = COPY $x13
%x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64)
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
name: cmp_slt_i72 name: cmp_slt_i72
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_slt_i72 ; CHECK-LABEL: name: cmp_slt_i72
; CHECK: %xhi:_(s64) = COPY $x10 ; CHECK: %xhi:_(s64) = COPY $x10
; CHECK-NEXT: %xlo:_(s64) = COPY $x11 ; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12 ; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13 ; CHECK-NEXT: %ylo:_(s64) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %xlo, 8
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %ylo, 8
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C1]](s64) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %xhi, [[C2]](s64) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[C3]](s64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C4]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C3]](s64)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C5]](s64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C6]](s64)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %yhi, [[C7]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[SHL3]], [[C8]](s64)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C9]](s64)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[OR2]], [[C8]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[OR1]](s64), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10 %xhi:_(s64) = COPY $x10
%xlo:_(s64) = COPY $x11 %xlo:_(s64) = COPY $x11
%yhi:_(s64) = COPY $x12 %yhi:_(s64) = COPY $x12
%ylo:_(s64) = COPY $x13 %ylo:_(s64) = COPY $x13
%x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64)
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
name: cmp_sge_i72 name: cmp_sge_i72
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sge_i72 ; CHECK-LABEL: name: cmp_sge_i72
; CHECK: %xhi:_(s64) = COPY $x10 ; CHECK: %xhi:_(s64) = COPY $x10
; CHECK-NEXT: %xlo:_(s64) = COPY $x11 ; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12 ; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13 ; CHECK-NEXT: %ylo:_(s64) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %xlo, 8
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %ylo, 8
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C1]](s64) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), %xhi(s64), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %xhi, [[C2]](s64) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[C3]](s64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C4]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C3]](s64)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C5]](s64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C6]](s64)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %yhi, [[C7]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[SHL3]], [[C8]](s64)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C9]](s64)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[OR2]], [[C8]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sge), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(uge), [[OR1]](s64), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10 %xhi:_(s64) = COPY $x10
%xlo:_(s64) = COPY $x11 %xlo:_(s64) = COPY $x11
%yhi:_(s64) = COPY $x12 %yhi:_(s64) = COPY $x12
%ylo:_(s64) = COPY $x13 %ylo:_(s64) = COPY $x13
%x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64)
▲ Show 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
name: cmp_sle_i72 name: cmp_sle_i72
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: cmp_sle_i72 ; CHECK-LABEL: name: cmp_sle_i72
; CHECK: %xhi:_(s64) = COPY $x10 ; CHECK: %xhi:_(s64) = COPY $x10
; CHECK-NEXT: %xlo:_(s64) = COPY $x11 ; CHECK-NEXT: %xlo:_(s64) = COPY $x11
; CHECK-NEXT: %yhi:_(s64) = COPY $x12 ; CHECK-NEXT: %yhi:_(s64) = COPY $x12
; CHECK-NEXT: %ylo:_(s64) = COPY $x13 ; CHECK-NEXT: %ylo:_(s64) = COPY $x13
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG %xlo, 8
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL %xhi, [[C]](s64) ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG %ylo, 8
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 56 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL %xlo, [[C1]](s64) ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), %xhi(s64), %yhi
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR %xhi, [[C2]](s64) ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[LSHR]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C]]
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR1:%[0-9]+]]:_(s64) = G_LSHR [[SHL]], [[C3]](s64)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL2:%[0-9]+]]:_(s64) = G_SHL [[OR]], [[C4]](s64)
; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[LSHR1]], [[SHL2]]
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[OR]], [[C3]](s64)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL3:%[0-9]+]]:_(s64) = G_SHL %yhi, [[C5]](s64)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[SHL4:%[0-9]+]]:_(s64) = G_SHL %ylo, [[C6]](s64)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[LSHR2:%[0-9]+]]:_(s64) = G_LSHR %yhi, [[C7]](s64)
; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[SHL4]], [[LSHR2]]
; CHECK-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 56
; CHECK-NEXT: [[LSHR3:%[0-9]+]]:_(s64) = G_LSHR [[SHL3]], [[C8]](s64)
; CHECK-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[SHL5:%[0-9]+]]:_(s64) = G_SHL [[OR2]], [[C9]](s64)
; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[LSHR3]], [[SHL5]]
; CHECK-NEXT: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[OR2]], [[C8]](s64)
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(sle), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s64) = G_ICMP intpred(eq), [[ASHR]](s64), [[ASHR1]]
; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s64) = G_ICMP intpred(ule), [[OR1]](s64), [[OR3]]
; CHECK-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[ICMP1]], [[C10]]
; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]] ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[AND]](s64), [[ICMP2]], [[ICMP]]
; CHECK-NEXT: $x10 = COPY [[SELECT]](s64) ; CHECK-NEXT: $x10 = COPY [[SELECT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%xhi:_(s64) = COPY $x10 %xhi:_(s64) = COPY $x10
%xlo:_(s64) = COPY $x11 %xlo:_(s64) = COPY $x11
%yhi:_(s64) = COPY $x12 %yhi:_(s64) = COPY $x12
%ylo:_(s64) = COPY $x13 %ylo:_(s64) = COPY $x13
%x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64) %x0:_(s128) = G_MERGE_VALUES %xhi(s64), %xlo(s64)
▲ Show 20 Lines • Show All 1,126 Lines • Show Last 20 Lines