[Thumb1] Use callee-saved register to adjust stack pointer

[keith.walker.arm]

Summary

When adjusting the Stack Pointer at the end of the function epilogue,
use a callee-saved register, rather than explicitly using R4 which may
not have been saved.

[olista01]

Do you have a test case for the situation where r4 is not saved?

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

552

Please add an assertion to check that ScratchRegister has been set to something.

[keith.walker.arm]

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

552

I'll simplify the assert in the branch which adjusts SP using FP.
The other uses of the ScratchRegister in emitPrologueEpilogueSPUpdate(() already has an assert if the ScratchRegister is used.

[keith.walker.arm]

Amended on os the asserts to make the test now match what is being set as the scratch register.

I tried to come up with a suitable additional test which didn't involve the code actually saving R4. I do have a C reproducer but it is quite a number of "fuzzed" c code and trying to turn it into a sensible IR/MIR regression test proved problematic. Also I believe that we have sufficient tests in place to ensure that the scratch register we now used is one of the callee saved registers, thus the additional test is not really required.

[keith.walker.arm]

No additional asserts were needed to be added as all cases where ScratchRegister is used (including in the function emitPrologueEpilogueSPUpdate()) aleady has asserts in place.

[olista01]

LGTM

llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

if (!AFI->hasStackFrame()) {
 
     // Move SP to start of FP callee save spill area.
     NumBytes -= (AFI->getFrameRecordSavedAreaSize() +
                  AFI->getGPRCalleeSavedArea1Size() +
                  AFI->getGPRCalleeSavedArea2Size() +
                  AFI->getDPRCalleeSavedAreaSize() +
                  ArgRegsSaveSize);
 
+    // We are likely to need a scratch register and we know all callee-save
+    // registers are free at this point in the epilogue, so pick one.
+    unsigned ScratchRegister = ARM::NoRegister;
+    bool HasFP = hasFP(MF);
+    for (auto &I : MFI.getCalleeSavedInfo()) {
+      Register Reg = I.getReg();
+      if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
+        ScratchRegister = Reg;
+        break;
+      }
+    }
+
     if (AFI->shouldRestoreSPFromFP()) {
       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
       // Reset SP based on frame pointer only if the stack frame extends beyond
       // frame pointer stack slot, the target is ELF and the function has FP, or
       // the target uses var sized objects.
       if (NumBytes) {
-        assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
+        assert(ScratchRegister != ARM::NoRegister &&
                "No scratch register to restore SP from FP!");
-        emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
+        emitThumbRegPlusImmediate(MBB, MBBI, dl, ScratchRegister, FramePtr, -NumBytes,
                                   TII, *RegInfo, MachineInstr::FrameDestroy);
         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
-            .addReg(ARM::R4)
+            .addReg(ScratchRegister)
             .add(predOps(ARMCC::AL))
             .setMIFlag(MachineInstr::FrameDestroy);
       } else
         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
             .addReg(FramePtr)
             .add(predOps(ARMCC::AL))
             .setMIFlag(MachineInstr::FrameDestroy);
     } else {
-      // For a large stack frame, we might need a scratch register to store
-      // the size of the frame.  We know all callee-save registers are free
-      // at this point in the epilogue, so pick one.
-      unsigned ScratchRegister = ARM::NoRegister;
-      bool HasFP = hasFP(MF);
-      for (auto &I : MFI.getCalleeSavedInfo()) {
-        Register Reg = I.getReg();
-        if (isARMLowRegister(Reg) && !(HasFP && Reg == FramePtr)) {
-          ScratchRegister = Reg;
-          break;
-        }
-      }
       if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
           &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
         MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
         if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
           emitPrologueEpilogueSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes,
                                        ScratchRegister, MachineInstr::FrameDestroy);
       } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
         emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes,

llvm/test/CodeGen/ARM/cmse.ll

 ; CHECK-8B-NEXT:    add r7, sp, #8
 ; CHECK-8B-NEXT:    sub sp, #16
 ; CHECK-8B-NEXT:    mov r4, sp
 ; CHECK-8B-NEXT:    lsrs r4, r4, #4
 ; CHECK-8B-NEXT:    lsls r4, r4, #4
 ; CHECK-8B-NEXT:    mov sp, r4
 ; CHECK-8B-NEXT:    mov r0, sp
 ; CHECK-8B-NEXT:    bl func51
-; CHECK-8B-NEXT:    subs r4, r7, #7
-; CHECK-8B-NEXT:    subs r4, #1
-; CHECK-8B-NEXT:    mov sp, r4
+; CHECK-8B-NEXT:    subs r6, r7, #7
+; CHECK-8B-NEXT:    subs r6, #1
+; CHECK-8B-NEXT:    mov sp, r6
 ; CHECK-8B-NEXT:    pop {r4, r6, r7}
 ; CHECK-8B-NEXT:    pop {r0}
 ; CHECK-8B-NEXT:    mov lr, r0
 ; CHECK-8B-NEXT:    mov r0, lr
 ; CHECK-8B-NEXT:    mov r1, lr
 ; CHECK-8B-NEXT:    mov r2, lr
 ; CHECK-8B-NEXT:    mov r3, lr
 ; CHECK-8B-NEXT:    mov r12, lr

llvm/test/CodeGen/ARM/thumb1-varalloc.ll

   
 bb2:
   %5 = call ptr @strdup(ptr %2) nounwind
   store ptr %5, ptr @__baz, align 4
   br label %bb3
   
 bb3:
   %.0 = phi ptr [ %0, %entry ], [ %5, %bb2 ], [ %2, %bb1 ]
-; CHECK:      subs    r4, r7, #7
-; CHECK-NEXT: subs    r4, #1
-; CHECK-NEXT: mov     sp, r4
+; CHECK:      subs    r6, r7, #7
+; CHECK-NEXT: subs    r6, #1
+; CHECK-NEXT: mov     sp, r6
 ; CHECK-NEXT: pop     {r4, r6, r7, pc}
   ret ptr %.0
 }
 
 declare noalias ptr @strdup(ptr nocapture) nounwind
 declare i32 @_called_func(ptr, ptr) nounwind
 
 ; Simple variable ending up *at* sp.

llvm/test/CodeGen/Thumb/2011-EpilogueBug.ll

 ; RUN: llc -mtriple=thumbv6-apple-darwin < %s | FileCheck %s
 ; r8869722
 
 %struct.state = type { i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, ptr }
 %struct.info = type { i32, i32, i32, i32, i32, i32, i32, ptr }
 
 define void @t1(ptr %v) {
-; CHECK: push {r4
   %tmp6 = load i32, ptr null
   %tmp8 = alloca float, i32 %tmp6
   store i32 1, ptr null
   br label %return
 
 return:                                           ; preds = %0
-; CHECK: mov sp, r4
+; CHECK: subs [[SCRATCH:r[0-7]]], r7, #7
+; CHECK: subs [[SCRATCH]], #1
+; CHECK: mov sp, [[SCRATCH]]
+; CHECK-NEXT: pop
+; CHECK-SAME: [[SCRATCH]]
   ret void
 }

llvm/test/CodeGen/Thumb/callee_save.ll

 ; CHECK-NEXT:    subs r0, r1, r0
 ; CHECK-NEXT:    mov sp, r0
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    movs r0, #1
 ; CHECK-NEXT:    movs r1, #2
 ; CHECK-NEXT:    movs r2, #3
 ; CHECK-NEXT:    movs r3, #4
-; CHECK-NEXT:    subs r4, r7, #7
-; CHECK-NEXT:    subs r4, #9
-; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    subs r6, r7, #7
+; CHECK-NEXT:    subs r6, #9
+; CHECK-NEXT:    mov sp, r6
 ; CHECK-NEXT:    pop {r4, r6}
 ; CHECK-NEXT:    mov r8, r4
 ; CHECK-NEXT:    mov r9, r6
 ; CHECK-NEXT:    pop {r4, r6, r7, pc}
 entry:
   %b = alloca i32, i32 %a
   call void asm sideeffect "", "r,~{r8},~{r9}"(ptr %b)
   %vecinit = insertelement <4 x i32> undef, i32 1, i32 0
   %vecinit11 = insertelement <4 x i32> %vecinit, i32 2, i32 1
   %vecinit12 = insertelement <4 x i32> %vecinit11, i32 3, i32 2
   %vecinit13 = insertelement <4 x i32> %vecinit12, i32 4, i32 3
   ret <4 x i32> %vecinit13
 }

llvm/test/CodeGen/Thumb/emergency-spill-slot.ll

 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    str r0, [r6]
 ; CHECK-NEXT:    ldr r0, .LCPI0_1
 ; CHECK-NEXT:    str r5, [r0, r6]
 ; CHECK-NEXT:    ldr r0, [r6]
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    subs r4, r7, #7
-; CHECK-NEXT:    subs r4, #5
-; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    subs r6, r7, #7
+; CHECK-NEXT:    subs r6, #5
+; CHECK-NEXT:    mov sp, r6
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI0_0:
 ; CHECK-NEXT:    .long 4294963196 @ 0xffffeffc
 ; CHECK-NEXT:  .LCPI0_1:
 ; CHECK-NEXT:    .long 1024 @ 0x400
 entry:

 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    str r0, [sp]
 ; CHECK-NEXT:    ldr r0, .LCPI5_0
 ; CHECK-NEXT:    str r5, [r0, r7]
 ; CHECK-NEXT:    ldr r0, [sp]
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    subs r4, r7, #7
-; CHECK-NEXT:    subs r4, #5
-; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    subs r6, r7, #7
+; CHECK-NEXT:    subs r6, #5
+; CHECK-NEXT:    mov sp, r6
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  @ %bb.1:
 ; CHECK-NEXT:  .LCPI5_0:
 ; CHECK-NEXT:    .long 128 @ 0x80
 entry:
   %y = alloca [4 x i32], align 16
   %asm1 = call { i32, i32, i32, i32, i32, i32, i32 } asm "", "={r0},={r1},={r2},={r3},={r4},={r5},={r6},0,1,2,3,4,5,6"(ptr %y, ptr %p, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef) #3

 ; CHECK-NEXT:    mov r0, sp
 ; CHECK-NEXT:    adds r1, r7, #7
 ; CHECK-NEXT:    adds r1, #1
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    str r5, [r7, #124]
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    subs r4, r7, #7
-; CHECK-NEXT:    subs r4, #5
-; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    subs r6, r7, #7
+; CHECK-NEXT:    subs r6, #5
+; CHECK-NEXT:    mov sp, r6
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 entry:
   %y = alloca [4 x i32], align 16
   %asm1 = call { i32, i32, i32, i32, i32, i32, i32 } asm "", "={r0},={r1},={r2},={r3},={r4},={r5},={r6},0,1,2,3,4,5,6"(ptr %y, ptr %p, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef) #3
   %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 0
   %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 1
   %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 2
   %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 3

 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
 ; CHECK-NEXT:    str r0, [sp, #8] @ 4-byte Spill
 ; CHECK-NEXT:    ldr r0, [sp, #12] @ 4-byte Reload
 ; CHECK-NEXT:    str r5, [r0, #120]
 ; CHECK-NEXT:    ldr r0, [sp, #8] @ 4-byte Reload
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    subs r4, r7, #7
-; CHECK-NEXT:    subs r4, #5
-; CHECK-NEXT:    mov sp, r4
+; CHECK-NEXT:    subs r6, r7, #7
+; CHECK-NEXT:    subs r6, #5
+; CHECK-NEXT:    mov sp, r6
 ; CHECK-NEXT:    pop {r4, r5, r6, r7, pc}
 entry:
   %y = alloca [4 x i32], align 16
   %asm1 = call { i32, i32, i32, i32, i32, i32, i32 } asm "", "={r0},={r1},={r2},={r3},={r4},={r5},={r6},0,1,2,3,4,5,6"(ptr %y, ptr %p, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef) #3
   %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 0
   %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 1
   %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 2
   %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 3
   %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 4
   %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 5
   %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32 } %asm1, 6
   %arrayidx = getelementptr inbounds i32, ptr %p, i32 30
   store i32 %asmresult6, ptr %arrayidx, align 4
   call void asm sideeffect "", "{r0},{r1},{r2},{r3},{r4},{r5},{r6}"(i32 %asmresult, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7)
   ret void
 }

llvm/test/CodeGen/Thumb/frame-chain.ll

 ; FP-NEXT:    movs r3, #7
 ; FP-NEXT:    bics r1, r3
 ; FP-NEXT:    mov r3, sp
 ; FP-NEXT:    subs r1, r3, r1
 ; FP-NEXT:    mov sp, r1
 ; FP-NEXT:    movs r1, #0
 ; FP-NEXT:    str r1, [r6, #4]
 ; FP-NEXT:    str r0, [r2]
-; FP-NEXT:    subs r4, r7, #7
-; FP-NEXT:    subs r4, #1
-; FP-NEXT:    mov sp, r4
+; FP-NEXT:    subs r6, r7, #7
+; FP-NEXT:    subs r6, #1
+; FP-NEXT:    mov sp, r6
 ; FP-NEXT:    pop {r4, r6, r7, pc}
 ;
 ; FP-AAPCS-LABEL: required_fp:
 ; FP-AAPCS:       @ %bb.0:
 ; FP-AAPCS-NEXT:    .save {lr}
 ; FP-AAPCS-NEXT:    push {lr}
 ; FP-AAPCS-NEXT:    mov lr, r11
 ; FP-AAPCS-NEXT:    .save {r11}

 ; FP-AAPCS-NEXT:    movs r3, #7
 ; FP-AAPCS-NEXT:    bics r1, r3
 ; FP-AAPCS-NEXT:    mov r3, sp
 ; FP-AAPCS-NEXT:    subs r1, r3, r1
 ; FP-AAPCS-NEXT:    mov sp, r1
 ; FP-AAPCS-NEXT:    movs r1, #0
 ; FP-AAPCS-NEXT:    str r1, [r6, #4]
 ; FP-AAPCS-NEXT:    str r0, [r2]
-; FP-AAPCS-NEXT:    mov r4, r11
-; FP-AAPCS-NEXT:    subs r4, #8
-; FP-AAPCS-NEXT:    mov sp, r4
+; FP-AAPCS-NEXT:    mov r6, r11
+; FP-AAPCS-NEXT:    subs r6, #8
+; FP-AAPCS-NEXT:    mov sp, r6
 ; FP-AAPCS-NEXT:    pop {r4, r6}
 ; FP-AAPCS-NEXT:    pop {r0}
 ; FP-AAPCS-NEXT:    mov r11, r0
 ; FP-AAPCS-NEXT:    pop {pc}
 ;
 ; NOFP-LABEL: required_fp:
 ; NOFP:       @ %bb.0:
 ; NOFP-NEXT:    .save {r4, r6, r7, lr}

 ; NOFP-NEXT:    movs r3, #7
 ; NOFP-NEXT:    bics r1, r3
 ; NOFP-NEXT:    mov r3, sp
 ; NOFP-NEXT:    subs r1, r3, r1
 ; NOFP-NEXT:    mov sp, r1
 ; NOFP-NEXT:    movs r1, #0
 ; NOFP-NEXT:    str r1, [r6, #4]
 ; NOFP-NEXT:    str r0, [r2]
-; NOFP-NEXT:    subs r4, r7, #7
-; NOFP-NEXT:    subs r4, #1
-; NOFP-NEXT:    mov sp, r4
+; NOFP-NEXT:    subs r6, r7, #7
+; NOFP-NEXT:    subs r6, #1
+; NOFP-NEXT:    mov sp, r6
 ; NOFP-NEXT:    pop {r4, r6, r7, pc}
 ;
 ; NOFP-AAPCS-LABEL: required_fp:
 ; NOFP-AAPCS:       @ %bb.0:
 ; NOFP-AAPCS-NEXT:    .save {lr}
 ; NOFP-AAPCS-NEXT:    push {lr}
 ; NOFP-AAPCS-NEXT:    mov lr, r11
 ; NOFP-AAPCS-NEXT:    .save {r11}

 ; NOFP-AAPCS-NEXT:    movs r3, #7
 ; NOFP-AAPCS-NEXT:    bics r1, r3
 ; NOFP-AAPCS-NEXT:    mov r3, sp
 ; NOFP-AAPCS-NEXT:    subs r1, r3, r1
 ; NOFP-AAPCS-NEXT:    mov sp, r1
 ; NOFP-AAPCS-NEXT:    movs r1, #0
 ; NOFP-AAPCS-NEXT:    str r1, [r6, #4]
 ; NOFP-AAPCS-NEXT:    str r0, [r2]
-; NOFP-AAPCS-NEXT:    mov r4, r11
-; NOFP-AAPCS-NEXT:    subs r4, #8
-; NOFP-AAPCS-NEXT:    mov sp, r4
+; NOFP-AAPCS-NEXT:    mov r6, r11
+; NOFP-AAPCS-NEXT:    subs r6, #8
+; NOFP-AAPCS-NEXT:    mov sp, r6
 ; NOFP-AAPCS-NEXT:    pop {r4, r6}
 ; NOFP-AAPCS-NEXT:    pop {r0}
 ; NOFP-AAPCS-NEXT:    mov r11, r0
 ; NOFP-AAPCS-NEXT:    pop {pc}
   %3 = alloca i32, align 4
   %4 = alloca i32, align 4
   %5 = alloca ptr, align 8
   %6 = alloca i64, align 8

llvm/test/CodeGen/Thumb/large-stack.ll

 }
 
 ; Largest stack for which three tADDspi/tSUBspis are enough
 define void @test100_nofpelim() "frame-pointer"="all" {
 ; CHECK-LABEL: test100_nofpelim{{>?}}:
 ; CHECK: sub sp, #508
 ; CHECK: sub sp, #508
 ; CHECK: sub sp, #508
-; CHECK: subs r4, r7, #7
-; CHECK: subs r4, #1
-; CHECK: mov sp, r4
+; CHECK: subs [[SCRATCH:r[0-7]]], r7, #7
+; CHECK: subs [[SCRATCH]], #1
+; CHECK: mov sp, [[SCRATCH]]
+; CHECK: pop
+; CHECK-SAME: [[SCRATCH]]
     %tmp = alloca [ 1524 x i8 ] , align 4
     ret void
 }
 
 ; Smallest stack for which we use a constant pool
 define void @test2() {
 ; CHECK-LABEL: test2{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
     %tmp = alloca [ 1528 x i8 ] , align 4
     ret void
 }
 
 ; Smallest stack for which we use a constant pool
 define void @test2_nofpelim() "frame-pointer"="all" {
 ; CHECK-LABEL: test2_nofpelim{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
-; CHECK: subs r4, r7, #7
-; CHECK: subs r4, #1
-; CHECK: mov sp, r4
+; CHECK: subs [[SCRATCH:r[0-7]]], r7, #7
+; CHECK: subs [[SCRATCH]], #1
+; CHECK: mov sp, [[SCRATCH]]
+; CHECK: pop
+; CHECK-SAME: [[SCRATCH]]
     %tmp = alloca [ 1528 x i8 ] , align 4
     ret void
 }
 
 define i32 @test3() {
 ; CHECK-LABEL: test3{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]

 }
 
 define i32 @test3_nofpelim() "frame-pointer"="all" {
 ; CHECK-LABEL: test3_nofpelim{{>?}}:
 ; CHECK: ldr [[TEMP:r[0-7]]],
 ; CHECK: add sp, [[TEMP]]
 ; CHECK: ldr [[TEMP2:r[0-7]]],
 ; CHECK: add [[TEMP2]], sp
-; CHECK: subs r4, r7,
-; CHECK: mov sp, r4
+; CHECK: subs [[SCRATCH:r[0-7]]], r7,
+; CHECK: mov sp, [[SCRATCH]]
+; CHECK: pop
+; CHECK-SAME: [[SCRATCH]]
     %retval = alloca i32, align 4
     %tmp = alloca i32, align 4
     %a = alloca [805306369 x i8], align 8
     store i32 0, ptr %tmp
     %tmp1 = load i32, ptr %tmp
     ret i32 %tmp1
 }