[ARM] Permit VGETLNi32 and VSETLNi32 without mnemonic suffix.

[simon_tatham]

Summary

These instructions transfer 32 bits of data between an integer
register and half of a d-register. Currently LLVM accepts them only
with the syntax vmov.32 r0, d0[0] or vmov.32 d0[0], r0. But the
ARMARM says that the .32 suffix on the mnemonic should be optional.

Added a pair of NEONInstAlias to accept the bare vmov version, and
checked that the result is the same as with .32.

This only adds new syntax accepted in assembly. The existing explicit
version is still used when disassembling these instructions.

[dmgreen]

LGTM

[simon_tatham]

Correction: using NEONInstAlias was a mistake because it meant the
aliases had stricter requirements than the instructions they map to.
The revised version of the patch gives each alias the same
requirements as its base instruction. For example, these aliases are
now accepted in thumbv7m as well as armv8a.

I'm a bit worried to find that those requirements are different,
though. VSETLNi32 simply requires HasVFP2, whereas VGETLNi32
requires both HasFPRegs and HasFastVGETLNi32. I would have thought
that the matching get and set operations ought to be enabled by the
same feature! And surely HasFastVGETLNi32 only ought to be
conditionalizing the selection of VGETLNi32 during compilation,
and shouldn't also make it illegal to write by hand in assembler.

But those are probably things to fix in a separate patch.

[simon_tatham]

Further correction: in this version I had to explicitly set EmitPriority or several tests failed.

[dmgreen]

For example, these aliases are now accepted in thumbv7m as well as armv8a.

Ah I see. The v8.1-m reference I had looked at didn't have the same optional instruction suffix. IIRC we don't use VGETLNi32 for MVE, it goes via MVE_VMOV_from_lane_32 instead, and the D reg variant is an alias of the Q reg version (and doesn't mark the size as optional in the same way). They do look like they were there in v7m though.

[simon_tatham]

Even better idea: instead of repeating the list of predicates in each InstAlias, I can just import them by pulling out the Predicates field of the instruction record that each one expands to. Then if we do fix the VGETLNi32/VSETLNi32 mismatch later, the aliases will automatically pick up the same change without anyone having to remember to fix it in two places.

(I don't know why InstAlias doesn't do this automatically, now I think about it!)

[dmgreen]

I didn't even know that was possible. It still sounds good to me.

llvm/lib/Target/ARM/ARMInstrNEON.td

 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
                           (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
                           IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
                           [(set GPR:$R, (extractelt (v2i32 DPR:$V),
                                            imm:$lane))]>,
                 Requires<[HasFPRegs, HasFastVGETLNi32]> {
   let Inst{21} = lane{0};
 }
+// VGETLNi32 is also legal as just vmov r0,d0[0] without the .32 suffix
+def : InstAlias<"vmov${p} $R, $V$lane",
+    (VGETLNi32 GPR:$R, DPR:$V, VectorIndex32:$lane, pred:$p), 0>,
+    Requires<VGETLNi32.Predicates>;
 let Predicates = [HasNEON] in {
 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
 def : Pat<(ARMvgetlanes (v16i8 QPR:$src), imm:$lane),
           (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
                            (DSubReg_i8_reg imm:$lane))),
                      (SubReg_i8_lane imm:$lane))>;
 def : Pat<(ARMvgetlanes (v8i16 QPR:$src), imm:$lane),
           (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
                                            GPR:$R, imm:$lane))]>,
                 Requires<[HasVFP2]> {
   let Inst{21} = lane{0};
   // This instruction is equivalent as
   // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm)
   let isInsertSubreg = 1;
 }
 }
+// VSETLNi32 is also legal as just vmov d0[0],r0 without the .32 suffix
+def : InstAlias<"vmov${p} $V$lane, $R",
+    (VSETLNi32 DPR:$V, GPR:$R, VectorIndex32:$lane, pred:$p), 0>,
+    Requires<VSETLNi32.Predicates>;
 
 // TODO: for odd lanes we could optimize this a bit by using the VINS
 // FullFP16 instruction when it is available
 multiclass InsertEltF16<ValueType VTScalar, ValueType VT4, ValueType VT8> {
   def : Pat<(insertelt (VT4 DPR:$src1), (VTScalar HPR:$src2), imm:$lane),
             (VT4 (VSETLNi16 DPR:$src1,
                  (COPY_TO_REGCLASS HPR:$src2, GPR), imm:$lane))>;
   def : Pat<(insertelt (VT8 QPR:$src1), (VTScalar HPR:$src2), imm:$lane),

llvm/test/MC/ARM/neon-mov-encoding.s

 @ CHECK: vqmovun.s32  d16, q8         @ encoding: [0x60,0x02,0xf6,0xf3]
 @ CHECK: vqmovun.s64  d16, q8         @ encoding: [0x60,0x02,0xfa,0xf3]
 
   vmov.s8   r0, d16[1]
   vmov.s16  r0, d16[1]
   vmov.u8   r0, d16[1]
   vmov.u16  r0, d16[1]
   vmov.32   r0, d16[1]
+  vmov      r0, d16[1]
   vmov.8  d16[1], r1
   vmov.16 d16[1], r1
   vmov.32 d16[1], r1
   vmov.8  d18[1], r1
   vmov.16 d18[1], r1
   vmov.32 d18[1], r1
+  vmov    d18[1], r1
 
 @ CHECK: vmov.s8  r0, d16[1]      @ encoding: [0xb0,0x0b,0x50,0xee]
 @ CHECK: vmov.s16  r0, d16[1]      @ encoding: [0xf0,0x0b,0x10,0xee]
 @ CHECK: vmov.u8  r0, d16[1]      @ encoding: [0xb0,0x0b,0xd0,0xee]
 @ CHECK: vmov.u16  r0, d16[1]      @ encoding: [0xf0,0x0b,0x90,0xee]
 @ CHECK: vmov.32  r0, d16[1]      @ encoding: [0x90,0x0b,0x30,0xee]
+@ CHECK: vmov.32  r0, d16[1]      @ encoding: [0x90,0x0b,0x30,0xee]
 @ CHECK: vmov.8  d16[1], r1              @ encoding: [0xb0,0x1b,0x40,0xee]
 @ CHECK: vmov.16  d16[1], r1      @ encoding: [0xf0,0x1b,0x00,0xee]
 @ CHECK: vmov.32  d16[1], r1      @ encoding: [0x90,0x1b,0x20,0xee]
 @ CHECK: vmov.8  d18[1], r1              @ encoding: [0xb0,0x1b,0x42,0xee]
 @ CHECK: vmov.16  d18[1], r1      @ encoding: [0xf0,0x1b,0x02,0xee]
 @ CHECK: vmov.32  d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
+@ CHECK: vmov.32  d18[1], r1      @ encoding: [0x90,0x1b,0x22,0xee]
 
 
         vmvn.8 d1, d2
         vmvn.16 d1, d2
         vmvn.32 d1, d2
         vmvn.64 d1, d2
         vmvn.i8 d1, d2
         vmvn.i16 d1, d2