[RISCV] Match ext + ext + srem + trunc to vrem.vv

[LWenH]

Summary

This patch match the SDNode pattern:" trunc (srem(sext, ext))" to vrem.vv. This could remove the extra "vsext" ,"vnsrl" and the "vsetvli" instructions in the case like "c[i] = a[i] % b[i]", where the element types in the array are all int8_t or int16_t at the same time.

For element types like uint8_t or uint16_t, the "zext + zext + urem + trunc" based redundant IR have been removed during the instCombine pass, this is because the urem operation won't lead to the overflowed in the LLVM. However, for signed types, the instCombine pass can not remove such patterns due to the potential for Undefined Behavior in LLVM IR. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this situation doesn't occur for i32. To address this, LLVM first signed extends the operands for srem to i32 to prevent the UB.

For RVV, such overflow operations are already defined by the specification and yield deterministic output for extreme inputs. For example, based on the spec, for the i8 type, -128 % -1 actually have 0 as the output result under the overflowed situation. Therefore, it would be able to match such pattern in the instruction selection phase for the rvv backend rather than removing them in the target-independent optimization passes like instCombine pass.

This patch only handle the sign_ext circumstances for srem. For more information about the C test cases compared with GCC, please see : https://gcc.godbolt.org/z/MWzE7WaT4

[Jim]

Could you have pre-commit test for easily showing the change of this patch?

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

2236 ↗

(On Diff #545603)

indents doesn't look similar with other pat definition.

[LWenH]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

2236 ↗

(On Diff #545603)

Sure, but I'm not quite familiar with such process of pre-commit test in LLVM, could you give me some hint about the pre-commit test here or how to do so?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

2236 ↗

(On Diff #545603)

Make a separate phabricator review with the new test cases. Update this patch to show how those tests are changed. Add the pre-commit patch as a parent of this patch.

[craig.topper]

It would be good if the description said why this can't be done before the instruction selection phase for signed.

[LWenH]

Address @craig.topper and @Jim 's comments. Update and add precommit test for this patch.

Actually, I think these signed operation can't be removed before the instruction selection phase. These signed extension and trunc operation pair in LLVM system is to prevent Undefined Behavior. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this won't happen for i32. So LLVM first extend this to i32 to prevent the UB. For the unsigned, such pattern can be able to removed during the instcombine pass, this is because the urem operation won't lead to the overflowed in LLVM. For RVV, such overflow operation has been defined in the spec and have the determined output. For example, base on the spec, for the i8 type, -128 % -1 actually have 0 as the output result. So, I'm thinking for the rvv backend, we can remove such pattern to shrink the codesize.

[craig.topper]

In D156685#4576001, @LWenH wrote:

Address @craig.topper and @Jim 's comments. Update and add precommit test for this patch.

Actually, I think these signed operation can't be removed before the instruction selection phase. These signed extension and trunc operation pair in LLVM system is to prevent Undefined Behavior. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this won't happen for i32. So LLVM first extend this to i32 to prevent the UB. For the unsigned, such pattern can be able to removed during the instcombine pass, this is because the urem operation won't lead to the overflowed in LLVM. For RVV, such overflow operation has been defined in the spec and have the determined output. For example, base on the spec, for the i8 type, -128 % -1 actually have 0 as the output result. So, I'm thinking for the rvv backend, we can remove such pattern to shrink the codesize.

I agree they can't be removed before the instruction selection phase. Can you explain this in the commit message so that it will be in the git log when this is committed?

[LWenH]

In D156685#4582348, @craig.topper wrote:

In D156685#4576001, @LWenH wrote:

Address @craig.topper and @Jim 's comments. Update and add precommit test for this patch.

Actually, I think these signed operation can't be removed before the instruction selection phase. These signed extension and trunc operation pair in LLVM system is to prevent Undefined Behavior. Taking an example, -128 % -1 will lead to the Undefined Behaviour(overflowed) under the i8 type in LLVM IR, but this won't happen for i32. So LLVM first extend this to i32 to prevent the UB. For the unsigned, such pattern can be able to removed during the instcombine pass, this is because the urem operation won't lead to the overflowed in LLVM. For RVV, such overflow operation has been defined in the spec and have the determined output. For example, base on the spec, for the i8 type, -128 % -1 actually have 0 as the output result. So, I'm thinking for the rvv backend, we can remove such pattern to shrink the codesize.

I agree they can't be removed before the instruction selection phase. Can you explain this in the commit message so that it will be in the git log when this is committed?

Address @craig.topper's comments, update patch description about matching this pattern in the instruction selection phase. Thank you for your suggestion and the help with submitting the precommit test!

[craig.topper]

LGTM

[LWenH]

@craig.topper I think I don't have the commit access for the remote repository, could you commit these patches for me? Thank you.

[craig.topper]

In D156685#4583440, @LWenH wrote:

@craig.topper I think I don't have the commit access for the remote repository, could you commit these patches for me? Thank you.

Sure. Can you give your name and email for the git log

[LWenH]

In D156685#4583452, @craig.topper wrote:

In D156685#4583440, @LWenH wrote:

@craig.topper I think I don't have the commit access for the remote repository, could you commit these patches for me? Thank you.

Sure. Can you give your name and email for the git log

Sure, here is my contact message, username: LWenH, email: [e-mail]. Thank you.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 }
 
 // 11.11. Vector Integer Divide Instructions
 defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU", isSEWAware=1>;
 defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV", isSEWAware=1>;
 defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU", isSEWAware=1>;
 defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM", isSEWAware=1>;
 
+foreach vtiTowti = AllWidenableIntVectors in {
+  defvar vti = vtiTowti.Vti;
+  defvar wti = vtiTowti.Wti;
+  let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                               GetVTypePredicates<wti>.Predicates) in {
+  def : Pat<
+    (vti.Vector 
+      (riscv_trunc_vector_vl
+        (srem (wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs1))),
+              (wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs2)))),
+        (vti.Mask true_mask), (XLenVT srcvalue))),
+      (!cast<Instruction>("PseudoVREM_VV_"#vti.LMul.MX#"_E"#!shl(1, vti.Log2SEW))
+        (vti.Vector (IMPLICIT_DEF)), 
+        vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
+  }
+}
+
 // 11.12. Vector Widening Integer Multiply Instructions
 defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, sext_oneuse,
                                    "PseudoVWMUL">;
 defm : VPatWidenBinarySDNode_VV_VX<mul, zext_oneuse, zext_oneuse,
                                    "PseudoVWMULU">;
 defm : VPatWidenBinarySDNode_VV_VX<mul, anyext_oneuse, anyext_oneuse,
                                    "PseudoVWMULU">;
 defm : VPatWidenBinarySDNode_VV_VX<mul, zext_oneuse, anyext_oneuse,

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc
 }
 
 define <vscale x 1 x i8> @vrem_vv_nxv1i8_sext_twice(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv1i8_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v8, v9
-; CHECK-NEXT:    vrem.vv v8, v10, v8
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
   %sext_vb = sext <vscale x 1 x i8> %vb to <vscale x 1 x i16>
   %vc_ext = srem <vscale x 1 x i16> %sext_va, %sext_vb
   %vc = trunc <vscale x 1 x i16> %vc_ext to <vscale x 1 x i8>
   ret <vscale x 1 x i8> %vc
 }
 
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc
 }
 
 define <vscale x 2 x i8> @vrem_vv_nxv2i8_sext_twice(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv2i8_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v8, v9
-; CHECK-NEXT:    vrem.vv v8, v10, v8
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf4, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
   %sext_vb = sext <vscale x 2 x i8> %vb to <vscale x 2 x i16>
   %vc_ext = srem <vscale x 2 x i16> %sext_va, %sext_vb
   %vc = trunc <vscale x 2 x i16> %vc_ext to <vscale x 2 x i8>
   ret <vscale x 2 x i8> %vc
 }
 
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc
 }
 
 define <vscale x 4 x i8> @vrem_vv_nxv4i8_sext_twice(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv4i8_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v8, v9
-; CHECK-NEXT:    vrem.vv v8, v10, v8
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf2, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8, mf2, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
   %sext_vb = sext <vscale x 4 x i8> %vb to <vscale x 4 x i16>
   %vc_ext = srem <vscale x 4 x i16> %sext_va, %sext_vb
   %vc = trunc <vscale x 4 x i16> %vc_ext to <vscale x 4 x i8>
   ret <vscale x 4 x i8> %vc
 }
 
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc
 }
 
 define <vscale x 8 x i8> @vrem_vv_nxv8i8_sext_twice(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv8i8_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v12, v9
-; CHECK-NEXT:    vrem.vv v10, v10, v12
-; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v10, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
   %sext_vb = sext <vscale x 8 x i8> %vb to <vscale x 8 x i16>
   %vc_ext = srem <vscale x 8 x i16> %sext_va, %sext_vb
   %vc = trunc <vscale x 8 x i16> %vc_ext to <vscale x 8 x i8>
   ret <vscale x 8 x i8> %vc
 }
 
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc
 }
 
 define <vscale x 16 x i8> @vrem_vv_nxv16i8_sext_twice(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv16i8_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
-; CHECK-NEXT:    vsext.vf2 v12, v8
-; CHECK-NEXT:    vsext.vf2 v16, v10
-; CHECK-NEXT:    vrem.vv v12, v12, v16
-; CHECK-NEXT:    vsetvli zero, zero, e8, m2, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8, m2, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v10
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
   %sext_vb = sext <vscale x 16 x i8> %vb to <vscale x 16 x i16>
   %vc_ext = srem <vscale x 16 x i16> %sext_va, %sext_vb
   %vc = trunc <vscale x 16 x i16> %vc_ext to <vscale x 16 x i8>
   ret <vscale x 16 x i8> %vc
 }
 
; CHECK-NEXT:    ret
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc
 }
 
 define <vscale x 32 x i8> @vrem_vv_nxv32i8_sext_twice(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv32i8_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
-; CHECK-NEXT:    vsext.vf2 v16, v8
-; CHECK-NEXT:    vsext.vf2 v24, v12
-; CHECK-NEXT:    vrem.vv v16, v16, v24
-; CHECK-NEXT:    vsetvli zero, zero, e8, m4, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e8, m4, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v12
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>
   %sext_vb = sext <vscale x 32 x i8> %vb to <vscale x 32 x i16>
   %vc_ext = srem <vscale x 32 x i16> %sext_va, %sext_vb
   %vc = trunc <vscale x 32 x i16> %vc_ext to <vscale x 32 x i8>
   ret <vscale x 32 x i8> %vc
 }
 
; RV64-NEXT:    ret
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
   ret <vscale x 1 x i16> %vc
 }
 
 define <vscale x 1 x i16> @vrem_vv_nxv1i16_sext_twice(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv1i16_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v8, v9
-; CHECK-NEXT:    vrem.vv v8, v10, v8
-; CHECK-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
   %sext_vb = sext <vscale x 1 x i16> %vb to <vscale x 1 x i32>
   %vc_ext = srem <vscale x 1 x i32> %sext_va, %sext_vb
   %vc = trunc <vscale x 1 x i32> %vc_ext to <vscale x 1 x i16>
   ret <vscale x 1 x i16> %vc
 }
 
; RV64-NEXT:    ret
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
   ret <vscale x 2 x i16> %vc
 }
 
 define <vscale x 2 x i16> @vrem_vv_nxv2i16_sext_twice(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv2i16_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v8, v9
-; CHECK-NEXT:    vrem.vv v8, v10, v8
-; CHECK-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v8, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
   %sext_vb = sext <vscale x 2 x i16> %vb to <vscale x 2 x i32>
   %vc_ext = srem <vscale x 2 x i32> %sext_va, %sext_vb
   %vc = trunc <vscale x 2 x i32> %vc_ext to <vscale x 2 x i16>
   ret <vscale x 2 x i16> %vc
 }
 
; RV64-NEXT:    ret
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
   ret <vscale x 4 x i16> %vc
 }
 
 define <vscale x 4 x i16> @vrem_vv_nxv4i16_sext_twice(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv4i16_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-NEXT:    vsext.vf2 v10, v8
-; CHECK-NEXT:    vsext.vf2 v12, v9
-; CHECK-NEXT:    vrem.vv v10, v10, v12
-; CHECK-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v10, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v9
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
   %sext_vb = sext <vscale x 4 x i16> %vb to <vscale x 4 x i32>
   %vc_ext = srem <vscale x 4 x i32> %sext_va, %sext_vb
   %vc = trunc <vscale x 4 x i32> %vc_ext to <vscale x 4 x i16>
   ret <vscale x 4 x i16> %vc
 }
 
; RV64-NEXT:    ret
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
   ret <vscale x 8 x i16> %vc
 }
 
 define <vscale x 8 x i16> @vrem_vv_nxv8i16_sext_twice(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv8i16_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-NEXT:    vsext.vf2 v12, v8
-; CHECK-NEXT:    vsext.vf2 v16, v10
-; CHECK-NEXT:    vrem.vv v12, v12, v16
-; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v12, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v10
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
   %sext_vb = sext <vscale x 8 x i16> %vb to <vscale x 8 x i32>
   %vc_ext = srem <vscale x 8 x i32> %sext_va, %sext_vb
   %vc = trunc <vscale x 8 x i32> %vc_ext to <vscale x 8 x i16>
   ret <vscale x 8 x i16> %vc
 }
 
; RV64-NEXT:    ret
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
   ret <vscale x 16 x i16> %vc
 }
 
 define <vscale x 16 x i16> @vrem_vv_nxv16i16_sext_twice(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv16i16_sext_twice:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT:    vsext.vf2 v16, v8
-; CHECK-NEXT:    vsext.vf2 v24, v12
-; CHECK-NEXT:    vrem.vv v16, v16, v24
-; CHECK-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
-; CHECK-NEXT:    vnsrl.wi v8, v16, 0
+; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT:    vrem.vv v8, v8, v12
 ; CHECK-NEXT:    ret
   %sext_va = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>
   %sext_vb = sext <vscale x 16 x i16> %vb to <vscale x 16 x i32>
   %vc_ext = srem <vscale x 16 x i32> %sext_va, %sext_vb
   %vc = trunc <vscale x 16 x i32> %vc_ext to <vscale x 16 x i16>
   ret <vscale x 16 x i16> %vc
 }