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Differential D156309

[AMDGPU] Precommit tests for D156308
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Authored by Pierre-vh on Jul 26 2023, 3:31 AM.

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Reviewers
arsenm
Commits
rG6a767fbc36a3: [AMDGPU] Precommit tests for D156308
Summary

Also includes another testcase that's unrelated, it's just a sanity check.

Diff Detail

Event Timeline

Pierre-vh created this revision.Jul 26 2023, 3:31 AM
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Pierre-vh requested review of this revision.Jul 26 2023, 3:31 AM
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Pierre-vh added a child revision: D156308: [AMDGPU] Fix PromoteAlloca Subvector Stores for Single Elements.Jul 26 2023, 3:31 AM
arsenm accepted this revision.Jul 26 2023, 3:50 AM
This revision is now accepted and ready to land.Jul 26 2023, 3:50 AM
This revision was landed with ongoing or failed builds.Jul 26 2023, 4:21 AM
Closed by commit rG6a767fbc36a3: [AMDGPU] Precommit tests for D156308 (authored by Pierre-vh). · Explain Why
This revision was automatically updated to reflect the committed changes.
Pierre-vh added a commit: rG6a767fbc36a3: [AMDGPU] Precommit tests for D156308.
Harbormaster completed remote builds in B248207: Diff 544287.Jul 26 2023, 8:08 AM

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
47 lines

Diff 544300

llvm/test/CodeGen/AMDGPU/promote-alloca-subvecs.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca -amdgpu-promote-alloca-to-vector-limit=512 < %s | FileCheck %s
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
define void @test_trivial_subvector(<2 x i64> %val.0, <2 x i64> %val.1) { define void @test_trivial_subvector(<2 x i64> %val.0, <2 x i64> %val.1) {
; CHECK-LABEL: define void @test_trivial_subvector ; CHECK-LABEL: define void @test_trivial_subvector
; CHECK-SAME: (<2 x i64> [[VAL_0:%.*]], <2 x i64> [[VAL_1:%.*]]) { ; CHECK-SAME: (<2 x i64> [[VAL_0:%.*]], <2 x i64> [[VAL_1:%.*]]) {
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[VAL_0]], i64 0 ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x i64> [[VAL_0]], i64 0
▲ Show 20 Lines • Show All 316 Lines • ▼ Show 20 Lines
; CHECK-NEXT: store <3 x i32> [[VAL]], ptr addrspace(5) [[STACK]], align 16 ; CHECK-NEXT: store <3 x i32> [[VAL]], ptr addrspace(5) [[STACK]], align 16
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%stack = alloca [4 x i64], align 4, addrspace(5) %stack = alloca [4 x i64], align 4, addrspace(5)
store <3 x i32> %val, ptr addrspace(5) %stack store <3 x i32> %val, ptr addrspace(5) %stack
ret void ret void
} }
define void @test_accessty_too_small(<2 x i16> %val) {
; CHECK-LABEL: define void @test_accessty_too_small
; CHECK-SAME: (<2 x i16> [[VAL:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[STACK:%.*]] = alloca [4 x i64], align 4, addrspace(5)
; CHECK-NEXT: store <2 x i16> [[VAL]], ptr addrspace(5) [[STACK]], align 4
; CHECK-NEXT: ret void
;
entry:
%stack = alloca [4 x i64], align 4, addrspace(5)
store <2 x i16> %val, ptr addrspace(5) %stack
ret void
}
define void @store_2xi32_into_double(double %foo) {
; CHECK-LABEL: define void @store_2xi32_into_double
; CHECK-SAME: (double [[FOO:%.*]]) {
; CHECK-NEXT: [[DUMMYUSER0:%.*]] = freeze double 0x5F0000005E
; CHECK-NEXT: [[DUMMYUSER1:%.*]] = freeze double undef
; CHECK-NEXT: [[DUMMYUSER2:%.*]] = freeze double undef
; CHECK-NEXT: [[DUMMYUSER3:%.*]] = freeze double undef
; CHECK-NEXT: ret void
;
%alloca = alloca [9 x double], align 8, addrspace(5)
store <2 x i32> <i32 94, i32 95>, ptr addrspace(5) %alloca, align 8
%load0 = load double, ptr addrspace(5) %alloca, align 8
%dummyuser0 = freeze double %load0
%idx4 = getelementptr inbounds [9 x double], ptr addrspace(5) %alloca, i32 0, i32 4
%idx5 = getelementptr inbounds [9 x double], ptr addrspace(5) %alloca, i32 0, i32 5
store <4 x i32> <i32 102, i32 103, i32 104, i32 105>, ptr addrspace(5) %idx4, align 8
%load1 = load double, ptr addrspace(5) %idx4, align 8
%dummyuser1 = freeze double %load1
%load2 = load double, ptr addrspace(5) %idx5, align 8
%dummyuser2 = freeze double %load2
%idx8 = getelementptr inbounds [9 x double], ptr addrspace(5) %alloca, i32 0, i32 8
store <2 x i32> <i32 110, i32 111>, ptr addrspace(5) %idx8, align 8
%load3 = load double, ptr addrspace(5) %idx8, align 8
%dummyuser3 = freeze double %load3
ret void
}