[TableGen][NFC] Refine obtaining qualified register class ids.

[craig.topper]

Is this NFC?

[kosarev]

Is this NFC?

Yes. Will update the commit message tomorrow to mention that.

[kosarev]

Update the commit message to mention the NFC nature of the patch.

[kosarev]

Ping.

[craig.topper]

LGTM

llvm/utils/TableGen/CodeGenRegisters.h

public:
     /// Generate register pressure set for this register class and any class
     /// synthesized from it.
     bool GeneratePressureSet;
 
     // Return the Record that defined this class, or NULL if the class was
     // created by TableGen.
     Record *getDef() const { return TheDef; }
 
+    std::string getNamespaceQualification() const;
     const std::string &getName() const { return Name; }
     std::string getQualifiedName() const;
+    std::string getIdName() const;
+    std::string getQualifiedIdName() const;
     ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; }
     unsigned getNumValueTypes() const { return VTs.size(); }
     bool hasType(const ValueTypeByHwMode &VT) const;
 
     const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const {
       if (VTNum < VTs.size())
         return VTs[VTNum];
       llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");

llvm/utils/TableGen/CodeGenRegisters.cpp

if (A->getMembers().size() > B->getMembers().size())
     return true;
   if (A->getMembers().size() < B->getMembers().size())
     return false;
 
   // Finally order by name as a tie breaker.
   return StringRef(A->getName()) < B->getName();
 }
 
+std::string CodeGenRegisterClass::getNamespaceQualification() const {
+  return Namespace.empty() ? "" : (Namespace + "::").str();
+}
+
 std::string CodeGenRegisterClass::getQualifiedName() const {
-  if (Namespace.empty())
-    return getName();
-  else
-    return (Namespace + "::" + getName()).str();
+  return getNamespaceQualification() + getName();
+}
+
+std::string CodeGenRegisterClass::getIdName() const {
+  return getName() + "RegClassID";
+}
+
+std::string CodeGenRegisterClass::getQualifiedIdName() const {
+  return getNamespaceQualification() + getIdName();
 }
 
 // Compute sub-classes of all register classes.
 // Assume the classes are ordered topologically.
 void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
   auto &RegClasses = RegBank.getRegClasses();
 
   // Visit backwards so sub-classes are seen first.

llvm/utils/TableGen/DAGISelMatcherGen.cpp

if (Def->isSubClassOf("RegisterOperand"))
       Def = Def->getValueAsDef("RegClass");
     if (Def->isSubClassOf("RegisterClass")) {
       // If the register class has an enum integer value greater than 127, the
       // encoding overflows the limit of 7 bits, which precludes the use of
       // StringIntegerMatcher. In this case, fallback to using IntegerMatcher.
       const CodeGenRegisterClass &RC =
           CGP.getTargetInfo().getRegisterClass(Def);
       if (RC.EnumValue <= 127) {
-        std::string Value = getQualifiedName(Def) + "RegClassID";
+        std::string Value = RC.getQualifiedIdName();
         AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
         ResultOps.push_back(NextRecordedOperandNo++);
       } else {
         AddMatcher(new EmitIntegerMatcher(RC.EnumValue, MVT::i32));
         ResultOps.push_back(NextRecordedOperandNo++);
       }
       return;
     }

llvm/utils/TableGen/GlobalISelMatchTable.cpp

 }
 
 void RegisterBankOperandMatcher::emitPredicateOpcodes(MatchTable &Table,
                                                       RuleMatcher &Rule) const {
   Table << MatchTable::Opcode("GIM_CheckRegBankForClass")
         << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
         << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
         << MatchTable::Comment("RC")
-        << MatchTable::NamedValue(RC.getQualifiedName() + "RegClassID")
+        << MatchTable::NamedValue(RC.getQualifiedIdName())
         << MatchTable::LineBreak;
 }
 
 //===- MBBOperandMatcher --------------------------------------------------===//
 
 void MBBOperandMatcher::emitPredicateOpcodes(MatchTable &Table,
                                              RuleMatcher &Rule) const {
   Table << MatchTable::Opcode("GIM_CheckIsMBB") << MatchTable::Comment("MI")

 
 //===- ConstrainOperandToRegClassAction -----------------------------------===//
 
 void ConstrainOperandToRegClassAction::emitActionOpcodes(
     MatchTable &Table, RuleMatcher &Rule) const {
   Table << MatchTable::Opcode("GIR_ConstrainOperandRC")
         << MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
         << MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
-        << MatchTable::NamedValue(RC.getQualifiedName() + "RegClassID")
+        << MatchTable::NamedValue(RC.getQualifiedIdName())
         << MatchTable::LineBreak;
 }
 
 //===- MakeTempRegisterAction ---------------------------------------------===//
 
 void MakeTempRegisterAction::emitActionOpcodes(MatchTable &Table,
                                                RuleMatcher &Rule) const {
   Table << MatchTable::Opcode("GIR_MakeTempReg")
         << MatchTable::Comment("TempRegID") << MatchTable::IntValue(TempRegID)
         << MatchTable::Comment("TypeID")
         << MatchTable::NamedValue(Ty.getCxxEnumValue())
         << MatchTable::LineBreak;
 }
 
 } // namespace gi
 } // namespace llvm

llvm/utils/TableGen/RegisterBankEmitter.cpp

for (const auto &Bank : Banks) {
     for (const auto &RC : Bank.register_classes())
       RCsGroupedByWord[RC->EnumValue / 32].push_back(RC);
 
     OS << "const uint32_t " << Bank.getCoverageArrayName() << "[] = {\n";
     unsigned LowestIdxInWord = 0;
     for (const auto &RCs : RCsGroupedByWord) {
       OS << "    // " << LowestIdxInWord << "-" << (LowestIdxInWord + 31) << "\n";
       for (const auto &RC : RCs) {
-        std::string QualifiedRegClassID =
-            (Twine(RC->Namespace) + "::" + RC->getName() + "RegClassID").str();
-        OS << "    (1u << (" << QualifiedRegClassID << " - "
+        OS << "    (1u << (" << RC->getQualifiedIdName() << " - "
            << LowestIdxInWord << ")) |\n";
       }
       OS << "    0,\n";
       LowestIdxInWord += 32;
     }
     OS << "};\n";
   }
   OS << "\n";

llvm/utils/TableGen/RegisterInfoEmitter.cpp

if (!RegisterClasses.empty()) {
     assert(RegisterClasses.size() <= 0xffff &&
            "Too many register classes to fit in tables");
 
     OS << "\n// Register classes\n\n";
     if (!Namespace.empty())
       OS << "namespace " << Namespace << " {\n";
     OS << "enum {\n";
     for (const auto &RC : RegisterClasses)
-      OS << "  " << RC.getName() << "RegClassID"
-         << " = " << RC.EnumValue << ",\n";
+      OS << "  " << RC.getIdName() << " = " << RC.EnumValue << ",\n";
     OS << "\n};\n";
     if (!Namespace.empty())
       OS << "} // end namespace " << Namespace << "\n\n";
   }
 
   const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
   // If the only definition is the default NoRegAltName, we don't need to
   // emit anything.
for (const auto &RC : RegisterClasses) {
     std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits";
     std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")";
     assert(isInt<8>(RC.CopyCost) && "Copy cost too large.");
     uint32_t RegSize = 0;
     if (RC.RSI.isSimple())
       RegSize = RC.RSI.getSimple().RegSize;
     OS << "  { " << RCName << ", " << RCBitsName << ", "
        << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
-       << ", " << RCBitsSize << ", " << RC.getQualifiedName() + "RegClassID"
-       << ", " << RegSize << ", " << RC.CopyCost << ", "
+       << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
+       << RegSize << ", " << RC.CopyCost << ", "
        << (RC.Allocatable ? "true" : "false") << " },\n";
   }
 
   OS << "};\n\n";
 
   EmitRegMappingTables(OS, Regs, false);
 
   // Emit Reg encoding table
if (!BaseClasses.empty()) {
         for (const CodeGenRegisterClass *RC : BaseClasses) {
           if (is_contained(RC->getMembers(), &Reg)) {
             BaseRC = RC;
             break;
           }
         }
 
         OS << "    "
-           << (BaseRC ? BaseRC->getQualifiedName() + "RegClassID"
-                      : "InvalidRegClassID")
+           << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID")
            << ",  // " << Reg.getName() << "\n";
       }
       OS << "  };\n\n"
             "  assert(Reg < ArrayRef(Mapping).size());\n"
             "  unsigned RCID = Mapping[Reg];\n"
             "  if (RCID == InvalidRegClassID)\n"
             "    return nullptr;\n"
             "  return RegisterClasses[RCID];\n"