[AArch64] Ignore instructions not supported by CPU in AArch64SVESchedPseudoTest

[sdesmalen]

Summary

When adding new Pseudos for instructions that are not supported
by the CPU for which the scheduler model is being tested, the test fails
if these pseudos are not covered by the regex's in the scheduling model.

Rather than failing, this test should check that the CPU supports the
original instruction modelled by the pseudo. If not, the pseudo is
not relevant to the scheduling model being tested.

[harviniriawan]

thank you :)

[dmgreen]

Can you check this works in a Release build? If so it looks OK to me.

(It would be good if we had a more supported way of always querying an opcode for whether it was legal. I've wanted to use the same thing in llvm-exegesis recently).

[sdesmalen]

In D156094#4528143, @dmgreen wrote:

Can you check this works in a Release build? If so it looks OK to me.

Thanks. I tried a Release build and it worked as expected.

(It would be good if we had a more supported way of always querying an opcode for whether it was legal. I've wanted to use the same thing in llvm-exegesis recently).

Yes, I kind of expected there to be an interface for this already. Given there wasn't I wondered if this use-case was actually more niche than I thought. Feel free to move this out into a separate utility function if you want to reuse it for llvm-exegesis.

llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp

 #include "AArch64InstrInfo.h"
 #include "AArch64Subtarget.h"
 #include "AArch64TargetMachine.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 #include "gtest/gtest.h"
 
 using namespace llvm;
 namespace {
 std::unique_ptr<LLVMTargetMachine> createTargetMachine(const std::string &CPU) {

 
 std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
   AArch64Subtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
                       std::string(TM->getTargetCPU()),
                       std::string(TM->getTargetFeatureString()), *TM, true);
   return std::make_unique<AArch64InstrInfo>(ST);
 }
 
+#define GET_COMPUTE_FEATURES
+#include "AArch64GenInstrInfo.inc"
+
+/// Returns true if the instruction is enabled under a feature that the
+/// CPU supports.
+static bool isInstructionSupportedByCPU(unsigned Opcode,
+                                        FeatureBitset Features) {
+  FeatureBitset AvailableFeatures =
+      llvm::AArch64_MC::computeAvailableFeatures(Features);
+  FeatureBitset RequiredFeatures =
+      llvm::AArch64_MC::computeRequiredFeatures(Opcode);
+  FeatureBitset MissingFeatures =
+      (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures;
+  return MissingFeatures.none();
+}
+
 void runSVEPseudoTestForCPU(const std::string &CPU) {
 
   std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine(CPU);
   ASSERT_TRUE(TM);
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
   ASSERT_TRUE(II);
 
   const MCSubtargetInfo *STI = TM->getMCSubtargetInfo();
   MCSchedModel SchedModel = STI->getSchedModel();
 
   for (unsigned i = 0; i < AArch64::INSTRUCTION_LIST_END; ++i) {
     // Check if instruction is in the pseudo table
     // i holds the opcode of the pseudo, OrigInstr holds the opcode of the
     // original instruction
     int OrigInstr = AArch64::getSVEPseudoMap(i);
     if (OrigInstr == -1)
       continue;
 
+    // Ignore any pseudos/instructions which may not be part of the scheduler
+    // model for the CPU we're testing. This avoids this test from failing when
+    // new instructions are added that are not yet covered by the scheduler
+    // model.
+    if (!isInstructionSupportedByCPU(OrigInstr, STI->getFeatureBits()))
+      continue;
+
     const MCInstrDesc &Desc = II->get(i);
     unsigned SCClass = Desc.getSchedClass();
     const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCClass);
 
     const MCInstrDesc &DescOrig = II->get(OrigInstr);
     unsigned SCClassOrig = DescOrig.getSchedClass();
     const MCSchedClassDesc *SCDescOrig =
         SchedModel.getSchedClassDesc(SCClassOrig);