[AIX][TLS] Account for local-exec accesses in XCOFFObjectWriter

[amyk]

Summary

This is a follow up to D149722 and aims to address https://github.com/llvm/llvm-project/issues/63885.
Local-exec accesses were not previously accounted for in XCOFFObjectWriter. Specifically, the R_TLS_LE
relocation was not previously handled, which lead to the incorrect value being written for the relocation target.
Within this patch, the value being written is set to the symbol's virtual address and extra relocation tests are added.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

183

Copy/paste error?

255–256

Missing the interesting 4 bytes of the encoded value.

258–259

Same comment.

261–262

To be consistent, same comment.

264–265

Same comment.

[amyk]

Update aix-tls-le-xcoff-reloc.ll to show the bytes of the encoded value that I originally missed, and also add the correct symbol name that I missed earlier.

[hubert.reinterpretcast]

Code change looks good.
For each test:

• Noted the symbol table index for the referenced symbols of each R_TLS_LE relocation.
• Checked that the values encoded "at" the target addresses match the address values of the referenced symbols.

LGTM; thanks!

llvm/lib/MC/XCOFFObjectWriter.cpp

void XCOFFObjectWriter::recordRelocation(MCAssembler &Asm,
   assert((Fixup.getOffset() <=
           MaxRawDataSize - Layout.getFragmentOffset(Fragment)) &&
          "Fragment offset + fixup offset is overflowed.");
   uint32_t FixupOffsetInCsect =
       Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
 
   const uint32_t Index = getIndex(SymA, SymASec);
   if (Type == XCOFF::RelocationType::R_POS ||
-      Type == XCOFF::RelocationType::R_TLS)
+      Type == XCOFF::RelocationType::R_TLS ||
+      Type == XCOFF::RelocationType::R_TLS_LE)
     // The FixedValue should be symbol's virtual address in this object file
     // plus any constant value that we might get.
     FixedValue = getVirtualAddress(SymA, SymASec) + Target.getConstant();
   else if (Type == XCOFF::RelocationType::R_TLSM)
     // The FixedValue should always be zero since the region handle is only
     // known at load time.
     FixedValue = 0;
   else if (Type == XCOFF::RelocationType::R_TOC ||

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN:     -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
 
 @ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8
 @VarInit = global i64 87, align 8
 @IThreadLocalVarUninit = internal thread_local(localexec) global i64 0, align 8
+@IThreadLocalVarUninit2 = internal thread_local(localexec) global i64 0, align 8
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
 
 define void @storeITLUninit(i64 noundef %x) {
 entry:
   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
   store i64 %x, ptr %0, align 8
   ret void
 }
 
 define i64 @loadTLInit() {
 entry:
   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
   %1 = load i64, ptr %0, align 8
   %2 = load i64, ptr @VarInit, align 8
   %add = add nsw i64 %2, %1
   ret i64 %add
 }
 
+define signext i64 @loadTLUninit() {
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  store i64 1, ptr %0, align 8
+  %1 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit2)
+  %2 = load i64, ptr %1, align 8
+  %add = add nsw i64 %2, 1
+  ret i64 %add
+}
+
 ; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
 ; RELOC-NEXT: Format: aix5coff64-rs6000
 ; RELOC-NEXT: Arch: powerpc64
 ; RELOC-NEXT: AddressSize: 64bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x2
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (15)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x6
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (15)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (17)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x1A
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (17)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0x68
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (23)
+; RELOC:       Virtual Address: 0x36
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (25)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCU (0x30)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x42
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (25)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCL (0x31)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xA8
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (29)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0x70
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC:       Virtual Address: 0xB0
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (27)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 64
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xC0
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (31)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 
 ; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o
 ; SYM-NEXT: Format: aix5coff64-rs6000
 ; SYM-NEXT: Arch: powerpc64
 ; SYM-NEXT: AddressSize: 64bit
 ; SYM-NEXT: Symbols [
-; SYM:     Index: 15
+; SYM:     Index: 19
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
-; SYM-NEXT:     Value (RelocatableAddress): 0x68
+; SYM-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 16
+; SYM-NEXT:       Index: 20
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 17
+; SYM:     Index: 21
 ; SYM-NEXT:     Name: ThreadLocalVarInit
-; SYM-NEXT:     Value (RelocatableAddress): 0x70
+; SYM-NEXT:     Value (RelocatableAddress): 0xB0
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 22
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM:     Index: 25
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0xC0
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 18
+; SYM-NEXT:       Index: 26
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 21
+; SYM:     Index: 27
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 22
+; SYM-NEXT:       Index: 28
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 23
+; SYM:     Index: 29
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x8
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 24
+; SYM-NEXT:       Index: 30
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 31
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0x10
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 32
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o:  file format aix5coff64-rs6000
 ; DIS:      Disassembly of section .text:
 ; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 15) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 15) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stdx 3, 13, 4
 ; DIS-NEXT:                                       blr
 ; DIS:      0000000000000010 (idx: 5) .loadTLInit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 17) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 19) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 23) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 8(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 17) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 16(4)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 19) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 23) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ldx 3, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 0(4)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
+; DIS:      0000000000000030 (idx: 7) .loadTLUninit:
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 25) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                li 5, 1
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 3, 0(3)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 19) IThreadLocalVarUninit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ld 4, 24(4)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 25) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stdx 5, 13, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                ldx 3, 13, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addi 3, 3, 1
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      0000000000000030 (idx: 7) VarInit[RW]:
-; DIS-NEXT:       30: 00 00 00 00
-; DIS-NEXT:       34: 00 00 00 57
-; DIS:      0000000000000038 (idx: 9) storeITLUninit[DS]:
-; DIS-NEXT:       38: 00 00 00 00
-; DIS-NEXT: 0000000000000038:  R_POS        (idx: 3) .storeITLUninit
-; DIS-NEXT:       3c: 00 00 00 00
-; DIS-NEXT:       40: 00 00 00 00
-; DIS-NEXT: 0000000000000040:  R_POS        (idx: 13) TOC[TC0]
-; DIS-NEXT:       44: 00 00 00 68
-; DIS:      0000000000000050 (idx: 11) loadTLInit[DS]:
-; DIS-NEXT:       50: 00 00 00 00
-; DIS-NEXT: 0000000000000050:  R_POS        (idx: 5) .loadTLInit
-; DIS-NEXT:       54: 00 00 00 10
+; DIS:      0000000000000058 (idx: 9) VarInit[RW]:
 ; DIS-NEXT:       58: 00 00 00 00
-; DIS-NEXT: 0000000000000058:  R_POS        (idx: 13) TOC[TC0]
-; DIS-NEXT:       5c: 00 00 00 68
-; DIS:      0000000000000068 (idx: 15) IThreadLocalVarUninit[TE]:
+; DIS-NEXT:       5c: 00 00 00 57
+; DIS:      0000000000000060 (idx: 11) storeITLUninit[DS]:
+; DIS-NEXT:       60: 00 00 00 00
+; DIS-NEXT: 0000000000000060:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT:       64: 00 00 00 00
 ; DIS-NEXT:       68: 00 00 00 00
-; DIS-NEXT: 0000000000000068:  R_TLS_LE     (idx: 23) IThreadLocalVarUninit[UL]
-; DIS-NEXT:       6c: 00 00 00 00
-; DIS:      0000000000000070 (idx: 17) ThreadLocalVarInit[TE]:
-; DIS-NEXT:       70: 00 00 00 00
-; DIS-NEXT: 0000000000000070:  R_TLS_LE     (idx: 21) ThreadLocalVarInit[TL]
-; DIS-NEXT:       74: 00 00 00 00
-; DIS:      0000000000000078 (idx: 19) VarInit[TE]:
+; DIS-NEXT: 0000000000000068:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT:       6c: 00 00 00 a8
+; DIS:      0000000000000078 (idx: 13) loadTLInit[DS]:
 ; DIS-NEXT:       78: 00 00 00 00
-; DIS-NEXT: 0000000000000078:  R_POS        (idx: 7) VarInit[RW]
-; DIS-NEXT:       7c: 00 00 00 30
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT:       7c: 00 00 00 10
+; DIS-NEXT:       80: 00 00 00 00
+; DIS-NEXT: 0000000000000080:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT:       84: 00 00 00 a8
+; DIS:      0000000000000090 (idx: 15) loadTLUninit[DS]:
+; DIS-NEXT:       90: 00 00 00 00
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 7) .loadTLUninit
+; DIS-NEXT:       94: 00 00 00 30
+; DIS-NEXT:       98: 00 00 00 00
+; DIS-NEXT: 0000000000000098:  R_POS        (idx: 17) TOC[TC0]
+; DIS-NEXT:       9c: 00 00 00 a8
+; DIS:      00000000000000a8 (idx: 19) IThreadLocalVarUninit[TE]:
+; DIS-NEXT:       a8: 00 00 00 00
+; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 29) IThreadLocalVarUninit[UL]
+; DIS-NEXT:       ac: 00 00 00 08
+; DIS:      00000000000000b0 (idx: 21) ThreadLocalVarInit[TE]:
+; DIS-NEXT:       b0: 00 00 00 00
+; DIS-NEXT: 00000000000000b0:  R_TLS_LE     (idx: 27) ThreadLocalVarInit[TL]
+; DIS-NEXT:       b4: 00 00 00 00
+; DIS:      00000000000000b8 (idx: 23) VarInit[TE]:
+; DIS-NEXT:       b8: 00 00 00 00
+; DIS-NEXT: 00000000000000b8:  R_POS        (idx: 9) VarInit[RW]
+; DIS-NEXT:       bc: 00 00 00 58
+; DIS:      00000000000000c0 (idx: 25) IThreadLocalVarUninit2[TE]:
+; DIS-NEXT:       c0: 00 00 00 00
+; DIS-NEXT: 00000000000000c0:  R_TLS_LE     (idx: 31) IThreadLocalVarUninit2[UL]
+; DIS-NEXT:       c4: 00 00 00 10
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      0000000000000000 (idx: 21) ThreadLocalVarInit[TL]:
+; DIS:      0000000000000000 (idx: 27) ThreadLocalVarInit[TL]:
 ; DIS-NEXT:        0: 00 00 00 00
 ; DIS-NEXT:        4: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      0000000000000008 (idx: 23) IThreadLocalVarUninit[UL]:
+; DIS:      0000000000000008 (idx: 29) IThreadLocalVarUninit[UL]:
+; DIS-NEXT: ...
+; DIS:      0000000000000010 (idx: 31) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...
 

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
 
 @ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8
 @VarInit = global i64 87, align 8
 @IThreadLocalVarUninit = internal thread_local(localexec) global i64 0, align 8
+@IThreadLocalVarUninit2 = internal thread_local(localexec) global i64 0, align 8
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
 
 define void @storeITLUninit(i64 noundef %x) {
 entry:
   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
   store i64 %x, ptr %0, align 8
   ret void
 }
 
 define i64 @loadTLInit() {
 entry:
   %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @ThreadLocalVarInit)
   %1 = load i64, ptr %0, align 8
   %2 = load i64, ptr @VarInit, align 8
   %add = add nsw i64 %2, %1
   ret i64 %add
 }
 
+define signext i64 @loadTLUninit() {
+entry:
+  %0 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit)
+  store i64 1, ptr %0, align 8
+  %1 = tail call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @IThreadLocalVarUninit2)
+  %2 = load i64, ptr %1, align 8
+  %add = add nsw i64 %2, 1
+  ret i64 %add
+}
+
 ; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o
 ; RELOC-NEXT: Format: aixcoff-rs6000
 ; RELOC-NEXT: Arch: powerpc
 ; RELOC-NEXT: AddressSize: 32bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (17)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x16
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (17)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x18
 ; RELOC-NEXT:       Symbol: .__get_tpointer (1)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 26
 ; RELOC-NEXT:       Type: R_RBA (0x18)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x4E
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (19)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCU (0x30)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x52
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (19)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOCL (0x31)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x54
 ; RELOC-NEXT:       Symbol: .__get_tpointer (1)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 26
 ; RELOC-NEXT:       Type: R_RBA (0x18)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0xB0
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (25)
+; RELOC:       Virtual Address: 0xBE
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCU (0x30)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xC2
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOCL (0x31)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x114
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (31)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 32
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 ; RELOC:     Relocation {
-; RELOC-NEXT:       Virtual Address: 0xB4
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
+; RELOC-NEXT:       Virtual Address: 0x118
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (29)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 32
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0x120
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (33)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 32
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 
 ; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o
 ; SYM-NEXT: Format: aixcoff-rs6000

 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 0
 ; SYM-NEXT:       SymbolType: XTY_ER (0x0)
 ; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 17
+; SYM:     Index: 21
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
-; SYM-NEXT:     Value (RelocatableAddress): 0xB0
+; SYM-NEXT:     Value (RelocatableAddress): 0x114
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 18
+; SYM-NEXT:       Index: 22
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 19
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: ThreadLocalVarInit
-; SYM-NEXT:     Value (RelocatableAddress): 0xB4
+; SYM-NEXT:     Value (RelocatableAddress): 0x118
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 20
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 23
+; SYM:     Index: 27
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0x120
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 28
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TE (0x16)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 29
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 24
+; SYM-NEXT:       Index: 30
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 25
+; SYM:     Index: 31
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x8
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 26
+; SYM-NEXT:       Index: 32
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 33
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0x10
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 34
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o:  file format aixcoff-rs6000
 ; DIS:      Disassembly of section .text:
 ; DIS:      00000000 (idx: 5) .storeITLUninit:
 ; DIS-NEXT:                                       mflr 0
 ; DIS-NEXT:                                       stwu 1, -32(1)
 ; DIS-NEXT:                                       stw 0, 40(1)
 ; DIS-NEXT:                                       mr 5, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 17) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 6, 0(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 17) IThreadLocalVarUninit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) IThreadLocalVarUninit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                bla 0
 ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA  (idx: 1)      .__get_tpointer[PR]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 3, 6
 ; DIS-NEXT:                                       stw 4, 4(3)
 ; DIS-NEXT:                                       stw 5, 0(3)
 ; DIS-NEXT:                                       addi 1, 1, 32
 ; DIS-NEXT:                                       lwz 0, 8(1)
 ; DIS-NEXT:                                       mtlr 0
 ; DIS-NEXT:                                       blr
 ; DIS:      00000040 (idx: 7) .loadTLInit:
 ; DIS-NEXT:                                       mflr 0
 ; DIS-NEXT:                                       stwu 1, -32(1)
 ; DIS-NEXT:                                       stw 0, 40(1)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 19) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 23) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 4, 4(3)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 19) ThreadLocalVarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 23) ThreadLocalVarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                bla 0
 ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA  (idx: 1)      .__get_tpointer[PR]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 3, 4
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 4, 4(3)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 3, 0(3)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 5, 2, 0
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 25) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 5, 8(5)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) VarInit[TE]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 25) VarInit[TE]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 6, 4(5)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 5, 0(5)
 ; DIS-NEXT:                                       addc 4, 6, 4
 ; DIS-NEXT:                                       adde 3, 5, 3
 ; DIS-NEXT:                                       addi 1, 1, 32
 ; DIS-NEXT:                                       lwz 0, 8(1)
 ; DIS-NEXT:                                       mtlr 0
 ; DIS-NEXT:                                       blr
+; DIS:      00000090 (idx: 9) .loadTLUninit:
+; DIS-NEXT:                                       mflr 0
+; DIS-NEXT:                                       stwu 1, -32(1)
+; DIS-NEXT:                                       stw 0, 40(1)
+; DIS-NEXT:                                       li 5, 1
+; DIS-NEXT:                                       li 6, 0
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 3, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 21) IThreadLocalVarUninit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 4, 0(3)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 21) IThreadLocalVarUninit[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                bla 0
+; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA  (idx: 1)      .__get_tpointer[PR]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 4, 3, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stw 5, 4(4)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                stw 6, 0(4)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                addis 4, 2, 0
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU       (idx: 27) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 4, 12(4)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL       (idx: 27) IThreadLocalVarUninit2[TE]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                add 3, 3, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 4, 4(3)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}                lwz 3, 0(3)
+; DIS-NEXT:                                       addic 4, 4, 1
+; DIS-NEXT:                                       addze 3, 3
+; DIS-NEXT:                                       addi 1, 1, 32
+; DIS-NEXT:                                       lwz 0, 8(1)
+; DIS-NEXT:                                       mtlr 0
+; DIS-NEXT:                                       blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      00000090 (idx: 9) VarInit[RW]:
-; DIS-NEXT:       90: 00 00 00 00
-; DIS-NEXT:       94: 00 00 00 57
-; DIS:      00000098 (idx: 11) storeITLUninit[DS]:
-; DIS-NEXT:       98: 00 00 00 00
-; DIS-NEXT: 00000098:  R_POS        (idx: 5) .storeITLUninit
-; DIS-NEXT:       9c: 00 00 00 b0
-; DIS-NEXT: 0000009c:  R_POS        (idx: 15) TOC[TC0]
-; DIS-NEXT:       a0: 00 00 00 00
-; DIS:      000000a4 (idx: 13) loadTLInit[DS]:
-; DIS-NEXT:       a4: 00 00 00 40
-; DIS-NEXT: 000000a4:  R_POS        (idx: 7) .loadTLInit
-; DIS-NEXT:       a8: 00 00 00 b0
-; DIS-NEXT: 000000a8:  R_POS        (idx: 15) TOC[TC0]
-; DIS-NEXT:       ac: 00 00 00 00
-; DIS:      000000b0 (idx: 17) IThreadLocalVarUninit[TE]:
-; DIS-NEXT:       b0: 00 00 00 00
-; DIS-NEXT: 000000b0:  R_TLS_LE     (idx: 25) IThreadLocalVarUninit[UL]
-; DIS:      000000b4 (idx: 19) ThreadLocalVarInit[TE]:
-; DIS-NEXT:       b4: 00 00 00 00
-; DIS-NEXT: 000000b4:  R_TLS_LE     (idx: 23) ThreadLocalVarInit[TL]
-; DIS:      000000b8 (idx: 21) VarInit[TE]:
-; DIS-NEXT:       b8: 00 00 00 90
-; DIS-NEXT: 000000b8:  R_POS        (idx: 9) VarInit[RW]
+; DIS:      000000e8 (idx: 11) VarInit[RW]:
+; DIS-NEXT:       e8: 00 00 00 00
+; DIS-NEXT:       ec: 00 00 00 57
+; DIS:      000000f0 (idx: 13) storeITLUninit[DS]:
+; DIS-NEXT:       f0: 00 00 00 00
+; DIS-NEXT: 000000f0:  R_POS        (idx: 5) .storeITLUninit
+; DIS-NEXT:       f4: 00 00 01 14
+; DIS-NEXT: 000000f4:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT:       f8: 00 00 00 00
+; DIS:      000000fc (idx: 15) loadTLInit[DS]:
+; DIS-NEXT:       fc: 00 00 00 40
+; DIS-NEXT: 000000fc:  R_POS        (idx: 7) .loadTLInit
+; DIS-NEXT:       100: 00 00 01 14
+; DIS-NEXT: 00000100:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT:       104: 00 00 00 00
+; DIS:      00000108 (idx: 17) loadTLUninit[DS]:
+; DIS-NEXT:       108: 00 00 00 90
+; DIS-NEXT: 00000108:  R_POS        (idx: 9) .loadTLUninit
+; DIS-NEXT:       10c: 00 00 01 14
+; DIS-NEXT: 0000010c:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT:       110: 00 00 00 00
+; DIS:      00000114 (idx: 21) IThreadLocalVarUninit[TE]:
+; DIS-NEXT:       114: 00 00 00 08
+; DIS-NEXT: 00000114:  R_TLS_LE     (idx: 31) IThreadLocalVarUninit[UL]
+; DIS:      00000118 (idx: 23) ThreadLocalVarInit[TE]:
+; DIS-NEXT:       118: 00 00 00 00
+; DIS-NEXT: 00000118:  R_TLS_LE     (idx: 29) ThreadLocalVarInit[TL]
+; DIS:      0000011c (idx: 25) VarInit[TE]:
+; DIS-NEXT:       11c: 00 00 00 e8
+; DIS-NEXT: 0000011c:  R_POS        (idx: 11) VarInit[RW]
+; DIS:      00000120 (idx: 27) IThreadLocalVarUninit2[TE]:
+; DIS-NEXT:       120: 00 00 00 10
+; DIS-NEXT: 00000120:  R_TLS_LE     (idx: 33) IThreadLocalVarUninit2[UL]
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      00000000 (idx: 23) ThreadLocalVarInit[TL]:
+; DIS:      00000000 (idx: 29) ThreadLocalVarInit[TL]:
 ; DIS-NEXT:        0: 00 00 00 00
 ; DIS-NEXT:        4: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      00000008 (idx: 25) IThreadLocalVarUninit[UL]:
+; DIS:      00000008 (idx: 31) IThreadLocalVarUninit[UL]:
+; DIS-NEXT: ...
+; DIS:      00000010 (idx: 33) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...
 

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
 
 @ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4
 @VarInit = global i32 87, align 4
 @IThreadLocalVarUninit = internal thread_local(localexec) global i32 0, align 4
+@IThreadLocalVarUninit2 = internal thread_local(localexec) global i32 0, align 4
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
 
 define void @storeITLUninit(i32 noundef signext %x) {
 entry:
   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
   store i32 %x, ptr %0, align 4
   ret void
 }
 
 define signext i32 @loadTLInit() {
 entry:
   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
   %1 = load i32, ptr %0, align 4
   %2 = load i32, ptr @VarInit, align 4
   %add = add nsw i32 %2, %1
   ret i32 %add
 }
 
+define signext i32 @loadTLUninit() {
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  store i32 1, ptr %0, align 4
+  %1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit2)
+  %2 = load i32, ptr %1, align 4
+  %add = add nsw i32 %2, 1
+  ret i32 %add
+}
+
 ; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o
 ; RELOC-NEXT: Format: aix5coff64-rs6000
 ; RELOC-NEXT: Arch: powerpc64
 ; RELOC-NEXT: AddressSize: 64bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0x2
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (17)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (21)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x12
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (19)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0x60
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (27)
+; RELOC:       Virtual Address: 0x36
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (27)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOC (0x3)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xA0
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (33)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 64
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xA8
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (31)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0x68
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (25)
+; RELOC:       Virtual Address: 0xB8
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (35)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 64
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 
 ; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o
 ; SYM-NEXT: Format: aix5coff64-rs6000
 ; SYM-NEXT: Arch: powerpc64
 ; SYM-NEXT: AddressSize: 64bit
 ; SYM-NEXT: Symbols [
-; SYM:     Index: 17
+; SYM:     Index: 21
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
-; SYM-NEXT:     Value (RelocatableAddress): 0x60
+; SYM-NEXT:     Value (RelocatableAddress): 0xA0
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 18
+; SYM-NEXT:       Index: 22
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 19
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: ThreadLocalVarInit
-; SYM-NEXT:     Value (RelocatableAddress): 0x68
+; SYM-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 20
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 8
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 3
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 25
+; SYM:     Index: 27
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0xB8
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 28
+; SYM-NEXT:       SectionLen: 8
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 3
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 31
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 26
-; SYM-NEXT:       ContainingCsectSymbolIndex: 23
+; SYM-NEXT:       Index: 32
+; SYM-NEXT:       ContainingCsectSymbolIndex: 29
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 0
 ; SYM-NEXT:       SymbolType: XTY_LD (0x2)
 ; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 27
+; SYM:     Index: 33
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x4
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 28
+; SYM-NEXT:       Index: 34
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 35
+; SYM-NEXT:     Name: IThreadLocalVarUninit
+; SYM-NEXT:     Value (RelocatableAddress): 0x8
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 36
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       Auxiliary Type: AUX_CSECT (0xFB)
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o:  file format aix5coff64-rs6000
 ; DIS:      Disassembly of section .text:
 ; DIS:      0000000000000000 (idx: 3) .storeITLUninit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 0(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 17) IThreadLocalVarUninit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) IThreadLocalVarUninit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 3, 13, 4
 ; DIS-NEXT:                                      blr
 ; DIS:      0000000000000010 (idx: 5) .loadTLInit:
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 8(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 19) ThreadLocalVarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) ThreadLocalVarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 16(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) VarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 25) VarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 13, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 4, 0(4)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               add 3, 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               extsw 3, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
+; DIS:      0000000000000030 (idx: 7) .loadTLUninit:
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 3, 0(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) IThreadLocalVarUninit[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               ld 4, 24(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 27) IThreadLocalVarUninit2[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               li 5, 1
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 5, 13, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 13, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               addi 3, 3, 1
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               extsw 3, 3
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      000000000000002c (idx: 9) VarInit:
-; DIS-NEXT:       2c: 00 00 00 57
-; DIS:      0000000000000030 (idx: 11) storeITLUninit[DS]:
-; DIS-NEXT:       30: 00 00 00 00
-; DIS-NEXT: 0000000000000030:  R_POS        (idx: 3) .storeITLUninit
-; DIS-NEXT:       34: 00 00 00 00
-; DIS-NEXT:       38: 00 00 00 00
-; DIS-NEXT: 0000000000000038:  R_POS        (idx: 15) TOC[TC0]
-; DIS-NEXT:       3c: 00 00 00 60
-; DIS:      0000000000000048 (idx: 13) loadTLInit[DS]:
-; DIS-NEXT:       48: 00 00 00 00
-; DIS-NEXT: 0000000000000048:  R_POS        (idx: 5) .loadTLInit
-; DIS-NEXT:       4c: 00 00 00 10
-; DIS-NEXT:       50: 00 00 00 00
-; DIS-NEXT: 0000000000000050:  R_POS        (idx: 15) TOC[TC0]
-; DIS-NEXT:       54: 00 00 00 60
-; DIS:      0000000000000060 (idx: 17) IThreadLocalVarUninit[TC]:
+; DIS:      0000000000000050 (idx: 11) VarInit:
+; DIS-NEXT:       50: 00 00 00 57
+; DIS:      0000000000000058 (idx: 13) storeITLUninit[DS]:
+; DIS-NEXT:       58: 00 00 00 00
+; DIS-NEXT: 0000000000000058:  R_POS        (idx: 3) .storeITLUninit
+; DIS-NEXT:       5c: 00 00 00 00
 ; DIS-NEXT:       60: 00 00 00 00
-; DIS-NEXT: 0000000000000060:  R_TLS_LE     (idx: 27) IThreadLocalVarUninit[UL]
-; DIS:      0000000000000068 (idx: 19) ThreadLocalVarInit[TC]:
-; DIS-NEXT:       68: 00 00 00 00
-; DIS-NEXT: 0000000000000068:  R_TLS_LE     (idx: 25) ThreadLocalVarInit
-; DIS:      0000000000000070 (idx: 21) VarInit[TC]:
+; DIS-NEXT: 0000000000000060:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT:       64: 00 00 00 a0
+; DIS:      0000000000000070 (idx: 15) loadTLInit[DS]:
 ; DIS-NEXT:       70: 00 00 00 00
-; DIS-NEXT: 0000000000000070:  R_POS        (idx: 9) VarInit
+; DIS-NEXT: 0000000000000070:  R_POS        (idx: 5) .loadTLInit
+; DIS-NEXT:       74: 00 00 00 10
+; DIS-NEXT:       78: 00 00 00 00
+; DIS-NEXT: 0000000000000078:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT:       7c: 00 00 00 a0
+; DIS:      0000000000000088 (idx: 17) loadTLUninit[DS]:
+; DIS-NEXT:       88: 00 00 00 00
+; DIS-NEXT: 0000000000000088:  R_POS        (idx: 7) .loadTLUninit
+; DIS-NEXT:       8c: 00 00 00 30
+; DIS-NEXT:       90: 00 00 00 00
+; DIS-NEXT: 0000000000000090:  R_POS        (idx: 19) TOC[TC0]
+; DIS-NEXT:       94: 00 00 00 a0
+; DIS:      00000000000000a0 (idx: 21) IThreadLocalVarUninit[TC]:
+; DIS-NEXT:       a0: 00 00 00 00
+; DIS-NEXT: 00000000000000a0:  R_TLS_LE     (idx: 33) IThreadLocalVarUninit[UL]
+; DIS:      00000000000000a8 (idx: 23) ThreadLocalVarInit[TC]:
+; DIS-NEXT:       a8: 00 00 00 00
+; DIS-NEXT: 00000000000000a8:  R_TLS_LE     (idx: 31) ThreadLocalVarInit
+; DIS:      00000000000000b0 (idx: 25) VarInit[TC]:
+; DIS-NEXT:       b0: 00 00 00 00
+; DIS-NEXT: 00000000000000b0:  R_POS        (idx: 11) VarInit
+; DIS:      00000000000000b8 (idx: 27) IThreadLocalVarUninit2[TC]:
+; DIS-NEXT:       b8: 00 00 00 00
+; DIS-NEXT: 00000000000000b8:  R_TLS_LE     (idx: 35) IThreadLocalVarUninit2[UL]
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      0000000000000000 (idx: 25) ThreadLocalVarInit:
+; DIS:      0000000000000000 (idx: 31) ThreadLocalVarInit:
 ; DIS-NEXT:        0: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      0000000000000004 (idx: 27) IThreadLocalVarUninit[UL]:
+; DIS:      0000000000000004 (idx: 33) IThreadLocalVarUninit[UL]:
+; DIS-NEXT: ...
+; DIS:      0000000000000008 (idx: 35) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...
 

llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN:     -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s
 ; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s
 
 @ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4
 @VarInit = global i32 87, align 4
 @IThreadLocalVarUninit = internal thread_local(localexec) global i32 0, align 4
+@IThreadLocalVarUninit2 = internal thread_local(localexec) global i32 0, align 4
 declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull)
 
 define void @storeITLUninit(i32 noundef signext %x) {
 entry:
   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
   store i32 %x, ptr %0, align 4
   ret void
 }
 
 define signext i32 @loadTLInit() {
 entry:
   %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @ThreadLocalVarInit)
   %1 = load i32, ptr %0, align 4
   %2 = load i32, ptr @VarInit, align 4
   %add = add nsw i32 %2, %1
   ret i32 %add
 }
 
+define signext i32 @loadTLUninit() {
+entry:
+  %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit)
+  store i32 1, ptr %0, align 4
+  %1 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @IThreadLocalVarUninit2)
+  %2 = load i32, ptr %1, align 4
+  %add = add nsw i32 %2, 1
+  ret i32 %add
+}
+
 ; RELOC:      File: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o
 ; RELOC-NEXT: Format: aixcoff-rs6000
 ; RELOC-NEXT: Arch: powerpc
 ; RELOC-NEXT: AddressSize: 32bit
 ; RELOC-NEXT: Relocations [
 ; RELOC:       Virtual Address: 0xA
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (19)
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (23)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x10
 ; RELOC-NEXT:       Symbol: .__get_tpointer (1)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 26
 ; RELOC-NEXT:       Type: R_RBA (0x18)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x3A
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (21)
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (25)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 16
 ; RELOC-NEXT:       Type: R_TOC (0x3)
 ; RELOC-NEXT:     }
 ; RELOC:       Virtual Address: 0x44
 ; RELOC-NEXT:       Symbol: .__get_tpointer (1)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 26
 ; RELOC-NEXT:       Type: R_RBA (0x18)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0x80
-; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (29)
+; RELOC:       Virtual Address: 0x7E
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (29)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 16
+; RELOC-NEXT:       Type: R_TOC (0x3)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xD0
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit (35)
+; RELOC-NEXT:       IsSigned: No
+; RELOC-NEXT:       FixupBitValue: 0
+; RELOC-NEXT:       Length: 32
+; RELOC-NEXT:       Type: R_TLS_LE (0x23)
+; RELOC-NEXT:     }
+; RELOC:       Virtual Address: 0xD4
+; RELOC-NEXT:       Symbol: ThreadLocalVarInit (33)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 32
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
-; RELOC:       Virtual Address: 0x84
-; RELOC-NEXT:       Symbol: ThreadLocalVarInit (27)
+; RELOC:       Virtual Address: 0xDC
+; RELOC-NEXT:       Symbol: IThreadLocalVarUninit2 (37)
 ; RELOC-NEXT:       IsSigned: No
 ; RELOC-NEXT:       FixupBitValue: 0
 ; RELOC-NEXT:       Length: 32
 ; RELOC-NEXT:       Type: R_TLS_LE (0x23)
 ; RELOC-NEXT:     }
 
 ; SYM:      File: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o
 ; SYM-NEXT: Format: aixcoff-rs6000

 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 0
 ; SYM-NEXT:       SymbolType: XTY_ER (0x0)
 ; SYM-NEXT:       StorageMappingClass: XMC_PR (0x0)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 19
+; SYM:     Index: 23
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
-; SYM-NEXT:     Value (RelocatableAddress): 0x80
+; SYM-NEXT:     Value (RelocatableAddress): 0xD0
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 20
+; SYM-NEXT:       Index: 24
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 21
+; SYM:     Index: 25
 ; SYM-NEXT:     Name: ThreadLocalVarInit
-; SYM-NEXT:     Value (RelocatableAddress): 0x84
+; SYM-NEXT:     Value (RelocatableAddress): 0xD4
 ; SYM-NEXT:     Section: .data
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 22
+; SYM-NEXT:       Index: 26
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 27
+; SYM:     Index: 29
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0xDC
+; SYM-NEXT:     Section: .data
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 30
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_SD (0x1)
+; SYM-NEXT:       StorageMappingClass: XMC_TC (0x3)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 33
 ; SYM-NEXT:     Name: ThreadLocalVarInit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x0
 ; SYM-NEXT:     Section: .tdata
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_EXT (0x2)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 28
-; SYM-NEXT:       ContainingCsectSymbolIndex: 25
+; SYM-NEXT:       Index: 34
+; SYM-NEXT:       ContainingCsectSymbolIndex: 31
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 0
 ; SYM-NEXT:       SymbolType: XTY_LD (0x2)
 ; SYM-NEXT:       StorageMappingClass: XMC_TL (0x14)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
-; SYM:     Index: 29
+; SYM:     Index: 35
 ; SYM-NEXT:     Name: IThreadLocalVarUninit
 ; SYM-NEXT:     Value (RelocatableAddress): 0x4
 ; SYM-NEXT:     Section: .tbss
 ; SYM-NEXT:     Type: 0x0
 ; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYM-NEXT:     NumberOfAuxEntries: 1
 ; SYM-NEXT:     CSECT Auxiliary Entry {
-; SYM-NEXT:       Index: 30
+; SYM-NEXT:       Index: 36
+; SYM-NEXT:       SectionLen: 4
+; SYM-NEXT:       ParameterHashIndex: 0x0
+; SYM-NEXT:       TypeChkSectNum: 0x0
+; SYM-NEXT:       SymbolAlignmentLog2: 2
+; SYM-NEXT:       SymbolType: XTY_CM (0x3)
+; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
+; SYM-NEXT:       StabInfoIndex: 0x0
+; SYM-NEXT:       StabSectNum: 0x0
+; SYM-NEXT:     }
+; SYM-NEXT:   }
+; SYM:     Index: 37
+; SYM-NEXT:     Name: IThreadLocalVarUninit2
+; SYM-NEXT:     Value (RelocatableAddress): 0x8
+; SYM-NEXT:     Section: .tbss
+; SYM-NEXT:     Type: 0x0
+; SYM-NEXT:     StorageClass: C_HIDEXT (0x6B)
+; SYM-NEXT:     NumberOfAuxEntries: 1
+; SYM-NEXT:     CSECT Auxiliary Entry {
+; SYM-NEXT:       Index: 38
 ; SYM-NEXT:       SectionLen: 4
 ; SYM-NEXT:       ParameterHashIndex: 0x0
 ; SYM-NEXT:       TypeChkSectNum: 0x0
 ; SYM-NEXT:       SymbolAlignmentLog2: 2
 ; SYM-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYM-NEXT:       StorageMappingClass: XMC_UL (0x15)
 ; SYM-NEXT:       StabInfoIndex: 0x0
 ; SYM-NEXT:       StabSectNum: 0x0
 ; SYM-NEXT:     }
 ; SYM-NEXT:   }
 
 ; DIS:      {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o:  file format aixcoff-rs6000
 ; DIS:      Disassembly of section .text:
 ; DIS:      00000000 (idx: 5) .storeITLUninit:
 ; DIS-NEXT:                                      mflr 0
 ; DIS-NEXT:                                      stwu 1, -32(1)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 5, 0(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 19) IThreadLocalVarUninit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) IThreadLocalVarUninit[TC]
 ; DIS-NEXT:                                      mr 4, 3
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               bla 0
 ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1)      .__get_tpointer[PR]
 ; DIS-NEXT:                                      stw 0, 40(1)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 4, 3, 5
 ; DIS-NEXT:                                      addi 1, 1, 32
 ; DIS-NEXT:                                      lwz 0, 8(1)
 ; DIS-NEXT:                                      mtlr 0
 ; DIS-NEXT:                                      blr
 ; DIS:      00000030 (idx: 7) .loadTLInit:
 ; DIS-NEXT:                                      mflr 0
 ; DIS-NEXT:                                      stwu 1, -32(1)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 4, 4(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 21) ThreadLocalVarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 25) ThreadLocalVarInit[TC]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 5, 8(2)
-; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) VarInit[TC]
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 27) VarInit[TC]
 ; DIS-NEXT:                                      stw 0, 40(1)
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               bla 0
 ; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1)      .__get_tpointer[PR]
 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 3, 4
 ; DIS-NEXT:                                      lwz 4, 0(5)
 ; DIS-NEXT:                                      add 3, 4, 3
 ; DIS-NEXT:                                      addi 1, 1, 32
 ; DIS-NEXT:                                      lwz 0, 8(1)
 ; DIS-NEXT:                                      mtlr 0
 ; DIS-NEXT:                                      blr
+; DIS:      00000070 (idx: 9) .loadTLUninit:
+; DIS-NEXT:                                      mflr 0
+; DIS-NEXT:                                      stwu 1, -32(1)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 4, 0(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 23) IThreadLocalVarUninit[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwz 5, 12(2)
+; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC        (idx: 29) IThreadLocalVarUninit2[TC]
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               bla 0
+; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1)      .__get_tpointer[PR]
+; DIS-NEXT:                                      li 6, 1
+; DIS-NEXT:                                      stw 0, 40(1)
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               stwx 6, 3, 4
+; DIS-NEXT: [[#%x, ADDR:]]: {{.*}}               lwzx 3, 3, 5
+; DIS-NEXT:                                      addi 3, 3, 1
+; DIS-NEXT:                                      addi 1, 1, 32
+; DIS-NEXT:                                      lwz 0, 8(1)
+; DIS-NEXT:                                      mtlr 0
+; DIS-NEXT:                                      blr
 
 ; DIS:      Disassembly of section .data:
-; DIS:      00000064 (idx: 11) VarInit:
-; DIS-NEXT:       64: 00 00 00 57
-; DIS:      00000068 (idx: 13) storeITLUninit[DS]:
-; DIS-NEXT:       68: 00 00 00 00
-; DIS-NEXT: 00000068:  R_POS        (idx: 5) .storeITLUninit
-; DIS-NEXT:       6c: 00 00 00 80
-; DIS-NEXT: 0000006c:  R_POS        (idx: 17) TOC[TC0]
-; DIS-NEXT:       70: 00 00 00 00
-; DIS:      00000074 (idx: 15) loadTLInit[DS]:
-; DIS-NEXT:       74: 00 00 00 30
-; DIS-NEXT: 00000074:  R_POS        (idx: 7) .loadTLInit
-; DIS-NEXT:       78: 00 00 00 80
-; DIS-NEXT: 00000078:  R_POS        (idx: 17) TOC[TC0]
-; DIS-NEXT:       7c: 00 00 00 00
-; DIS:      00000080 (idx: 19) IThreadLocalVarUninit[TC]:
-; DIS-NEXT:       80: 00 00 00 00
-; DIS-NEXT: 00000080:  R_TLS_LE     (idx: 29) IThreadLocalVarUninit[UL]
-; DIS:      00000084 (idx: 21) ThreadLocalVarInit[TC]:
-; DIS-NEXT:       84: 00 00 00 00
-; DIS-NEXT: 00000084:  R_TLS_LE     (idx: 27) ThreadLocalVarInit
-; DIS:      00000088 (idx: 23) VarInit[TC]:
-; DIS-NEXT:       88: 00 00 00 64
-; DIS-NEXT: 00000088:  R_POS        (idx: 11) VarInit
+; DIS:      000000a8 (idx: 13) VarInit:
+; DIS-NEXT:       a8: 00 00 00 57
+; DIS:      000000ac (idx: 15) storeITLUninit[DS]:
+; DIS-NEXT:       ac: 00 00 00 00
+; DIS-NEXT: 000000ac:  R_POS        (idx: 5) .storeITLUninit
+; DIS-NEXT:       b0: 00 00 00 d0
+; DIS-NEXT: 000000b0:  R_POS        (idx: 21) TOC[TC0]
+; DIS-NEXT:       b4: 00 00 00 00
+; DIS:      000000b8 (idx: 17) loadTLInit[DS]:
+; DIS-NEXT:       b8: 00 00 00 30
+; DIS-NEXT: 000000b8:  R_POS        (idx: 7) .loadTLInit
+; DIS-NEXT:       bc: 00 00 00 d0
+; DIS-NEXT: 000000bc:  R_POS        (idx: 21) TOC[TC0]
+; DIS-NEXT:       c0: 00 00 00 00
+; DIS:      000000c4 (idx: 19) loadTLUninit[DS]:
+; DIS-NEXT:       c4: 00 00 00 70
+; DIS-NEXT: 000000c4:  R_POS        (idx: 9) .loadTLUninit
+; DIS-NEXT:       c8: 00 00 00 d0
+; DIS-NEXT: 000000c8:  R_POS        (idx: 21) TOC[TC0]
+; DIS-NEXT:       cc: 00 00 00 00
+; DIS:      000000d0 (idx: 23) IThreadLocalVarUninit[TC]:
+; DIS-NEXT:       d0: 00 00 00 04
+; DIS-NEXT: 000000d0:  R_TLS_LE     (idx: 35) IThreadLocalVarUninit[UL]
+; DIS:      000000d4 (idx: 25) ThreadLocalVarInit[TC]:
+; DIS-NEXT:       d4: 00 00 00 00
+; DIS-NEXT: 000000d4:  R_TLS_LE     (idx: 33) ThreadLocalVarInit
+; DIS:      000000d8 (idx: 27) VarInit[TC]:
+; DIS-NEXT:       d8: 00 00 00 a8
+; DIS-NEXT: 000000d8:  R_POS        (idx: 13) VarInit
+; DIS:      000000dc (idx: 29) IThreadLocalVarUninit2[TC]:
+; DIS-NEXT:       dc: 00 00 00 08
+; DIS-NEXT: 000000dc:  R_TLS_LE     (idx: 37) IThreadLocalVarUninit2[UL]
 
 ; DIS:      Disassembly of section .tdata:
-; DIS:      00000000 (idx: 27) ThreadLocalVarInit:
+; DIS:      00000000 (idx: 33) ThreadLocalVarInit:
 ; DIS-NEXT:        0: 00 00 00 01
 
 ; DIS:      Disassembly of section .tbss:
-; DIS:      00000004 (idx: 29) IThreadLocalVarUninit[UL]:
+; DIS:      00000004 (idx: 35) IThreadLocalVarUninit[UL]:
+; DIS-NEXT: ...
+; DIS:      00000008 (idx: 37) IThreadLocalVarUninit2[UL]:
 ; DIS-NEXT: ...