[PowerPC] Reorder setMaxAtomicSizeInBitsSupported(). NFC

[brad]

Summary

Reorder setMaxAtomicSizeInBitsSupported() in numerical and more logical order.

[MaskRay]

shouldInlineQuadwordAtomics contains a Subtarget.isPPC64() check, so this is NFC for both PPC32 and PPC64.
I wonder whether PPC32 may make shouldInlineQuadwordAtomics true in the future.

[brad]

In D155379#4503636, @MaskRay wrote:

shouldInlineQuadwordAtomics contains a Subtarget.isPPC64() check, so this is NFC for both PPC32 and PPC64.

Yes, I would expect shouldInlineQuadwordAtomics to check for the appropriate environment.

I wonder whether PPC32 may make shouldInlineQuadwordAtomics true in the future.

If that were the case I would expect shouldInlineQuadwordAtomics to check what is appropriate.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

if (!isPPC64) {
     // These libcalls are not available in 32-bit.
     setLibcallName(RTLIB::SHL_I128, nullptr);
     setLibcallName(RTLIB::SRL_I128, nullptr);
     setLibcallName(RTLIB::SRA_I128, nullptr);
     setLibcallName(RTLIB::MUL_I128, nullptr);
     setLibcallName(RTLIB::MULO_I64, nullptr);
   }
 
-  if (!isPPC64)
-    setMaxAtomicSizeInBitsSupported(32);
-  else if (shouldInlineQuadwordAtomics())
+  if (shouldInlineQuadwordAtomics())
     setMaxAtomicSizeInBitsSupported(128);
-  else
+  else if (isPPC64)
     setMaxAtomicSizeInBitsSupported(64);
+  else
+    setMaxAtomicSizeInBitsSupported(32);
 
   setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
 
   // We have target-specific dag combine patterns for the following nodes:
   setTargetDAGCombine({ISD::AND, ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL,
                        ISD::MUL, ISD::FMA, ISD::SINT_TO_FP, ISD::BUILD_VECTOR});
   if (Subtarget.hasFPCVT())
     setTargetDAGCombine(ISD::UINT_TO_FP);