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Differential D155363

[tests] precommit tests for D155350
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Authored by Allen on Jul 15 2023, 2:45 AM.

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Reviewers
nikic
Commits
rGa41e7a2a5db8: [tests] precommit tests for D155350

Diff Detail

Unit TestsFailed

TimeTest
60,040 msx64 debian > MLIR.Examples/standalone::test.toy
60,070 msx64 debian > ThreadSanitizer-x86_64.ThreadSanitizer-x86_64::restore_stack.cpp

Event Timeline

Allen created this revision.Jul 15 2023, 2:45 AM
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Allen requested review of this revision.Jul 15 2023, 2:45 AM
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Allen added a reviewer: nikic.Jul 15 2023, 2:46 AM
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Allen added a child revision: D155350: [ValueTracking] Support vscale assumes for isKnownToBeAPowerOfTwo.Jul 15 2023, 3:04 AM
nikic accepted this revision.Jul 15 2023, 3:08 AM

LGTM

This revision is now accepted and ready to land.Jul 15 2023, 3:08 AM
Harbormaster completed remote builds in B245573: Diff 540662.Jul 15 2023, 3:34 AM
This revision was landed with ongoing or failed builds.Jul 15 2023, 4:39 AM
Closed by commit rGa41e7a2a5db8: [tests] precommit tests for D155350 (authored by Allen). · Explain Why
This revision was automatically updated to reflect the committed changes.
Allen added a commit: rGa41e7a2a5db8: [tests] precommit tests for D155350.

Revision Contents

PathSize
llvm/
test/
Transforms/
InstCombine/
54 lines

Diff 540662

llvm/test/Transforms/InstCombine/rem-mul-shl.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
declare void @use8(i8) declare void @use8(i8)
declare i64 @llvm.vscale.i64()
define i8 @srem_non_matching(i8 %X, i8 %Y) { define i8 @srem_non_matching(i8 %X, i8 %Y) {
; CHECK-LABEL: @srem_non_matching( ; CHECK-LABEL: @srem_non_matching(
; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 15 ; CHECK-NEXT: [[BO0:%.*]] = mul nuw nsw i8 [[X:%.*]], 15
; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Y:%.*]], 5 ; CHECK-NEXT: [[BO1:%.*]] = mul nuw nsw i8 [[Y:%.*]], 5
; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]] ; CHECK-NEXT: [[R:%.*]] = srem i8 [[BO0]], [[BO1]]
; CHECK-NEXT: ret i8 [[R]] ; CHECK-NEXT: ret i8 [[R]]
; ;
▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]] ; CHECK-NEXT: [[R:%.*]] = urem i8 [[BO0]], [[BO1]]
; CHECK-NEXT: ret i8 [[R]] ; CHECK-NEXT: ret i8 [[R]]
; ;
%BO0 = shl nuw nsw i8 %X, %X %BO0 = shl nuw nsw i8 %X, %X
%BO1 = mul nuw nsw i8 %X, %X %BO1 = mul nuw nsw i8 %X, %X
%r = urem i8 %BO0, %BO1 %r = urem i8 %BO0, %BO1
ret i8 %r ret i8 %r
} }
; Negative test: No attribute vscale_range to indicate range
define i64 @urem_shl_vscale() {
; CHECK-LABEL: @urem_shl_vscale(
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
; CHECK-NEXT: [[REM:%.*]] = urem i64 1024, [[SHIFT]]
; CHECK-NEXT: ret i64 [[REM]]
;
%vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 2
%rem = urem i64 1024, %shift
ret i64 %rem
}
define i64 @urem_shl_vscale_range() vscale_range(1,16) {
; CHECK-LABEL: @urem_shl_vscale_range(
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
; CHECK-NEXT: [[REM:%.*]] = urem i64 1024, [[SHIFT]]
; CHECK-NEXT: ret i64 [[REM]]
;
%vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 2
%rem = urem i64 1024, %shift
ret i64 %rem
}
define i64 @urem_vscale_range() vscale_range(1,16) {
; CHECK-LABEL: @urem_vscale_range(
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
; CHECK-NEXT: [[REM:%.*]] = urem i64 1024, [[SHIFT]]
; CHECK-NEXT: ret i64 [[REM]]
;
%vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 2
%rem = urem i64 1024, %shift
ret i64 %rem
}
define i64 @urem_shl_vscale_out_of_range() vscale_range(1,16) {
; CHECK-LABEL: @urem_shl_vscale_out_of_range(
; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 20
; CHECK-NEXT: [[REM:%.*]] = urem i64 1024, [[SHIFT]]
; CHECK-NEXT: ret i64 [[REM]]
;
%vscale = call i64 @llvm.vscale.i64()
%shift = shl nuw nsw i64 %vscale, 20
%rem = urem i64 1024, %shift
ret i64 %rem
}
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